KR0137546B1 - Junction apparatus of video - Google Patents

Abstract

The present invention provides a codec means (5); Video interface means 6; ATM interface means 7; And system control means (8) for controlling the video interface means (6) and the ATM interface means (7), and for performing the B-ISDN UNI signal protocol. The present invention relates to a video matching device having an effect of providing a high quality video communication service through a B-ISDN by connecting a camera and a video casette recorder (VCR).

Description

Video Matching Device

1 is a configuration diagram of a system for a DS3 image quality communication service according to the present invention;

2 is a block diagram of a DS3-class video matching device according to the present invention.

3 is a detailed block diagram of the codec portion of FIG.

4 is a detailed block diagram of the video interface of FIG. 2;

FIG. 5 is a detailed block diagram of a connectionless communication mode interface unit of FIG.

6 is a detailed block diagram of the system control unit of FIG.

* Description of the symbols for the main parts of the drawings *

1: video camera 2: TV

3: video matching device 4: broadband integrated information network

5: DS3 codec section 6: video interface section

7: Connectionless communication mode (ATM) interface unit 8: System control unit

The present invention relates to a video matching device, and more particularly, to an apparatus for providing a matching function between a broadband integrated information network (B-ISDN) and a video input / output device.

Currently, a technology for transmitting a video signal of TV (hereinafter referred to as TV) level through B-ISDN has been researched to meet various service requirements of B-ISDN. Devices have not been announced and their need is increasingly highlighted by users who want high quality images.

Accordingly, the present invention devised in response to the above needs receives an analog video and audio signal as input, codes it into DS3 grade digital data, and then asynchronous transfer mode (hereinafter, referred to as ATM) cell. Cut into (Cell) units, map ATM cells to STM-1 (Synchronous Transfer Mode-1) frames, connect to B-ISDN, extract ATM cells from STM-1 frames received through B-ISDN, and It is an object of the present invention to provide a video matching device which extracts video and audio digital data transmitted from an ATM cell, converts it into an analog video NTSC (Natural Television System Committee) signal, and matches it to a TV, which is a video output device.

In order to achieve the above object, the present invention, after the analog video, audio signal is digital video, the audio signal is encoded into a digital video, audio signal and then multiplexed, or after receiving the multiplexed signal is demultiplexed into digital video, audio signal Codec means for decoding the digital video and audio signals into analog video and audio signals; The data received from the codec means is composed of an AAL-1 (Atm Adaptation Layer-1) header and a payload, and the AAL-1 header is examined from a received ATM (Asynchronous Transfer Mode) cell. Video interface means for restoring data and transferring the data to the codec means; ATM interface means for connecting the data transmitted from the video interface means and data for processing a predetermined broadband integrated information network (B-ISDN) UNI (User Network Interface) signal to the B-ISDN; And system control means for controlling the video interface means and the ATM interface means and performing the B-ISDN UNI signal protocol.

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 1 to 6.

1 is a DS3 video matching device interconnection diagram for providing a bi-directional real-time DS3 video quality digital communication service in B-ISDN, and the system to which the present invention is applied is largely as shown in the figure. Video and audio input devices of the VTR, video and audio output devices such as a TV (2), and video and audio signals of the input device are connected to the B-ISDN (4), and the video and audio received from the B-ISDN (4). It consists of a DS3-class video matching device 3 for connecting signals to the TV 2 as an output device, and a B-ISDN 4 for transmitting video data at high speed.

2 is a detailed block diagram of a DS3-class video matching device according to an embodiment of the present invention. The DS3 codec unit 5, the video interface unit 6, the ATM interface unit 7, and the system control unit 8 are shown in FIG. Equipped.

The DS3 codec unit 5 encodes an analog signal into a digital video signal, converts the analog audio signal into a digital audio signal, and multiplexes the signal to 45 Mbit / sec, and vice versa. It demultiplexes the signal into a digital audio signal and then converts the digital video signal into an analog video signal and converts the digital audio signal into an analog audio signal.

The video interface unit 6 is a Bipolar with 3 Zero Substitution (B3ZS) type signal and configures the data received from the DS3 codec unit 5 into an ATM Adaptation Layer-1 (AAL-1) header and a payload. After passing to the interface unit 7 and checking the AAL-1 header from the received ATM cell, data is recovered from the payload and transferred to the DS3 codec 5.

The ATM interface unit 7 transmits data having an identity source bit rate transmitted from the video interface unit 6 and data for processing a B-ISDNUNI (User Network Interface) signal transmitted from the system control unit 8 through the B-ISDN. In order to transmit and receive, the Sb-1 connection point including the photoelectric conversion function and the physical layer matching function are performed according to the STM-1 frame format of 155.520 Mbps.

The system control unit 8 is equipped with a microprocessor to control the video interface unit 6 and the ATM interface unit 7 and perform the B-ISDN UNI signal protocol of the International Telecommunication Union (ITU-TS) Q.2931. .

3 is a detailed block diagram of the DS3 codec unit shown in FIG. 2, and the DS3 codec unit includes an encoder and a decoder as shown in the figure.

The encoder consists of a video analog / digital converter 9, a video compressor 10, an audio analog / digital converter 11, a video / audio multiplexer 12, and a DS3 transmission line interface 13 The decoder consists of a video digital / analog converter 14, a video expander 15, an audio digital / analog converter 16, a video / audio demultiplexer 17, and a DS3 receiver line interface 18. have.

The video analog / digital converter 9 digitalizes an analog NTSC video signal with 2D-DPCM (2 Dimensional-Differential Pulse Coded Modulation), and the video compressor 10 compresses 2D-DPCM video data in a 2: 1 band. 4 bit fixed quantization.

The video / audio multiplexer 12 multiplexes digital audio / video data into a DS3 frame structure.

The DS3 transmission line interface unit 13 is a B3ZS (Bipolar with 3 Zero Substitution) type signal that is line coded a non-return to zero (NRZ) type signal having a DS3 frame structure that is an output signal of a video / audio multiplexer. And convert it to the video interface unit 6.

FIG. 4 is a detailed block diagram of the video interface of FIG.

The video interface unit is a DS3 codec interface (I / F) unit 19, a transmitting AAL-1 data generating unit 20, a control unit 21, an ATM receiving cell fifo 22, and receiving AAL-1 data. A processing unit 23 and a clock restoring unit 24 are provided.

The B3ZS signal transmitted to the DS3 codec unit 5 is decoded by the DS3 codec interface unit 19 to generate transmission data txdata and transmission clock signals txclk. This transmission data is stored in a serial to parallel fifo of the transmission AAL-1 data generator 20 at a transmission clock of 44.736 Mbps. In addition, the transmission clock is transmitted to the clock recovery unit 24 to transmit the time information of the transmission side to the reception side.

The transmission AAL-1 data generation unit 20 reads the 44.736 Mbps bitstream stored in the first-in, first-out unit by byte unit and generates 47 octets of the AAL-1 payload. It also multiplexes with one octet of the AAL-1 header to create a 48 octet ATM payload. The ATM header data is multiplexed with the ATM header (or ATM header information) obtained from the control unit 21 to make ATM cell data, and then transferred to the ATM interface unit 7.

The control unit 21 receives the address and data signals from the system control unit 8 and the control signals of the system control unit 8 to generate control signals (transmission start signal, loopback signal, clear signal, etc.) required by the video interface unit 6. And an ATM header value such as an assigned virtual channel (VCI) to the AAL-1 data generating unit 20 and the receiving AAL-1 data processing unit 23.

The ATM receiving cell first-in-first-out machine 22 functions to store the received ATM cell from the ATM interface unit 7 in units of bytes.

The receiving AAL-1 data processor 23 reads the ATM cell stored in the ATM receiving cell first-in-first-outer 22 and checks whether it is the same as the ATM header allocated from the control unit 21, and discards the incorrect ATM payload.

The correct ATM payload is again stored through the AAL-1 header check to store only the correct AAL-1 payload in the first-in, first-out. Incorrect payloads are also discarded by the 1-bit calibration function. In addition, the time information of the transmitting side received in the AAL-1 header is transmitted to the clock restoring unit 24.

The data stored in the first-in-first-out unit reads the data in parallel / serial using a clock recovered from the clock restore unit 24 and transmits the data to the DS3 codec interface unit 19 together with the recovery clock.

The DS3 codec interface unit 19 encodes the 44.736 Mbps clock received from the clock restoring unit 24 and the data transferred to the first-in, first-out-first-out of the receiving AAL-1 data processing unit 23 by B3ZS, and the DS3 codec unit 5 To pass.

The clock recovery unit 24 is composed of a transmission clock generator and a transmission clock recovery unit.

The transmitter clock generator transmits the clock information of the transmitter to the transmitter AAL-1 data generator 20 and utilizes it in the receiver to restore the clock of the transmitter. The transmitter clock recovery unit receives the received clock information. The AAL-1 data processor 23 receives the clock of the transmitting side.

FIG. 5 is a detailed block diagram of the ATM interface unit of FIG.

The system bus connection unit 25 is based on a Motorola BME (VME) bus, which is a standard commercialization bus, and T (T) is used for information transmission of high-speed CBR (Constant Bit Rate) information in columns A and C of the user-defined area. Use a bus.

The T-bus can transmit parallel data up to 19.44M Hz for high-speed data transfer of 155.52Mbps, and it is extended to the P2 connector of the VME bus to maintain compatibility with the system using the existing VME bus specification.

The AAL transmitter 26 accesses SRAM (Static Random Access Memory) for processing variable bit rate information and high-speed first-in-first-out for accessing constant bit rate information, thereby appropriately controlling the bus master. According to ITU-T 1.363, it performs AAL transmission function for AAL1, 3/4, 5, OAM information.

The AAL receiver 27 accesses the SRAM for processing the variable bit rate information and the T bus area for processing the constant bit rate information, and according to appropriate control of the bus master, AAL-1, 3/4, 5 recommended by ITU-T 1.363. It performs AAL reception function for OAM information.

The physical layer unit 28 receives user information processed by the AAL transmitter in units of ATM cells, converts an electrical signal into an optical signal, and transmits the optical signal by mapping it to a 155.520 Mbps STM-1 frame format and receiving the optical cable. After converting the optical signal into an electrical signal, the clock and the registered cell information are extracted from the mixed transmitter data and provided to the AAL receiver.

6 is a detailed block diagram of the system control unit of FIG.

The central processing unit 29 used MC68030 (Clock = 32MHZ, Pin Grid Array Type), and the clock generator 30 used two real time clocks (RTC1: Minimum 0.4) using a timer inside the MC68901. us-40ms max, RTC2: 1.6us min-20sec max), a real-time clock can generate a level 6 interrupt, and RTC1 has a higher priority than RTC2.

The serial interface 31 supports two RS-232C ports using the USART of the MC68901, and the LAN interface 32 is compatible with IEEE802.3 10Base5 Type A and 10Base2 Type B. Direct Memory Access (DMA) on the board And AMD's LANCE Chip AM7990 with a 48-byte first-in, first-out buffer.

The VME bus interface 33 should be able to operate as a VME bus master and a VME bus slave, accept an extended address, and provide functions such as a VME bus arbiter and an interrupt support.

The present invention as described above is connected to the TV, video camera and VCR (Video Casette Recorder) used in the home can be provided with a high-quality video communication service through the B-ISDN.

Claims (7)

Codec that encodes analog video and audio signals into digital video and audio signals and then multiplexes them, or receives multiplexed signals and demultiplexes them into digital video and audio signals and decodes digital video and audio signals into analog video and audio signals. Means (5); After the data received from the codec means 5 is composed of AAL-1 (Atm Adaptation Layer-1) header and payload, and the AAL-1 header is examined from the received ATM (Asynchronous Transfer Mode) cell, Video interface means (6) for restoring data from the payload and transferring the data to the codec means (5); ATM interface means (7) for connecting data transmitted from said video interface means (6) and data for processing a predetermined Broadband Integrated Information Network (B-ISDN) UNI (User Network Interface) unit to the B-ISDN; And system control means (8) for controlling the video interface means (6) and the ATM interface means (7) and for performing the B-ISDN UNI signal protocol. The method according to claim 1, wherein the codec means (5) A video analog / digital converter 9 for converting a predetermined video analog signal into a video digital signal; A video compressor (10) for compressing the digital video signal at a predetermined ratio; An audio analog / digital converter 11 for converting a predetermined audio analog signal into an audio digital signal; A video / audio multiplexer (12) for multiplexing the output of the video compressor (10) and the audio digital signal into a DS3 (DS3) frame structure; DS3 transmission line interface unit converts the output signal of the video / audio multiplexer 12 into a line-coded Bipolar with 3 Zero Substitution (B3ZS) type signal and delivers the signal to the video interface means 6. And a video matching device. The video matching device as claimed in claim 2, wherein the video analog / digital converter (9) receives an analog video signal of a National Television System Committee (NTSC) system. 4. The video analog / digital converter 9 according to claim 3, It receives NTSC analog video signal and digitalizes it with 2D-DPCM (2 Dimensional-Differential Pulse Coded Modulation). The video compression unit (10) is a video matching device, characterized in that the 2D-DPCM to compress two-bit fixed quantization of the 4-bit video data. 2. The apparatus according to claim 1, wherein the video interface means (6) comprises: a controller (21) for receiving an address, a data signal and a control signal from the system control means (8) and generating a predetermined control signal including an ATM header; Decode the data received from the codec means (5) to generate a transmission data (txdata) and a transmission clock (txclk) signal, encode predetermined reception data in a predetermined form according to a predetermined recovery clock, and transmit the same to the codec means (5). A codec interface unit 19; A transmission AAL-1 data generation unit (20) which reads the bitstream of the transmission data in bytes and converts it into ATM cell data according to a control signal generated by the control unit (21) and transmits it to the ATM interface unit (7); An ATM receiving cell first-in, first-out (22) for storing the received ATM cell from the ATM interface means (7); Reads the ATM cell stored in the ATM receiver cell first-in-first-out machine 22 and checks whether it is the same as the ATM header allocated from the controller 21, discards the incorrect ATM payload, and discards the received data according to the restoration clock. A reception AAL-1 data processing unit 23 which transfers the recovery clock to the unit 19; And The transmitting AAL-1 data generating unit 20 transmits the clock information of the transmitting side, and the receiving side uses the same to restore the clock of the transmitting side, and the received clock information is used by the receiving AAL-1 data processor 23. And a clock restoring section (24) for receiving the clock from the transmission side and restoring a clock on the transmitting side. The transmission AAL-1 data generation unit 20 according to claim 5, Read the bitstream of the transmitted data in bytes to generate 47 octets of AAL-1 payload, multiplex with one octet of AAL-1 header to make 48 octets of ATM payload, and obtain from the controller 21. And an ATM cell data by multiplexing with multiple ATM headers and ATM header information. The system of claim 1, wherein the ATM interface means (7) comprises: a system bus connection portion (25) for connecting with a system bus; An AAL transmitter 26 for performing an AAL transmission function; An AAL receiving unit 27 performing an AAL receiving function; And Receives user information processed by the AAL transmitter 26 in units of ATM cells, converts an electrical signal into an optical signal, maps the signal to a predetermined format, and transmits the optical signal through an optical cable. The optical signal received through the optical cable is converted into an electrical signal. And a physical layer unit (28) for extracting clock and cell information synchronized with the data from the mixed data of the transmission unit and providing the same to the AAL receiver (27).