KR0133556B1 - Lateral insulated gated bipolar transistor - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a horizontal insulated gate bipolar transistor, wherein a horizontal insulated gate bipolar transistor integrated on an SOI substrate includes: a cathode for capturing the injected holes in order to suppress the latchup caused by the injected holes; The electrode is formed to be connected to an impurity region formed at a position closer to the region where the MOS transistor is integrated, thereby greatly reducing the holes passing through the region where the MOS transistor is integrated, thereby reducing the voltage drop caused by the hole current caused by the holes. A horizontal isolation gate bipolar transistor is provided that can significantly reduce the latch-up threshold current.

Description

Horizontal Insulated Gate Bipolar Transistor

1 is a cross-sectional view showing the structure of a conventional LIGBT integrated on an SOI substrate.

2 is an equivalent circuit diagram of the LIGBT shown in FIG.

3 is a cross-sectional view showing the structure of the LIGBT according to the present invention integrated on an SOI substrate.

4 is an equivalent circuit diagram of the LIGBT shown in FIG.

5 is a view showing a comparison of the magnitude of the latch-up generation threshold current according to the life of the carrier in the LIGBT according to the present invention and the LIGBT according to the prior art.

Figure 6 is a view showing a comparison of the value of the current density that the latch-up according to the forward voltage drop in the LIGBT according to the present invention and the LIGBT according to the prior art.

* Explanation of symbols for main parts of the drawings

10 lower silicon substrate 12 insulating film

14 N-epitaxial layer 16 anode electrode

22: cathode electrode

The present invention relates to an insulated gate bipolar transistor, and more particularly, to a horizontal insulated gated bipolar transistor (hereinafter referred to as LIGBT) integrated on a semiconductor substrate.

Recently, LIGBT, which is widely used as a power device, is a device obtained by combining the structures of a MOS transistor and a bipolar transistor, and is an excellent power device having both the ease of on / off control of the MOS transistor and the current transfer capability of the bipolar transistor. The most difficult problem in using such a LIGBT is that it is vulnerable to latchup, which limits the amount of current that can be switched without latchup.

Among the semiconductor devices of recent years, semiconductor devices using a SOI substrate having a silicon layer spaced apart from an underlying semiconductor substrate by an insulating material in bulk can obtain high reliability, fast operation speed, and easy integration. Have Insulation isolation is very excellent when SOI substrate is used. Therefore, if a power IC is formed on the SOI substrate, fast switching speed can be obtained and general logic circuit and power device operating at low voltage can be obtained. The advantage is that it can be structurally separated from each other. Accordingly, a technology of using an SOI substrate as a substrate on which LIGBT is integrated has been developed.

1 is a cross-sectional structural diagram of an LIGBT integrated on an SOI substrate according to the prior art. Referring to FIG. 1, there is shown an SOI substrate composed of an n ⁻ epilayer 14 via a silicon substrate 10 and an insulating film 12. On the main surface of the n ⁻ epitaxial layer 14, p ⁺ well 18 connected to the anode electrode 16 and p ⁺ well spaced apart from the p ⁺ well 18 by a predetermined distance are exposed. ^- well 20, and a side portion wherein the ^p-well 20 and the connection and the top surface is the cathode (cathode) electrode of p ⁺ memol-well 24 and the upper surface is the cathode electrode (22 connected to the 22 And n ⁺ source region 26 formed to be connected to the p ⁺ methwell 24 and the p ^- well 20 to form a PN junction. A gate electrode 28 spaced apart by a gate insulating film is formed over an exposed surface of n ⁺ source region 26 parallel to each other and an exposed surface of n ^- epi layer 14 of p ^- well 20. The gate electrode is insulated from the cathode by the insulating film 30. In FIG. 1, the lines from the anode electrode to the cathode electrode indicate the flow of hole current by the injected holes.

2 is an equivalent circuit diagram of FIG. In FIG. 2, Q1 is a PNP type bipolar transistor formed by p ⁺ well 18, n ^- epilayer 14, p ^- well 20 of FIG. 1, and resistor Rs is p ^- well 20 is an NPN type bipolar transistor formed by n ⁺ source region 26. T1 is ^n-voltage applied to the gate electrode 28 is formed having a channel region of the exposed surface lower portion of the well 20 in the ^upper-epi layer to the drain (14), n ⁺ source region to a source (26) p It is an N-channel MOS transistor whose turn-on or turn-off is controlled by.

The operation of FIG. 1 will be described with reference to FIG. 2. When the turn-on voltage is supplied to the gate electrode 28 to form an inversion layer below the exposed surface of the p ^- well 20, the N-channel MOS transistor T1 is turned on, so that electrons are n ⁺ source region 26 from the PNP bipolar. Q1 is driven by being injected into the n ^- epi layer 14 which is the base of the transistor Q1. At this time, holes are injected from the anode electrode 16 to which the forward bias voltage is applied to the n ⁻ epitaxial layer 14 through the p ⁺ drain region 18. By which the injection hole n ^- the minority carrier injection effect to cause the conductivity modulation (conductivity modulation) of the epilayer (14) is generated, n accordingly ^- the invention doemeun reduce the forward voltage drop of the epi layer 12 greatly It is a well-known fact known to those skilled in the art.

While the PNP type bipolar transistor is being driven, the injected holes are captured in the cathode 22 through the n ⁻ epilayer 14 and the p ⁻ well 20 in turn. As the flow to the cathode 22 via the well (20), p ^{- -} p is located at the lower hole current yen channel Mohs source and the n ⁺ source region 26 of the transistor T1 in accordance with the movement of the hole-well (20 A voltage drop occurs in the resistance Rs on the path from the to the cathode electrode 22. When the voltage drop becomes greater than the cut-in voltage (for example, 0.7 volts) of the PN junction and acts as a forward bias voltage between p ⁻ well 20 and n ⁺ source region 26, n ⁺ source region 26. from p ^- a large amount of electrons are flowing into the well (20) p ⁺ well (18) → n ^- epitaxial layer (14) → p ^- well (20) → n ⁺ composed of a source region (26) PNPN thyristor (thyristor ) Will be turned on. As a result, a latch-up phenomenon occurs in which the current channel cannot be turned off even when the turn-off voltage is applied to the gate electrode of the N-channel MOS transistor T1. Once latch-up occurs, not only the turn-off control through the gate of the MOS transistor is impossible, but excessive current flows rapidly, causing serious damage to the device itself.

Further, as shown in FIG. 1, in the case of integrating LIGBT on the SOI substrate, since the holes, the minority carriers injected from the anode, do not flow to the substrate, all flow through the resistor Rs to the cathode, thus latching up. It has the disadvantage of being more susceptible to occurrence.

In order to solve this problem, the operating current supplied from the anode side should be lowered below the threshold current value at which latch-up occurs, but in this case, the forward voltage drop generated at the n ^- epi layer increases, requiring high current switching operation. Not suitable for use as a device. According to this problem, the user may use LIGBT, which is strong against latchup, even if the user experiences the problem of large forward voltage drop, or reduces the forward voltage decrease even if the user experiences the problem of latchup. You have the disadvantage of having to use LIGBT.

In order to solve the above problems, various techniques have been developed that can suppress the occurrence of latchup when integrating LIGBT on an SOI substrate. As a representative example, a method of lowering the resistance Rs by implanting ions into a p ^- well that causes latch-up is described in PROCEDING INTERNATIONAL 5th. SYMPOSIUM ISPSD'93 is described on pages 254-258, and a method of reducing the resistance Rs by reducing the length of n ⁺ source region using silicide contact was published in 1990 by SOLID STATE ELECTRONICS, Vol. 33, No. 5, pp. 497-501, and a method of reducing the resistance of Rs by reducing the length of the n ⁺ source region using trenches was published in 1993. PROCEDING INTERNA TIONAL 5th. See pages 236-239 of SYNPOSIUM ISPSD'93.

However, according to the conventional improvement methods described above, the latch current can be increased to some extent without causing forward voltage drop, but the hole current flowing through the resistor Rs is still present. Since the limit of the generated operating current is low, a fundamental problem such as latchup occurs when the operating current increases is still not improved.

Accordingly, an object of the present invention to solve the above problems is to provide a horizontal insulated gate bipolar transistor capable of high current switching to be suitable as a separate power element.

Another object of the present invention is to provide a horizontal insulated gate bipolar transistor having a low forward voltage drop to enable high current switching.

It is still another object of the present invention to provide a horizontal insulated gate bipolar transistor having a structure capable of suppressing the occurrence of latchup when integrated on an SOI substrate.

The present invention for achieving the above object, the first conductive semiconductor substrate having a lower surface in contact with the second conductive semiconductor substrate, and the second conductive type formed on the main surface of the first conductive semiconductor substrate A first diffusion region, a second diffusion region of a first conductivity type formed in the first diffusion region, a partial surface and a gate of the first diffusion region located between the first conductive semiconductor substrate and the second diffusion region A gate electrode interposed between the insulating layer and the gate electrode, the cathode being opposite to the gate electrode and insulated from the second diffusion region, and commonly connected to a portion of the second diffusion region and a portion of the second diffusion region; A second electrode formed on the first conductive semiconductor substrate spaced a predetermined distance from an electrode connected to the cathode electrode in the first diffusion region of the second conductive type and connected to the anode electrode supplying an operating current; Degree Characterized in that the third diffusion region by a horizontal insulated gate bipolar transistor having a type.

The gate electrode is a gate of a MOS transistor whose drain and source are the first conductive semiconductor substrate and the second diffusion region, respectively, and accordingly a control voltage for controlling the turn-on or turn-off is applied. Therefore, holes injected into the first conductive semiconductor substrate through the third diffusion region have a relatively more movement path than the number of holes passing through the portion located below the second diffusion region in the first diffusion region. As the number of holes trapped in the region adjacent to the short cathode electrode increases, the amount of holes passing through the first diffusion region below the second diffusion region which provides the latch-up induction is greatly reduced. Thus, according to the present invention, there is an advantage that can integrate the LIGBT that can flow a larger current without causing the latch-up. In this case, when the SOI substrate structure is formed between the second conductive semiconductor substrate and the first conductive semiconductor substrate through an insulating film, the SOI substrate is formed on the SOI substrate according to the prior art as shown in FIG. Compared to the LIGBT, the LIGBT integrated on the SOI substrate according to the present invention has a better latchup generation suppression effect.

In addition, the present invention provides a horizontal insulated gate bipolar transistor comprising: a first conductive semiconductor substrate having a lower surface interviewed with a second conductive semiconductor substrate; and a second conductive formed on a main surface of the first conductive semiconductor substrate. The first diffusion region of the die, the second diffusion region of the first conductive type formed in the first diffusion region, and a portion of the first and second diffusion regions in the sidewall of the trench formed so as to vertically cut the first and second diffusion regions. A trench gate interposed between an end of the second diffusion region and a gate insulating film, a cathode electrode formed to be insulated from the trench gate, and commonly connected to the first and second diffusion regions, and in the opposite direction to the trench gate. And a third diffusion region of the second conductivity type formed on the first conductive semiconductor substrate spaced apart from the first diffusion region by a predetermined distance and connected to the anode electrode to which an operating current is supplied. . The trench gate acts as a gate electrode of a MOS transistor having a first conductive semiconductor substrate and a second diffusion region as a drain and a source, respectively, and thus a turn-on or turn-off control voltage is applied. A portion of the first diffusion region facing the trench gate serves as a channel region of the MOS transistor. When the channel is formed by the turn-on voltage applied to the trench gate, electrons passing through the channel region have a direction perpendicular to the main surface of the first conductive semiconductor substrate and are injected into the first conductive semiconductor substrate. The peripheral region of the first diffusion region connected to the electrode is improved to move. At this time, since the first diffusion region connected to the cathode is adjacent to the outlet side of the channel through which the electrons pass, electrons supplied through the channel from the second diffusion region are located near the first diffusion region close to the cathode. Supply is concentrated. As a result, most of the holes injected from the third diffusion region to the first conductive semiconductor substrate as the operating current is applied to the anode electrode are the first diffusion region where the electrons are concentrated to recombine with the electrons. The number of holes that are concentrated at and moved to the vicinity of the first diffusion region located below the second diffusion region is significantly reduced. Thus, the amount of holes passing through the first diffusion region below the second diffusion region, which provides the cause of the latch up, is greatly reduced. Accordingly, according to the present invention, there is an advantage in that it is possible to integrate a LIGBT capable of flowing a larger current without causing latch-up. In this case, when the SOI substrate structure is formed between the second conductive semiconductor substrate and the first conductive semiconductor substrate through an insulating film, the SOI substrate is formed on the SOI substrate according to the prior art as shown in FIG. Compared to the LIGBT, the LIGBT integrated on the SOI substrate according to the present invention has a better latchup generation suppression effect.

The present invention also provides a horizontal insulated gate bipolar transistor comprising: a first conductive semiconductor substrate having a lower surface interviewed with a second conductive semiconductor substrate; and a first conductive formed on a main surface of the first conductive semiconductor substrate. A first diffusion region of the die, a second diffusion region of the second conductivity type formed to be positioned below the first diffusion region, and having a first concentration, and a portion of the first and second diffusion regions are vertically cut A trench gate formed at an end of the first and second diffusion regions and a gate insulating layer on sidewalls of the trench, and formed at sides of the first and second diffusion regions facing the trench gate, A third diffusion region of the second conductivity type having a second concentration having a high impurity concentration, a cathode electrode commonly connected to the first diffusion region and the third diffusion region, and the third in the direction opposite to the trench gate; And a fourth diffusion region of the second conductivity type formed on the first conductive semiconductor substrate spaced apart from the diffusion region by a predetermined distance and connected to the anode electrode to which an operating current is supplied.

The trench gate operates as a gate electrode of a MOS transistor having a first conductive semiconductor substrate and the first diffusion region as a drain and a source, respectively, and thus a turn-on or turn-off control voltage is applied. A portion of the second diffusion region that faces the trench gate serves as a channel region of the MOS transistor.

When the channel is formed by the turn-on voltage applied to the trench gate, electrons passing through the channel region have a direction perpendicular to the first conductive semiconductor substrate and the main surface and are injected into the first conductive semiconductor substrate. It moves toward the peripheral area of the third diffusion region connected to the electrode. At this time, since the third diffusion region connected to the cathode is adjacent to the outlet side of the channel through which the electrons pass, electrons supplied through the channel from the first diffusion region are adjacent to the third diffusion region close to the cathode. Supply is concentrated. As a result, most of the holes injected from the fourth diffusion region into the first conductive semiconductor substrate as the operating current is applied to the anode electrode are the third diffusion region where the electrons are concentrated to recombine with the electrons. The number of holes that are concentrated at and moved to the vicinity of the second diffusion region located below the first diffusion region is significantly reduced. As a result, more holes are trapped in the third diffusion region that is relatively closer than the second diffusion region. Thus, the amount of holes passing through the second diffusion region under the first diffusion region, which provides the cause of the latch up, is greatly reduced. Accordingly, according to the present invention, there is an advantage in that it is possible to integrate a LIGBT capable of flowing a larger current without causing latch-up. In this case, when the SOI substrate structure is formed between the second conductive semiconductor substrate and the first conductive semiconductor substrate through an insulating film, the SOI substrate is formed on the SOI substrate according to the prior art as shown in FIG. Compared to the LIGBT, the LIGBT integrated on the SOI substrate according to the present invention has a better latchup generation suppression effect.

That is, according to the present invention, since most of the holes injected into the semiconductor substrate have a structure in which the cathode is captured immediately without causing a voltage drop causing the latch up, a significantly improved latch-up threshold current value can be obtained. It is effective, and in particular, when integrated on an SOI substrate, there is an advantage that it is possible to obtain a LIGBT having excellent latch-up characteristics without degrading other device characteristics.

Hereinafter, to help the overall understanding of the present invention, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

In the following description, specific details such as the concentration and depth of impurities in each diffusion region, the length of the channel, the operating voltage, etc. are shown to provide a more general understanding of the present invention. It will be apparent to those skilled in the art that the present invention may be practiced without these specific details.

3 is a cross-sectional view of the LIGBT according to the present invention, in which a cross-sectional structure of a horizontal insulated gate bipolar transistor integrated in accordance with the present invention on an SOI substrate is shown. In FIG. 3, the LIGBT is integrated on the n ⁻ epitaxial layer 14 via the lower silicon substrate 10 and the insulating film 12 having a thickness of 3 mu m. Unlike the present embodiment, the same effect is obtained even when the present invention is applied to an SOI wafer in which two semiconductor substrates are bonded to each other via an insulating film. The n ⁻ epilayer 14 is doped at a concentration of 1 × 10 ¹⁵ / cm ³ and has a thickness of 8 μm. The third diffusion region 32 and also the p-type impurity, which are spaced 50 m apart from each other on the main surface of the n ⁻ epitaxial layer 14 and doped with a p-type impurity at a concentration of 2 × 10 ¹⁷ / cm ³ A fourth diffusion region 34 doped to a concentration of 10 ¹⁸ / cm ³ is formed.

The third diffusion region 32 is connected to the cathode electrode 22 and the fourth diffusion region 34 is connected to the anode electrode 16. The fourth diffusion region 34 is a means for providing an operating current when the PN junction with the n ⁻ epilayer 14 is forward biased by the voltage supplied from the anode electrode 16, wherein the fourth diffusion region ( Holes 34 are injected into the n ⁻ epilayer 14. The bottom of the fourth diffusion region 34 has a depth of 4 μm from the main surface of the N-epitaxial layer 14. The third diffusion region 32 is connected to the cathode electrode 22, which is a passage through which the operating current supplied through the n ⁻ epilayer 14 is output under specific conditions to be described later, and to the n ⁻ epilayer 14. The injected holes are the passages that are captured. The bottom of the third diffusion region 32 has a depth of 2.5 μm from the main surface.

The third diffusion region 32 is connected to the cathode electrode 22 in a direction opposite to the fourth diffusion region 34 and has a connection surface with the third diffusion region 32 and has n-type impurities 1. A first diffusion region 36 doped at a concentration of 10 ¹⁹ / cm ³ , and a lower portion of the source region 36 and the first diffusion region 36 and the third diffusion region 32 A second diffusion region 38 having a connection surface and doped with p-type impurities at a concentration of 2x10 ¹⁷ / cm ³ is formed. The first diffusion region 36 has a length of 2.7 μm and a depth of 1 μm. The bottom surface of the second diffusion region 38 has a depth of at least 4 μm from the main surface of the first diffusion region 36. In the opposite direction of the side portion of the first diffusion region 38 which is connected to the third diffusion region 32, the first diffusion region 38 is downward in a direction perpendicular to the main surface of the n ⁻ epitaxial layer 14 spaced apart by the gate insulating film 40. An extended trench gate 42 is formed. The trench gate 42 may be formed by etching the side portions of the first and second diffusion regions 36 and 38 to form a trench, depositing a gate insulating layer 40 and depositing a conductive layer such as polysilicon and then patterning the trench. Can be. In this embodiment, the gate insulating film 40 was formed to have a thickness of 1000 Å, and the channel length was 2 μm. Therefore, the first diffusion region 32 and the n ⁻ epitaxial layer 14 are respectively source and drain, and an inversion layer is formed in the second diffusion region 38 by a voltage applied to the trench gate 42. An N-channel MOS transistor is formed in which a current path between the drain and the source is formed.

In FIG. 3, lines directed from the anode electrode 16 to the cathode electrode 22 represent the flow of hole currents by the injected holes.

4 is an equivalent circuit diagram of the LIGBT shown in FIG. In FIG. 4, Q1 is a PNP type bipolar transistor having the fourth diffusion region 34 in FIG. 3 as an emitter, the n ⁻ epilayer 14 as a base, and the third diffusion region 32 as a collector. The bypass path in which the collector is directly connected to the cathode electrode 22 has a path connected to the cathode electrode 22 through the resistor Rs. The bypass path represents a path of a hole current flowing through the third diffusion region 32 directly to the cathode electrode 22 without passing through the second diffusion region 38, and the resistance Rs represents a second diffusion region ( It is the sum of the resistive components on the hole current path reaching the cathode electrode 22 via 38). Q2 is an NPN type bipolar transistor formed by the n ⁻ epitaxial layer 14, the third diffusion region 32, and the first diffusion region 36. T1 is turned on or off by a voltage applied to the trench gate 42 with n ⁻ epitaxial layer 14 as a drain and a first diffusion region 36 as a source and a second diffusion region 38 as a channel region. Is the N-channel MOS transistor to be controlled.

The operation of the LIGBT according to the present invention will be described with reference to FIGS. 3 and 4. When the turn-on voltage is applied to the trench gate 42, an inversion layer is formed in the second diffusion region 38 adjacent to the gate insulating layer 40, and thus an n ⁻ epitaxial layer 14 is formed from the first diffusion region 36. Flow of electrons is initiated. In this case, holes are injected through the anode electrode 16 to which the forward bias is supplied, and as a result, conductivity modulation occurs in the n ⁻ epilayer 14, thereby lowering the forward voltage drop. The holes are moved to the cathode electrode 22 side. At this time, since the third diffusion region 32 is doped at a higher concentration than the second diffusion region 38 and is at a relatively close distance, a large amount of injected holes pass through the third diffusion region 32 to form a cathode. Captured at the electrode 22. A cathode electrode (22) after the injection into the epi layer 14 ^- In addition, the electrons passing through the channel formed by the turn-on voltage applied to the trench gates having a direction perpendicular to the main surface of the semiconductor substrate n In this case, since the third diffusion region 32 connected to the cathode electrode 22 is in an adjacent position, the path of electrons is rapidly bent into the third diffusion region 32 so that the path becomes short. It becomes dark. As a result, among the holes that are injected into the n ⁻ epilayer 14 from the fourth diffusion region 34 and move toward the cathode electrode 22 as the operating current is applied to the anode electrode, the electrons are coupled to the electrons. In order to reduce the number of holes moving to the lower portion of the second diffusion region 38. Therefore, only some of the injected holes pass through the second diffusion region 38 and are captured by the cathode electrode 22. As a result, the voltage drop represented by the product of the hole current and the resistance Rs according to the flow of the holes passing through the second diffusion region 38 is greatly reduced, thereby greatly reducing the threshold current value causing the latchup. Increases. The inventors of the present application measured the latch-up generation threshold current value of each of the conventional LIGBT and the LIGBT according to the present invention manufactured under the same conditions, and the latch-up generation threshold current value of the LIGBT according to the present invention is not deteriorated. It was confirmed that the size of approximately 5 times or more than the threshold current value of the LIGBT according to the prior art.

In FIG. 3, it is more effective to form the bottom of the second diffusion region 38 at least lower than the bottom of the third diffusion region 32 to shorten the movement path of the electrons. The impurity concentration of (32) is preferably formed at least higher than the impurity concentration of the second diffusion region 38 so as to trap more holes.

5 shows a comparison of the latch-up generation threshold current value according to the life time of a carrier in the LIGBT according to the present invention and the LIGBT according to the related art. In the insulated-gate bipolar transistor, the average lifetime of the carrier is closely related to the occurrence of latch-up. As the average lifetime of the carrier increases, the ratio of holes injected from the anode to the recombination in the n ^- epi layer is small. This is because as the transport factor increases and the ratio of the hole current to the electron current increases, more hole currents pass through the resistor Rs causing the latchup. In FIG. 5, when the turn-on voltage applied to the gate is set to 10 volts and the average life of the carrier is adjusted from 0.05 k? To 10 k ?, both the LIGBT and the conventional LIGBT according to the present invention show a tendency to decrease the latch-up current. . However, it can be seen that the threshold current value at which latchup occurs is significantly higher than that of the conventional LIGBT according to the present invention. In FIG. 5, the threshold current density at which the latchup is generated in the conventional LIGBT when the average life is 0.05 ㎲ is 368 A / cm ² , while the threshold current density of the LIGBT according to the present invention is 1917 A / cm ² , approximately 5.2 times. high, whereas the average life of the 10㎲ the threshold current density of the conventional LIGBT 139A / cm ² in case the threshold current density of the LIGBT according to the invention is higher by approximately 12.3 times the 1716A / cm ^2. Therefore, according to the present invention, regardless of the average lifespan, it is approximately five times higher than that of the conventional technology, and furthermore, it is possible to obtain an excellent latch-up generation threshold current value when the average life of a carrier vulnerable to latchup is long. .

FIG. 6 shows a comparison of current density values at which latch-up occurs due to a forward voltage drop in the LIGBT according to the present invention and the LIGBT according to the related art. The measurement conditions are that the gate voltage is 15 volts and the average life of the carrier is 0.1 kW. In FIG. 6, a latch-up occurs in that a negative resistance region in which a current increases with increasing voltage and then reverses and a voltage decreases appears. It can be understood that when the latchup occurs, the current increases as the parasitic thyristor is turned on, but the voltage decreases, thereby showing a negative resistance region. In FIG. 6, the conventional LIGBT has a latchup at a current density of about 1 × 10 ⁻⁴ A / μm ² , whereas a latchup at about 6.2 × 10 ⁻⁴ A / μm ^{2 is performed} at the LIGBT according to the present invention. It can be seen that the latch-up generation threshold current of the LIGBT according to the present invention is approximately 6.2 times higher under the same conditions.

In the above-described embodiment, an example of the LIGBT for forming the trench gate integrated on the SOI substrate has been described, but this is an example in which the best effect can be obtained when the present invention is applied, and the present invention employs the SOI substrate. Even if it is applied to the LIGBT, the latch current generation threshold current can be increased. Similarly, even if the present invention is applied to a general LIGBT that does not employ the trench gate shown in FIG. 3, the latch-up generation threshold current can be increased.

As described above, according to the present invention, since the majority of the holes injected into the epi layer in the LIGBT have a structure in which the cathode is immediately trapped without causing a voltage drop causing the latch up, the latch-up threshold current value is significantly improved. There is an effect that can be obtained, and especially when integrated on the SOI substrate has the advantage that can obtain a LIGBT having excellent latch-up characteristics without deterioration of other device characteristics.

Claims (10)

A horizontal insulated gate bipolar transistor integrated on a semiconductor substrate, comprising: a first conductive semiconductor substrate having a lower surface interviewed with a second conductive semiconductor substrate, and a second formed on a main surface of the first conductive semiconductor substrate A first diffusion region of a conductivity type, a second diffusion region of a first conductivity type formed in the first diffusion region, and a first diffusion region located between the first conductive semiconductor substrate and the second diffusion region A gate electrode interposed between the partial surface and the gate insulating film, the gate electrode being opposed to the gate electrode around the second diffusion region, and formed to be insulated from each other, and common to the partial surface of the first diffusion region and the partial surface of the second diffusion region A cathode electrode connected to the second conductive semiconductor substrate spaced a predetermined distance from a side connected to the cathode electrode of the first diffusion region of the second conductive type and supplying an operating current. And a third diffusion region of a second conductivity type connected to the anode electrode. The horizontal insulating gate bipolar transistor according to claim 1, further comprising an insulating film interposed between the second conductive semiconductor substrate and the first conductive semiconductor substrate. 3. The semiconductor device of claim 1, wherein the first and third diffusion regions are regions doped with p-type impurities and the first conductive semiconductor substrate is a silicon epi layer doped with n-type impurities. Horizontal insulated gate bipolar transistor. In a horizontal insulated gate bipolar transistor, a first conductive semiconductor substrate having a lower surface in contact with a second conductive semiconductor substrate, and a first diffusion of a second conductive type formed on a main surface of the first conductive semiconductor substrate. An area, a second diffusion region of a first conductivity type formed in the first diffusion region, and a sidewall of a trench formed so that a portion of the first and second diffusion regions are vertically cut out of the first and second diffusion regions. A trench gate having an end portion and a gate insulating film interposed therebetween, a cathode electrode formed to be insulated from the trench gate and commonly connected to the first and second diffusion regions, and the first diffusion region in a direction opposite to the trench gate. And a third diffusion region of a second conductivity type formed on the first conductive semiconductor substrate spaced a predetermined distance from and connected to the anode electrode to which an operating current is supplied. Yangate bipolar transistor. The horizontal insulating gate bipolar transistor according to claim 4, further comprising an insulating film interposed between the second conductive semiconductor substrate and the second conductive semiconductor substrate. The method according to claim 4, wherein the first and third diffusion regions are regions doped with p-type impurities, and the first conductive semiconductor substrate is a silicon epitaxial doped with n-type impurities. Balanced insulated gate bipolar transistor. In a horizontal insulated gate bipolar transistor, a first conductive semiconductor substrate having a lower surface in contact with a second conductive semiconductor substrate and a first diffusion of a first conductive type formed on a main surface of the first conductive semiconductor substrate. A second diffusion region of a second conductivity type having a first impurity concentration and a portion of the trench formed to be cut vertically; A trench gate formed at sidewalls of the first and second diffusion regions and through the gate insulating layer, and formed at a side of the first and second diffusion regions facing the trench gate and higher than the first impurity concentration; A third diffusion region of the second conductivity type having a bi-concentration concentration, a cathode electrode commonly connected to the first diffusion region and a third diffusion region, and the third diffusion region in a direction opposite to the trench gate And a fourth diffusion region of a second conductivity type formed on the first conductive semiconductor substrate spaced a predetermined distance from and connected to an anode electrode supplied with an operating current. 8. The horizontal insulating gate bipolar transistor according to claim 7, further comprising an insulating film interposed between the second conductive semiconductor substrate and the first conductive semiconductor substrate. The method of claim 7, wherein the second to fourth diffusion regions are regions doped with p-type impurities, and the first conductive semiconductor substrate is a silicon epitaxial layer doped with n-type impurities. Balanced insulated gate bipolar transistor. 10. The horizontal insulated gate bipolar transistor of claim 8, wherein the bottom of the second diffusion region is formed at least lower than the bottom of the third diffusion region.