KR0133537B1 - Thin film transistor with dual gates - Google Patents

Thin film transistor with dual gates

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Publication number
KR0133537B1
KR0133537B1 KR1019890003759A KR890003759A KR0133537B1 KR 0133537 B1 KR0133537 B1 KR 0133537B1 KR 1019890003759 A KR1019890003759 A KR 1019890003759A KR 890003759 A KR890003759 A KR 890003759A KR 0133537 B1 KR0133537 B1 KR 0133537B1
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gate electrode
thin film
amorphous silicon
film transistor
electrode
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KR1019890003759A
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Korean (ko)
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KR900015370A (en
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안인호
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구자홍
엘지전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body

Abstract

A thin film transistor having double gate structure is disclosed. The thin film transistor comprises: a gate electrode(32a) for high voltage and a gate electrode(32b) for low voltage on a glass substrate(31) being ratio of the length between the high voltage gate electrode(32a) and the low voltage gate electrode(32b) is 1 : 10; a gate insulating layer(33), an amorphous silicon layer(34) and a passivation layer(35) sequentially formed on the double gate electrodes(32a,32b); an n+ amorphous silicon layer(36) connected to the amorphous silicon layer(34) through the passivation layer(35); and a drain electrode(37a) and a source electrode(37b) formed on the n+ amorphous silicon layer(36).

Description

이중 게이트형 박막트랜지스터Double Gate Thin Film Transistor

제1도는 일반적인 저전압용 박막트랜지스터의 단면도.1 is a cross-sectional view of a general low voltage thin film transistor.

제2도는 일반적인 고전압용 박막트랜지스터의 단면도.2 is a cross-sectional view of a general high voltage thin film transistor.

제3도는 본 발명 박막 트랜지스터의 단면도.3 is a cross-sectional view of the thin film transistor of the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

31 : 유리기판 32a : 고전압용 게이트전극31 glass substrate 32a high voltage gate electrode

32B : 저전압용 게이트전극 33 : 게이트절연층32B: low voltage gate electrode 33: gate insulating layer

34 : 아몰퍼스실리콘층 35 : 패시베이션층34: amorphous silicon layer 35: passivation layer

36 : 아몰퍼스실리콘층 37 : 드레인전극36: amorphous silicon layer 37: drain electrode

37b : 소오스전극37b: source electrode

본 발명은 2개의 게이트를 갖는 박막트랜지스터에 관한 것으로, 특히 한공정, 한기판상에 2개의 게이트를 증착하여 저전압 및 고전압양용으로 사용할 수 있게 한 이중 게이트형 박막 트랜지스터에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor having two gates, and more particularly, to a double gate type thin film transistor which can be used for both low voltage and high voltage by depositing two gates on a substrate.

일반적인 저전압용 박막 트랜지스터는 제1도에 도시한 바와 같이, 유리기판(1)상부에 금속박막이 전자빔(Electron Beam)으로 증착한 뒤 패터닝되어 게이트전극(2)이 형성되고, 그 게이트전극(2)상부에 실리콘나이트라이드로 게이트절연층(3)이 형성되며, 이 게이트절연층(3) 상부에 PE-CVD(Plasma Enhanced Chemical Vapor Deposition)법으로 아몰퍼스실리콘층(4)이 형성된다.In a typical low voltage thin film transistor, as shown in FIG. 1, a metal thin film is deposited on an upper surface of the glass substrate 1 with an electron beam and then patterned to form a gate electrode 2, and the gate electrode 2 The gate insulating layer 3 is formed on the upper portion of the gate insulating layer 3 using silicon nitride, and the amorphous silicon layer 4 is formed on the gate insulating layer 3 by the PE-CVD (Plasma Enhanced Chemical Vapor Deposition) method.

이어서 상기 게이트전극(2)을 중심으로 양측면에 드레인전극(7a)과 소오스전극(7b)이 형성되며, 그 드레인전극(7a)과 상기 아몰퍼스실리콘층(4) 사이에 아몰퍼스실리콘층(6)이 형성되고, 아울러 소오스전극(7b)과 아몰퍼스실리콘층(4)사이에도 아몰퍼스실리콘층(6)이 형성되어 있으며, 상기 아몰퍼스실리콘층(4)이 공기에 노출되는 것을 방지하기 위해 그 아몰퍼스실리콘층(4) 상부에 실리콘 나이트라이드로 된 패시베이션(Passi vation)층(4)이 형성되어 이루어졌다.A drain electrode 7a and a source electrode 7b are formed on both sides of the gate electrode 2, and an amorphous silicon layer 6 is formed between the drain electrode 7a and the amorphous silicon layer 4. In addition, an amorphous silicon layer 6 is formed between the source electrode 7b and the amorphous silicon layer 4, and the amorphous silicon layer 4 is formed to prevent the amorphous silicon layer 4 from being exposed to air. 4) A passivation layer 4 made of silicon nitride was formed on top.

이와 같이 이루어진 박막트랜지스터는 게이트전극(2)에 낮은 전압(2-4V)를 인가하면 이 게이트전극(2)에서 발생되는 전계가 드레인전극(7a)과 소오스전극(7b)방향으로 거의 균일하게 작용되기 때문에 드레인전극(7a)과 소오스전극(7b) 사이의 아몰퍼스실리콘층(4)은 전도 채널이 형성되어 저전압용 전계효과트랜지스터로 동작된다.In the thin film transistor formed as described above, when a low voltage (2-4V) is applied to the gate electrode 2, the electric field generated from the gate electrode 2 almost uniformly acts in the direction of the drain electrode 7a and the source electrode 7b. Therefore, the amorphous silicon layer 4 between the drain electrode 7a and the source electrode 7b is formed with a conduction channel to operate as a low voltage field effect transistor.

한편, 일반적인 고전압용 박막 트랜지스터는 제2도에 도시한 바와 같이, 유리기관(11) 상부에 게이트전극(12) 및 게이트절연층(13), 아몰퍼스실리콘층(14), 패시베이션층(15)이 순차적층되고, 게이트전극쪽과 다른한편의 패시베이션층(15)이 선택식각되어 아몰퍼스실리콘층(16)이 형성되며, 이 아몰퍼스실리콘층(16) 상부에 금속으로된 드레인전극(na)과 소오스전극(nb)이 각기 증착되어 이루어졌다.On the other hand, in the general high voltage thin film transistor, as shown in FIG. 2, the gate electrode 12, the gate insulating layer 13, the amorphous silicon layer 14, and the passivation layer 15 are formed on the glass tube 11. The passivation layer 15 on the other side of the gate electrode side is sequentially etched to form an amorphous silicon layer 16. The drain electrode na and the source electrode made of metal are formed on the amorphous silicon layer 16. (nb) was deposited respectively.

이와 같이 이루어진 박막트랜지스터는 게이트전극(12)에 소정의 전압(2-10V)이 인가되면 이 게이트전극(12)에서 발생되는 전계가 거의 전부 소오스전극(17b)쪽으로 가기 때문에 수-수십볼트의 낮은 드레인 전압에서는 전도채널이 형성되지 않게 되지만, 이때 드레인전극(17a)에 수백볼트의 고전압이 인가되면 드레인전극(17a)에서 발생되는 전계가 소오스전극(17b)까지 영향을 미쳐서 그 드레인전극(17a)과 소오스전극(17b)사이에 전도채널이 형성되어 고전압용 전계 효과 트랜지스터로 동작하게 된다.In this thin film transistor, when a predetermined voltage (2-10V) is applied to the gate electrode 12, almost all of the electric field generated by the gate electrode 12 goes toward the source electrode 17b. At the drain voltage, the conductive channel is not formed. However, when a high voltage of several hundred volts is applied to the drain electrode 17a, the electric field generated at the drain electrode 17a affects the source electrode 17b and the drain electrode 17a. A conduction channel is formed between the and source electrodes 17b to operate as a high voltage field effect transistor.

그러나 이와 같이 일반적인 박막트랜지스터는 드레인전압에 따라 저전압용과 고전압용으로 구분되어 사용되어야 하는 문제점이 있었다.However, such a general thin film transistor has a problem in that it should be used separately for low voltage and high voltage according to the drain voltage.

본 발명은 이와 같은 문제점을 해결하기 위하여 한 공정, 한 기판상에서 저전압, 고전압용으로 사용할 수 있도록 2개의 게이트를 증착시킨 박막트랜지스터를 창안한 것으로 이를 첨부한 도면에 의하여 상세히 설명하면 다음과 같다.In order to solve this problem, the present invention has been invented a thin film transistor in which two gates are deposited so as to be used for a low voltage and a high voltage on one process and one substrate, which will be described in detail with reference to the accompanying drawings.

제3도는 본 발명 박막 트랜지스터의 단면으로서 이에 도시한 바와 같이, 유리기판(31)상부에 금속박막을 전자빔(Electron Beam)으로 증착하고, 이어서 패터닝하여 고전압용 게이트전극(32a) 및 저전압용 게이트전극(32b)을 형성하는데, 여기서 상기 저전압용 게이트전극(32b)의 길이를 고전압용 게이트전극(32a)의 길이에 비하여 10배가 되도록 패터닝한다.3 is a cross-sectional view of the thin film transistor of the present invention, as shown therein, a metal thin film is deposited on the glass substrate 31 by an electron beam, and then patterned to form a high voltage gate electrode 32a and a low voltage gate electrode. (32b), wherein the length of the low voltage gate electrode 32b is patterned to be 10 times larger than the length of the high voltage gate electrode 32a.

이후 상기 고전압용 게이트전극(32a) 및 저전압용 게이트전극(32b) 상부에 실리콘 나이트 라이드와 같은 절연물질로 게이트절연층(33)을 형성하며, 그 게이트절연층(33)상부에 PE-CVD법에 의하여 전도채널용 아몰퍼스실리콘층(34)을 형성하고, 이 아몰퍼스실리콘층(34)의 보호막으로 사용하기 위하여 그 아몰퍼스실리콘층(34)상부에 실리콘 나이트라이드를 PE-CVD법으로 증착시켜 패시베이션층(35)을 형성한다. 또 상기 고전압용 게이트전극(32b) 윗쪽 및 저전압용 게이트전극(32b) 우측모서리쪽의 상기 패시베이션층(35)을 건식식각법으로 선택에칭하여 노출된 아몰퍼스실리콘층(34) 상부에 아몰퍼스실리콘층(36)을 형성한 후 금속박막을 증착시켜 소오스전극(37b) 및 드레인전극(37a)를 형성하였다.Thereafter, a gate insulating layer 33 is formed on the high voltage gate electrode 32a and the low voltage gate electrode 32b with an insulating material such as silicon nitride, and the PE-CVD method is formed on the gate insulating layer 33. Forming an amorphous silicon layer 34 for the conductive channel, and depositing silicon nitride on the amorphous silicon layer 34 by PE-CVD to use it as a protective film of the amorphous silicon layer 34. (35) is formed. In addition, an amorphous silicon layer is formed on the exposed amorphous silicon layer 34 by selectively etching the passivation layer 35 on the upper side of the high voltage gate electrode 32b and the right edge of the low voltage gate electrode 32b. 36), a metal thin film was deposited to form a source electrode 37b and a drain electrode 37a.

이와 같이 이루어진 본 발명의 박막 트랜지스터는, 고전압용으로 사용할 때에는 저전압용 게이트전극(32b)를 접지시키고, 고전압용 게이트전극(32a)에 소정전압(2-10V)을 인가하면 그 고전압용 게이트전극(32a)에서 발생되는 전계의 대부분이 소오스전극(37b)쪽으로 가해지므로 수-수십볼트의 낮은 드레인전극(37a)의 전압에서는 전도채널이 형성되지 않으나, 이때 드레인전극(37a)에 수백볼트의 고전압을 인가하면 그 드레인전극(37a)에서 발생되는 전계가 소오스전극(37b)까지 도달하게 되어 드레인전극(37a)과 소오스전극(37b)사이에 전도채널이 형성됨에 따라 드레인전류가 흐르는 고전압용 전계효과트랜지스터로 사용할 수 있게 된다.In the thin film transistor according to the present invention, the low voltage gate electrode 32b is grounded when the high voltage gate electrode 32 is used for high voltage, and a predetermined voltage (2-10V) is applied to the high voltage gate electrode 32a. Since most of the electric field generated at 32a) is applied toward the source electrode 37b, the conduction channel is not formed at the voltage of the low drain electrode 37a of several tens of volts. When applied, the electric field generated at the drain electrode 37a reaches the source electrode 37b, and as a conduction channel is formed between the drain electrode 37a and the source electrode 37b, a high voltage field effect transistor through which drain current flows. It can be used as.

한편, 저전압용으로 사용할 때에는 고전압용 게이트전극(32a)을 접지시키고, 저전압용 게이트전극(32b)에 소정전압(2-10V)을 인가하면, 그 저전압용 게이트전극(32b)에서 발생되는 전계가 드레인전극(37a)과 소오스전극(37b)쪽으로 거의 균일하게 작용하기 때문에 이 드레인전극(37a)과 소오스전극(37b)사이의 아몰퍼스실리콘층(34)에 전도채널이 형성되고, 이때 드레인전극(37a)에 수-수십볼트의 전압을 인가하면 그 드레인전극(37a)에서 소오스전극(37b)으로 드레인전류가 흐르게 된다.On the other hand, when used for low voltage, when the high voltage gate electrode 32a is grounded and a predetermined voltage (2-10V) is applied to the low voltage gate electrode 32b, an electric field generated at the low voltage gate electrode 32b is generated. Since it acts almost uniformly toward the drain electrode 37a and the source electrode 37b, a conductive channel is formed in the amorphous silicon layer 34 between the drain electrode 37a and the source electrode 37b, at which time the drain electrode 37a When a voltage of tens to tens of volts is applied, a drain current flows from the drain electrode 37a to the source electrode 37b.

이상에서 상세히 설명한 바와 같이, 본 발명은 한공정, 한 기판 상에서 제조한 박막 트랜지스터로 저전압 및 고전압용으로 사용할 수 있어 원가를 절감할 수 있는 이점이 있다.As described in detail above, the present invention is a thin film transistor manufactured on one process, one substrate can be used for low voltage and high voltage has the advantage of reducing the cost.

Claims (2)

유리기판상부에 소정의 길이 비율로 고전압용 게이트전극 및 저전압용 게이트전극이 형성되고, 상기 게이트전극의 상부에 게이트 절연층 및 아몰퍼스실리콘층, 패시베이션층이 형성되며, 그 패시베이션층이 선택식각되어 n+아몰퍼스실리콘층 및 드레인 전극, 소오스 전극이 순차 적층되어 형성된 것을 특징으로 하는 이중 게이트형 박막 트랜지스터.A high voltage gate electrode and a low voltage gate electrode are formed on the glass substrate at a predetermined length ratio, and a gate insulating layer, an amorphous silicon layer, and a passivation layer are formed on the gate electrode, and the passivation layer is selectively etched. + A double gate type thin film transistor, characterized in that the amorphous silicon layer, the drain electrode, and the source electrode are sequentially stacked. 제1항에 있어서, 고전압용 게이트 전극과 저전압용 게이트 전극(32b)은 그들 길이의 비율이 1 : 10이 되도록 형성된 것을 특징으로 하는 이중 게이트형 박막 트랜지스터.2. The double gate type thin film transistor according to claim 1, wherein the high voltage gate electrode and the low voltage gate electrode (32b) are formed such that their ratio is 1:10.
KR1019890003759A 1989-03-24 1989-03-24 Thin film transistor with dual gates KR0133537B1 (en)

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