KR0132560B1 - Dynamic semiconductor memory device - Google Patents

Abstract

It is an object of the present invention to provide a DRAM that realizes reliable operation with a small cell capacity.

The substrate region SUB of the MOS transistor is a collector base between the memory cell MC and the bit line BL constituted by the MOS transistor M1 and the capacitor C1, and the drain layer of the MOS transistor is used as a base. The bipolar transistor Q1 having an emitter connected to the bit line BL in this base layer is interposed to utilize the current amplifying action of the bipolar transistor Q1 for data reading.

Description

Dynamic Semiconductor Memory

1 is an equivalent circuit diagram showing the structure of a main DRAM part according to the first embodiment of the present invention.

2 is a diagram showing a cross-sectional structure of main parts of the first embodiment.

3 is a diagram showing characteristics of a pnp transistor in the first embodiment.

4 is a timing chart for explaining the write and read / write operations of zero data of the first embodiment.

5 is a timing chart for explaining one data write and read / write operation of the first embodiment.

6 shows a memory cell array of the first embodiment;

FIG. 7 illustrates a memory cell array in one embodiment for partitioned control of a plate. FIG.

FIG. 8 shows a memory cell array of an embodiment in which a bipolar transistor is used in two memory cells.

Figure 9 shows a memory cell array of an embodiment in which a loop bit line structure is applied to a DRAM.

FIG. 10 is an equivalent circuit diagram showing the configuration of the embodiment of FIG. 1 and the embodiment inverting the conductivity type of each part. FIG.

FIG. 11 is a timing diagram showing writing and reading / rewriting operations of zero data in the embodiment of FIG.

FIG. 12 is a timing diagram showing write and read / write operations of one data of the embodiment of FIG.

Fig. 13 is an equivalent circuit diagram showing a DRAM configuration of the embodiment which does not require plate potential control.

FIG. 14 is a diagram showing a configuration of an embodiment of a memory cell unit applied to a DRAM. FIG.

FIG. 15 is a diagram showing the configuration of the sense amplifier / restoration circuit section in the embodiment of FIG.

FIG. 16 is a timing chart for explaining the data reading operation of the embodiment of FIG.

FIG. 17 is a timing chart for explaining the data write operation of the embodiment of FIG.

18 is a sectional structural view of a main part of another embodiment.

19 is a sectional structural view of a main part of another embodiment.

20 is a sectional structural view of a main part of another embodiment.

21 is a sectional structural view of a main part of still another embodiment.

22 is a sectional structural view of a main part of another embodiment.

Fig. 23 is a sectional structural view of a main part of still another embodiment.

24 is a sectional structural view of an essential part of still another embodiment.

25 is a sectional structural view of a main part of still another embodiment.

26 is a sectional structural view of a main part of still another embodiment.

27 is a sectional structural view of a main part of another embodiment.

28 is a sectional structural view of a main part of another embodiment.

29 is a block diagram of a DRSM core circuit in an embodiment of the multi-bit bit line method.

30 is a cross-sectional configuration diagram of the memory cell of the embodiment of FIG.

FIG. 31 is a diagram for explaining writing and reading operations of the embodiment of FIG. 29; FIG.

32 is used to analytically obtain the potential difference between the bit line and the dummy bit line according to the embodiment of FIG.

FIG. 33 is a diagram illustrating the potential difference between the bit line and the dummy bit line obtained using FIG. 32 with respect to the ratio of the bit line capacity and the cell storage capacity. FIG.

34 is a diagram showing a modification of the cell configuration of FIG. 30;

35 illustrates another embodiment of lowering collector resistance.

36 illustrates another embodiment of lowering collector resistance.

FIG. 37 is a diagram showing the configuration of an embodiment in preparation for soft error and refresh. FIG.

38 is a cross-sectional view in the direction of the arrow in FIG.

FIG. 39 is a diagram showing the configuration of another embodiment for soft error and refresh. FIG.

40 is a cross-sectional view in the direction of the arrow in FIG. 39;

FIG. 41 shows a modification of the embodiment of FIG. 39; FIG.

42 is a diagram showing the configuration of another embodiment for soft error and refresh.

43 is a cross-sectional view in the direction of the arrow in FIG. 42;

FIG. 44 is a diagram showing the configuration of another embodiment for soft error and refresh.

45 shows a modification of the embodiment of FIG. 44;

46 is a block diagram of another embodiment in preparation for soft error and refresh.

47 is a block diagram of another embodiment in preparation for soft error and refresh.

FIG. 48 is a cross sectional view of a portion A-A 'of FIG. 47;

* Explanation of symbols for main parts of the drawings

1: p-type silicon engine 2: device isolation insulating film

3: gate insulating film 4: gate electrode (word line)

5: n-type drain layer (base layer) 6: n-type source layer

7: capacitor insulating film 8: plate

9: p-type emitter layer 10: bit line

31: memory cell 32: bit line control circuit

33: switching transistor 34: main word line

35: negative word line BL: bit line

/ BL: dummy bit line C1, C2: capacitor

DWL: dummy word line M1, M2: transistor gate MOS transistor

MC: memory cell MD: dummy cell

PLG: plate potential control circuit Q1, Q2: pnp transistor

RSTR: Restoration Circuit SA: Sense Amplifier Circuit

WL: word line

The present invention relates to a high density integrated dynamic semiconductor memory device (DRAM).

DRAM using a memory cell composed of one transistor / 1 capacitor has been significantly integrated due to advances in microfabrication technology. The signal read out to the bit lines in the DRAM is determined by the capacity of the capacitor C _S and the bit line capacitance C _B C ratio _S / C _B and the power source potential V _CC with. If the cell area is made small and the DRAM is highly integrated, the capacitor capacitance C _S is decreased, while the bit line capacitance C _B is increased due to the high integration. Therefore, the signal to be detected by the sense amplifier becomes smaller and becomes a problem of DRAM reliability.

Therefore, conventionally, trench capacitors, stack capacitors, and the like have been considered in order to obtain a large capacitor capacity with a small area. However, these also have a limit in increasing the capacity of the capacitor. In order to reduce the bit line capacity, a method of dividing the bit line to shorten the bit line connected to one sense amplifier is effective. However, when the number of bit line divisions increases, the number of sense amplifiers increases by that amount, resulting in an increase in chip area. Therefore, there is a limit in reducing the bit line capacity by bit line division. The higher the power source potential V _CC is, the larger the read signal is. However, since the breakdown voltage and reliability of the device decrease as the element becomes smaller, the power supply potential V _CC needs to be made smaller. Therefore, it is difficult to increase the magnitude of the signal read out to the bit line and improve the integration degree of the DRAM.

Moreover, the noise of burning a bit line with the improvement of DRAM contactability is becoming a problem. One of the bit line noises is due to capacitive coupling between bit lines. This noise becomes very large because the bit lines are arranged at a fine pitch. Another noise originates from capacitive coupling in word lines that are intersected with the bit lines. Although the wand and the bit line intersect with the interlayer insulating film interposed therebetween, the interlayer insulating film is thinned due to the improvement in the degree of integration. This is because the bit line needs to lower the aspect ratio of the contact hole as much as possible. Therefore, the amount of noise that rides bit lines from word lines increases with high integration of DRAM.

High-speed operation of the bit line sense amplifier also becomes a barrier due to the degradation of the read signal and the increase of noise accompanied with the improvement of the integration degree of DRAM. That is, the bit line sense amplifier is usually composed of flip flops. The sensitivity of the sense amplifier of this bit line is determined by the error of the threshold voltage of the MOS transistors constituting the flip flop. When a bit line sense amplifier composed of MOS transistors having an error in the threshold voltage is operated at high speed, there is a possibility that the 0 and 1 of the small signal read out to the bit line may be wrongly determined.

As described above, in the conventional DRAM, due to the high integration, the size of the signal appearing on the bit line gradually decreases due to a decrease in the capacitor capacity, an increase in the bit line capacity, a decrease in the power supply potential, and conversely, the bit line noise increases. Therefore, it is difficult to highly integrate DRAM without solving this. In addition, in order to reliably operate the bit line sense amplifier in response to the degradation of the signal read out to the bit line, there is a problem that the high speed operation of the bit line sense amplifier must be sacrificed.

It is an object of the present invention to provide a DRAM that solves this problem and can be further integrated and speeded up.

A DRAM according to the present invention has a structure in which a bipolar transistor is inserted between a drain and a bit line of a cell transistor. In an equivalent circuit, a bipolar transistor is configured in a state where a base is connected to the drain of a cell transistor, an emitter is connected to a bit line, and a collector is connected to the engine region of the cell transistor. The specific structure of the bipolar transistor has a vertical structure in which the basic region of the cell transistor is based on the collector and the drain, and the emitter is formed on the contact portion of the bit line. In other words, the present invention is a dynamic type semiconductor memory device, comprising: a semiconductor substrate, a memory cell formed of MOS transistors and capacitors arranged on the substrate, and a first conductive substrate region of the MOS transistor as a collector, and a drain as a second collector. A bipolar transistor having a conductive base and having a first conductive emitter coupled to the base, the bipolar transistor connected to the emitter of the bipolar transistor, the bit line and the gate of the MOS transistor for exchanging data with the memory cell, and the memory And a word line for driving the cell.

In addition, the present invention provides a dynamic semiconductor memory device, comprising: a semiconductor substrate having a first conductive region, a substrate, and a second conductive source and a drain formed apart from each other in the first conductive region of the substrate; A MOS transistor having a gate electrode formed on the first conductive region between these sources and drains through a gate insulating film to form a word line, a capacitor formed on a substrate using the second conductive source of the MOS transistor as one electrode; A bipolar transistor having a first conductivity type region having a MOS transistor as a collector, a second conductivity type drain as a base, and a first conductivity type emitter bonded to the base and a bit line connected to the emitter of the bipolar transistor; It is characterized by including.

In the present invention, a dynamic semiconductor memory device includes a semiconductor substrate, a memory cell formed of a first MOS transistor and a capacitor arranged on the substrate, and a drain of the first conductive substrate of the first MOS transistor. A bipolar transistor having a first conductivity type emitter bonded to the base as a second conductivity type, a bit line connected to an emitter of the bipolar transistor to exchange data with a memory cell, and a gate of the first MOS transistor; And a second MOS transistor connected to a first word line for driving a memory cell, a first word line connected to a drain, a second word line connected to a source, and a signal for selecting a bit line connected to a gate. It is characterized by.

The present invention is also characterized in that a barrier layer of a carrier is provided in a semiconductor substrate in addition to the configuration of claim 1. As the carrier barrier layer, an SOI substrate, a damage layer by high energy ion implantation, an n ⁺ type or a p ⁺ type buried layer is used. As a capacitor of the memory cell, the capacitance between the pass word line and the diffusion layer, the capacitance between the transistor isolation and the diffusion layer, and the fringe capacities or capacitances of the gate are used.

Data in the DRAM according to the present invention is read and written as follows. Consider a case where a cell transistor is an n-channel MOS transistor and a pnp transistor is formed between the drain and the bit line.

In the precharge cycle, for example, 3.3V is supplied to the bit line, which becomes the emitter potential of the pnp transistor. If 0 V (0 data) is held in the capacitor, it is supplied to the base when the cell transistor is turned on, the pnp transistor is turned on, and the collector current flows to discharge the bit line charge. On the other hand, when 3.3 V (1 data) is held in the capacitor, the pnp transistor is not turned on and the bit line charge is not discharged even when the cell transistor is turned on. Data 0 and 1 are determined depending on whether or not bit lines are discharged by the pnp transistor.

The bipolar transistor operation is not used for data writing. When 1 data is supplied to the bit line while the cell transistor is on, 1 data is written to the capacitor by the forward current between the pnp transistor base and emitter. When 0 data is supplied to the bit line, the base emitter of the pnp transistor is supplied. Zero data is written to the capacitor by the reverse breakdown current between the capacitors. At this time, however, it is better to control the plate potential of the capacitor at the same time in order to ensure more data writing.

As described above, in the present invention, the data readout detects a change in the bit line potential by using the storage amplification action of the bipolar transistor. Therefore, even in a DRAM having a small capacitor capacity and a large bit line capacity, data can be reliably read at high speed, and the influence of noise is relatively reduced. In addition, by reducing the number of sense amplifiers activated at one time, the power consumption of the chip can be reduced.

In addition, an SOI substrate serving as a barrier layer for carriers generated by α-rays incident on the substrate, a damage layer caused by high energy ion implantation, an n ⁺ buried layer or a p ⁺ buried layer, and the like are separated and contribute to refreshing. By using transistor isolation to suppress leakage current at the stage, C _S required by the read voltage and S / N ratio of the sense amplifier is set to almost zero, and soft errors caused by the barrier layer of the carrier on the substrate are eliminated. Therefore, C _S required is set to almost zero, and C _S required at refreshing due to transistor isolation or the like is set to almost zero. Therefore, C _S can be reduced to the limit, and the capacitor can be effectively or completely eliminated, so that the capacitor process can be very simply or completely omitted.

An embodiment of the present invention will be described below with reference to the drawings.

1 is an equivalent circuit diagram showing a configuration of a main DRAM part according to an embodiment of the present invention. Here, one sense amplifier circuit SA and a recovery circuit RSTR. A pair of bit lines BL and / BL connected to them, memory cells MC and dummy cells MD provided in the bit lines BL and / BL are shown.

The memory cell MC is composed of an n-channel MOS transistor M1 which is a cell transistor and a capacitor C1 connected thereto. The connection node SN of the MOS transistor M1 and the capacitor C1 is an accumulation node, and the other node of the capacitor C1 is a plate PL. The dummy cell MD is similarly composed of an n-channel MOS transistor M2 and a capacitor C2. The dummy cell potential setting n-channel MOS transistor M9 is connected to the accumulation node SND of the dummy cell MD. The gate of the MOS transistor M1 of the memory cell MC is connected to the word line WL, and the gate of the dummy cell MD is connected to the dummy word line DWL.

The pnp transistors Q1 and Q2 are provided between the drains of the MOS transistors M1 and M2 of the memory cell MC and the dummy cell MD and the bit lines BL and / BL, respectively. The emitters of the transistors Q1 and Q2 are connected to the bit lines BL and / BL, respectively, the base is connected to the drains of the MOS transistors M1 and M2, respectively, and the collector is the substrate of the MOS transistors M1 and M2. Is connected to (SUB). The capacitor plate PL of the memory cell MC and the dummy cell MD is provided with a plate potential control circuit PLG for supplying a predetermined clock when writing data. The plate potential control circuit PLG actually generates a clock at a predetermined timing in synchronization with the write cycle as part of the clock generation circuit in the peripheral circuit.

The bit line sense amplifier circuit SA is a flip flop composed of n-channel MOS transistors M3 and M4, and the recovery circuit RSTR is a flip flop composed of p-channel MOS transistors M5 and M6. The activation n-channel MOS transistor M7 is provided at the common source of the sense amplifier circuit SA, and the activation p-channel MOS transistor M8 is provided at the common source of the recovery circuit RSTR.

Writing n-channel MOS transistors M10 and M11 are provided at the side ends of the data input / output lines of the bit lines BL and / BL, respectively.

2 is a structural diagram of a memory cell portion of this embodiment. The gate electrode 4 is formed through the gate insulating film 3 in the region surrounded by the element isolation insulating film 2 of the p-type silicon substrate 1. The gate electrode 4 is continuously arranged in the direction perpendicular to the plane of the drawing to form the word line WL. The substrate 1 is self-aligned with the gate electrode 4 to form an n-type drain 5 and a source 6. On the source 6, the capacitor electrode 8 which becomes a common plate with respect to all the memory cells is formed through the capacitor insulating film 7. As shown in FIG.

The pnp transistor is formed in the drain portion of the memory cell structure, that is, the bit line connection portion. In other words, the p-type transistor is formed by forming the p-type emitter 9 on the n-type drain surface part with the n-type drain 5 as the base and the p-type silicon substrate 1 as the collector.

The bit line 10 is connected to the p-type emitter 9 of the pnp transistor.

3 is a base voltage-base current characteristic diagram of a pnp transistor. V _BE is the forward rise voltage of the base emitter, and BV _BE is the reverse breakdown voltage of the base emitter.

The operation of the DRAM configured as described above will be described with reference to FIGS. 4 and 5. FIG.

4 shows writing of zero data into a memory cell in which one data is stored, and a read / write operation of the written zero data. From time _t 0 to _t 1, there is a precharge cycle, during which the bit lines BL and / BL are precharged to the power source potential V _CC by a known precharge circuit (not shown). At this time, the potentials of the base nodes B1 and B2 of the pnp transistors Q1 and Q2 are V _CC -V _BE . The storage node SN of the memory cell MC is held at one data V _CC -V _BE . The accumulation node SND of the dummy cell MD is written with (1/2) V _CC through the write MOS transistor M9.

Thereafter, the gate terminal (WDC) for a dummy cell at time _t 1 the writing MOS transistor (M9) of the L level at time _t 2 the word line (WL) and a dummy word line (DWL) is raised. As a result, the MOS transistors M1 and M2 of the memory cell MC and the dummy cell MD are turned on, and the memory cell data and the dummy cell data are output to the nodes B1 and B2, respectively.

In this case, however, since the storage node SN and the base node B1 on the memory cell MC side are V _CC -V _BE , there is no change in potential of these nodes. Therefore, there is no change in potential of the bit line BL. On the other hand, since the potential of the storage node SND is (1/2) V _{CC on the} dummy cell MD side, a potential change of the base node B2 where V _BE is equal to (1/2) V _CC occurs. At this time, the potential V _B2 of the base node _B2 is as follows.

V _B2 = V _CC -V _BE- (V _CC -2V _BE ) / 2 (1 + C _BB / C _S ). . . (One)

However, C _BB is a parasitic capacitance attached to the base of the pnp transistor Q2.

When the potential of the node B2 shown in equation (1) becomes smaller than V _CC -V _BE , the pnp transistor Q2 is turned on, thereby discharging the electric charge accumulated in the dummy bit line / BL, and the potential is lowered. do. When the sense amplifier SA is activated at time _t 3, the dummy bit line / BL drops to 0V as shown by the dotted line, and at the time _t 2, the recovery circuit RSTR is activated so that the bit line BL is activated. _Becomes V _CC .

Next, at time _t 5, the control signal WGT becomes H level, and the transfer gate MOS transistors M10 and M11 are turned on. The bit line BL has write data 0 (0V) and a dummy bit line (/ BL). In reverse, data 1 (V _CC ) is transmitted from the I / O line. When the breakdown voltage between the base and emitters of the pnp transistor Q1 is set to BV _BE = (1/2) V _CC , and the potential of the base node B1 is larger than BV _BE , the base and emitter voltages of the pnp transistor Q1 are set between the base and emitters. Is yielded and the potential of the base node B1 becomes BV _BE = (1/2) V _CC .

Then, at time _t 6, the plate PL goes from (1/2) V _CC to V _CC , so that the potentials of the nodes B1 and B2 are about to rise by capacitive coupling through the capacitors C1 and C2. At this time, the node B1 side is clamped to (1/2) V _CC because the base and emitter are yielding, and only the potential on the node B2 side rises. Subsequently, when the plate PL returns from V _CC to (1/2) V _CC at time _t 7, the potential of the node B2 returns to V _CC −V _BE and the potential of the node B1 becomes 0V. That is, 0 is written in the memory cell MC.

Next, a read / write operation of zero data will be described using FIG. Time _t 8 to _t 9 are precharge cycles. In the meantime, the bit lines BL and / BL are precharged to V _CC -V _BE . At time _t 10, the word line WL and the dummy word line DWL rise, and the data of the memory cells MC and the dummy cells MD appear as base nodes B1 and B2. At this time, the potential of the node B1 is as follows.

V _B1 = V _CC -V _BE- (V _CC -V _BE ) / 2 (1 + C _BB / C _S ). . . (2)

The potential V _B2 of the node _B2 is represented by the above equation (1). Since V _B1 is smaller than V _{B2 in} these equations, the collector current of the pnp transistor Q1 on the memory cell MC side is larger than that of the pnp transistor Q2 on the dummy cell MD side, so that the potential of the bit line BL is increased. It is lower than the dummy bit line / BL.

And being at time _t 11 a sense amplifier circuit (SA) is enabled, at time _t 12 restore circuit (RSTR) is activated, the bit line (BL) is a dummy bit line (/ BL) to 0V is to V _CC. Therefore, zero data of the memory cell MC is read. At time _t 13, the plate PL goes from (1/2) V _CC to V _CC , and at time _t 14 the plate PL returns to (1/2) V _CC , the same as in the case of zero writing. 0 V, i.e., zero data, is rewritten to the accumulation node SN of the cell MC.

Next, the write and read / write operations of one data will be described with reference to FIG.

From time _t 15 to time _t 16, there is a precharge cycle, during which the bit line BL and the dummy bit line / BL are free with V _CC , and the base nodes B1 and B2 are free with V _CC -V _BE . Occupied.

The storage node SN of the memory cell MC has a potential of 0 V to which zero data is currently written, and the potential of the node SND of the dummy cell MD is (1/2) V _CC . At time _t 17, the word line WL and the dummy word line DWL rise, and the data of the memory cell MC and the dummy cell MD appear at the nodes B1 and B2, respectively. At this time, the potential V _B1 of the node _B1 is represented by equation (2), and the potential V _B2 of the node _B2 is represented by equation (1). In this case, the pnp transistor Q1 on the memory cell MC side is turned on deeper than the pnp transistor Q2 on the dummy cell MD side, and a large collector current flows so that the potential of the bit line BL is dummy. The potential of the bit line BL is lower than that of the dummy bit line / BL.

That at time _t 18 a sense amplifier circuit (SA) is enabled, at time _t 19 restore circuit (RSTR) is activated, the dummy bit line (/ BL) becomes V _CC., And the second signal (WGT) at time _t 20 0 data (0 V) opposite to the dummy bit line / BL is transmitted to one data V _CC to be written to the bit line BL and to the dummy bit line / BL. If at time _t 21 the plate PL goes from (1/2) V _CC to V _CC and the potential of the plate PL returns to (1/2) V _CC at time _t 22, the node of the dummy cell MD (SND) is 0V, and the node SN of the memory cell MC is V _CC -V _BE . Thus, one data is added to the memory cell MD.

Next, one data read / write operation will be described with reference to FIG. At time _t 13 to _t 24, the precharge cycle is performed, and the bit line BL and the dummy bit line / BL are precharged at V _CC -V _BE . At time _t 25, the word line WL and the dummy word line DWL rise, and the data of the memory cell MC and the dummy cell MD are output to the nodes B1 and B2, respectively. At this time, since the nodes SN and B1 are both V _CC -V _BE , the potential change of the node B1 and the bit line BL does not occur. The potential V _B2 of the node _B2 is represented by equation (1).

At time _t 26, the sense amplifier circuit SA is activated, and at time _t 27, the restoration circuit RSTR is activated, whereby a large collector current flows in the pnp transistor Q2 on the dummy cell MD side. With V _CC , the dummy bit line / BL becomes 0V. Therefore, one data of the memory cell MC is read out. Then, at time _t 28, the plate PL goes from (1/2) V _CC to V _CC , and at time _t 29 the plate PL regenerates to (1/2) V _CC , so that the node SND is 0 V, the node SN becomes V _CC -V _BE and the memory cell MC is rewritten.

As described above, in the present embodiment, since the operation of discharging the bit line charge on the zero side by the bipolar transistor at the time of data reading is used, data can be reliably read even if the capacitor capacity of the memory cell is small. Therefore, it is possible to achieve high integration of the DRAM without using capacitors having a complicated structure without having to store capacity.

In addition, by activating the sense amplifier circuit at high speed as in the related art, high speed read is possible without a read error, and the noise is also strong.

A concrete numerical example is given and the effect of this Example is demonstrated. In the conventional method, the signal difference ΔV appearing in the bit line and the dummy bit line is ΔV = V _CC / 2 (1 = C _B / C _S ). . . (3). When C _S = 600fF, C _S = 30fF, and V _CC = 3.3V, ΔV = 79 mV.

On the other hand, in the present embodiment, the signal difference appearing at the base of the bipolar transistor is _{ΔV B0} = V _CC / 2 (1 + C _BB / C _S ) at zero data read. . . (4)

ΔV _B1 = (V _CC −V _BE ) / 2 (1 + C _BB / C _S ) when reading 1 data. . . (5) is.

When C _BB = 10fF, C _S = 30fF, V _CC = 3.3V, and V _BE = 0.6V, ΔV _B0 = 1.2V and ΔV _B1 = 0.79V. When the performance of the bipolar transistor is sufficiently high, and the charge in which the bit line is accumulated is sufficiently high by the bipolar transistor, the difference between the two potential differences, ΔV _B0 and ΔV _B1 , becomes the potential difference between the bit lines. Therefore, sensitivity 10 times or more is obtained as compared with the conventional method.

In the above embodiment, the plate potential is clocked between (1/2) V _CC and V _CC , but the clocking potential is not limited to this. When writing the stored data and the inverse data, the clocking potential value may be set to the breakdown voltage BV _BE or more, such as the breakdown between the base emitters of the bipolar transistor by clocking.

FIG. 6 shows an overall configuration in which a cell array showing only main parts in FIG. 1 is laid out in an open bit line manner. n memory cells MC _li -MC _ni are disposed along the i-th (i = 1-m) bit lines BL and / BL, and a pnp transistor QC _li -QC _ni is disposed in each memory cell. M memory cells MC _jl -MC _jm are arranged along the j-th (j = 1-n) word line WL. The plate is shared by all memory cells in this embodiment.

FIG. 7 is a DRAM cell array of an embodiment with a slight modification of FIG. In this embodiment, the plate PL is separated for each word line WL, and the plate PL of the memory cell corresponding to one word line WL is common. When the plates are separated in this manner, the capacity of each plate is reduced, so that high speed driving of the plate potential is possible.

8 is a DRAM cell array of another embodiment. In this embodiment, two memory cells driven by adjacent word lines share one bipolar transistor. The plate may be common to all memory cells or may be divided as shown in FIG.

FIG. 9 is an embodiment in which two memory cells are laid out in a folded bit line manner while sharing one bipolar transistor. Also in this embodiment, the plate may be common to all the memory cells or may be divided as shown in FIG. In addition, it is also possible to layout in a ground bit line manner with one bipolar transistor provided in one memory cell.

10 is an embodiment in which the conductivity type of each part of the first embodiment is reversed. Parts corresponding to those in FIG. 1 are denoted by the same reference numerals as in FIG. 1, and the transistors M1 and M2 constituting the memory cell MC and the dummy cell MD are p-channel MOS transistors, and the sense amplifier circuit SA is p. The channel MOS transistors M5 and M6 are configured, and the recovery circuit RSTR is configured by the n channel MOS transistors M3 and M4. The bipolar transistors Q1 and Q2 respectively provided between the memory cell MC, the dummy cell MD, and the bit lines BL and / BL are npn transistors.

Read and write operations in the DRAM of the embodiment of FIG. 10 will be described with reference to FIGS. Here, data writing also shows the case where the stored data and the inverse data are written.

11 is a timing diagram of zero data write and read / write operations.

In the precharge cycle at time _t 0- _t 1, the bit lines BL and / BL are precharged to 0V. At this time, the base nodes B1 and B2 are precharged to V _BE . At time _t 2, the word line WL and the dummy word line DWL rise, and the data of the memory cell MC is represented by the bit line BL. At time _t 3 the sense amplifier circuit SA is activated, and at time _t 4 the restoration circuit RSTR is activated. At time _t 5, the control signal WGT rises, and data 0 (0V) is transmitted to the boot line BL, and data 1 (V _CC ) is transferred to the dummy bit line / BL. At time _t 6, the plate PL drops to 0 V at (1/2) Vcc and returns to (1/2) V _CC at time _t 7. If the breakdown voltage BV _BE between the base and emitter of the npn transistor is (1/2) V _CC , the accumulation node SND on the dummy cell MD side is V _CC in the same principle as the above embodiment, and the memory cell MC The accumulation node SN on the side becomes V _BE . This is zero data writing to the memory cell MC.

Next, in the read / write operation, after the precharge cycle at time _t 8 to _t 9, the word line WL and the dummy word line DWL rise at the time _t 10, and the memory cell MC and the dummy cell MD Data at nodes B1 and B2. This operates the npn transistor, so that data appears on the bit lines BL and / BL. At this time, the npn transistor Q2 on the dummy cell MD side is turned on deeper, so that the potential of the dummy bit line / BL is higher than the potential of the bit line BL. And at time _t 11 is the sense amplifier circuit (SA), at time _t 12 restore circuit (RSTR) is activated bit line data is amplified. Then, at time _t 13- _t 14, the plate potential goes from (1/2) V _CC to 0 V, clocked to (1/2) V _CC and rewritten.

Next, the operation of writing one data and reading / writing of write data will be described with reference to FIG. Here, the writing of one data also indicates the case of inverting writing of zero data. After the pre-charge cycle time of _t 15- _t 16, the wand time line (WL) and a dummy word line (DWL) is raised at _t 17 and the time _t 18 in the sense amplifier circuit (SA) is activated, and the time from _t 19 The recovery circuit RSTR is activated to amplify the bit line potential. Data 1 to be written at time _t 20 is transferred to the bit line BL, and V _CC is written to the node SN of the memory cell MC by clocking the plate PL at _t 21- _t 22.

In the read / write operation, the word line WL and the dummy word line DWL rise at time _t 10 after the precharge cycle of _t 23 to _t 24, and the data of the memory cell MC and the dummy cell MD are lost. Appear at nodes B1 and B2, and appear at bit lines BL and / BL under the action of the npn transistor. And at time _t 25 is the sense amplifier circuit (SA), at time _t 26 restore circuit (RSTR) is activated bit line data is amplified. Then at _t 28- _t 29 the plate potential goes from (1/2) V _CC to 0 V, clocked at (1/2) V _CC to perform data rewriting.

The layout similar to that of Figs. 6 to 9 can also be adopted for the DRAM cell array of the embodiment using the p-channel MOS transistor and the npn transistor.

13 is a configuration diagram of a main DRAM part of another embodiment. Unlike FIG. 1, in the present embodiment, resistors R1 and R2 having sufficiently high resistance values are inserted between the base and emitter of the pnp transistors Q1 and Q2, respectively.

In this way, when the resistors R1 and R2 are inserted, the clock plate is not clocked to the capacitor plate PL as in the previous embodiment, and thus data can be written without yielding between the base and emitter of the pnp transistor.

However, a technique for reducing bit line connection by forming a memory cell unit by connecting a plurality of memory cells in series in a DRAM is known. This method has the advantage of reducing the cell area, but has the disadvantage of inferior reliability of the data read operation. The data of the memory cell unit reads data sequentially from the memory cell closest to the bit line, and stores the read data once in the register, and when reading data of the memory cell far from the bit line, the data is placed between this and the bit line. The capacity of another memory cell is added to the bit line capacity. Therefore, the bit line capacity is effectively increased, that is, the memory cell charge is effectively reduced, which causes a read error.

Since the DRAM according to the present invention can read out the memory cell data using the current amplifying action of the bipolar transistor, a great effect can be obtained when the DRAM is applied to the DRAM of the above-described memory cell unit.

FIG. 14 is a configuration diagram of an essential part to which the present invention is applied to such a memory cell unit DRAM. Here, one dummy cell unit consisting of four memory cells MC0-MC3 connected to the bit line BL, and one consisting of four dummy cells MD0-MD3 connected to the dummy bit line / BL. Two dummy cell units are shown. The drains of the single-axis MOS transistors of the memory cell unit are connected to the bases of the pnp transistors Q1 and Q2 in the same manner as in the above embodiment. The other end of the memory cell unit is connected to the bit line BL through the storage node data writing MOS transistor MW1, and the other end of the dummy cell unit is via the same writing MOS transistor MW2 (1/2). V _CC is intended to be supplied.

FIG. 15 is a specific configuration diagram of the sense amplifier / restoration circuit section in FIG. In this embodiment, the current mirror type CMOS differential amplifier circuit DA is used as the sense amplifier / restoration circuit, and the two input nodes are connected to the bit line BL and the dummy bit through the transfer gate MOS transistors M21 and M22. It is connected to the line / BL. The upper bit lines GBL and / GBL following the output of the differential amplifying circuit DA are provided with a register REG for storing data once read out from the memory cell unit. The bit lines BL and / BL are provided with an equalizing circuit EQ which is set at these precharge potentials V _PRE , and an equalizing MOS transistor B35 is also provided in the upper bit lines GBL and / GBL.

The flip-flop type sense amplifier / restoration circuit may be used for the differential amplifier circuit DA in the same manner as in the previous embodiment. Therefore, the reason for using the differential amplification circuit DA is that if the register REG holds the read data once and is configured as a latch type having an amplitude from 0 V to the power supply potential V _CC , the sense amplifier / restoration circuit section has a latch type. Because it does not need. The resistor PEG may be a dynamic type as long as it has an amplitude from 0V to V _CC .

16 is a timing chart for explaining a read operation of a DRAM according to the present embodiment.

As an initial state, (1/2) V _CC is written in all the similar cell units MD0-MD3 in the similar cell unit. The upper bit lines GBL and / GBL are equalized by the equalizing MOS transistor M35, and the bit lines BL and / BL are equalized to the precharge potential V _PRE by the equalizing circuit EQ. The precharge potential V _PRE may be larger than the value obtained by adding the base-emitter forward voltage V _BE of the pnp transistor to the dummy cell write potential (1/2) V _CC , for example, V _CC . At this time, as in the previous embodiment, the base nodes B1 and B2 of the pnp transistors Q1 and Q2 are precharged to V _PRE -V _BE .

In order to enter the read cycle, the equalization MOS transistor M35 of the upper bit lines GBL and / GBL is first turned off, the equalization circuit EQ of the bit lines BL and / BL is also turned off, and the first data is read out. The word line WL0 and the dummy word line DWL0 rise. If the data of the memory cell MC0 is 0, the potential of the base node B1 on the bit line BL side is lower than that of the base node B2 on the dummy bit line / BL side, and thus the pnp transistor Q1 is turned on. do.

At this time, since the amount of charges emitted from the emitter of the pnp transistor Q1 to the collector is h _FE times the charge command drawn to the base, the bit line BL discharges at a high speed. The data read in the bit lines BL and / BL in this manner is amplified by the current mirror type differential amplifier circuit DA by turning on M26, M27, M28, and M29 and stored in the register RFG. When writing to the register REG ends, the upper bit lines GBL and / GBL and the bit lines BL and / BL are equalized again.

Subsequently, the process moves to data reading of the memory cell MC1. The method is the same as that of the memory cell MC0. FIG. 16 shows the case where the data of the memory cell MC1 is 1, where the potential drop of the bit line BL is smaller than that of the dummy bit line / BL. In turn, the memory cells MC2 and MC3 are read out, and data is stored in the register REG.

17 is a timing chart for explaining the write operation of the DRAM according to the present embodiment.

As an initial state, the differential amplifier circuit DA is kept in an inactive state. The word lines WL0-WL3 and the dummy word lines DWL0-DWL3 are both maintained at the H level. The upper bit lines GBL and / GBL and the bit lines BL and / BL are equalized. Then, in the write cycle, the word line WL0 and the dummy word line DWL0 are first lowered, and the write line WL _W and the dummy word line DWL _W are raised so that they can be written. After that, the equalizing MOS transistor M35 and the equalizing circuit EQ are turned off, and data to be written to the memory cell MC0 is read from the register REG. This data is transferred to the bit line BL through the transfer gate MOS transistor M21 and is transferred to the memory cell MC0 through the write MOS transistor MW1 and the cell transistors of the memory cells MC3, MC2 and MC1. Is written. The word line WL1 and the dummy word line DML1 descend to complete writing. At the same time, (1/2) V _CC is also written to the dummy cell MD0.

In the following, data is written to the memory cells MC1, MC2, and MC3. When data is written to the last memory cell MC3, M22 is turned on so that the reverse data of the bit line BL is written to the dummy bit line / BL. In this way, the (1/2) V _CC precharge potential for the next reading can be created by turning on the equalization circuit. The same applies to the case of data writing outside such a writing operation or to rewriting read data.

As described above, according to the present embodiment, in a system in which a plurality of memory cells are connected in series to form a memory cell unit, since the current amplification action of the bipolar transistor enters when the memory cell data is read out, The bit line capacity is effectively reduced, so that a highly reliable DRAM with no read error can be obtained.

Next, some embodiments in which the structure shown in FIG. 2 is modified with respect to the DRAM cell structure of the present invention will be described.

In the embodiment of FIG. 18, the p-type polycrystalline silicon layer 12 is buried in the bit line connection portion formed in the insulating film 11. By filling in the connection holes of the p-type polycrystalline silicon layer 12, the bit line 10 can be prevented from coming into contact with the metal.

In the embodiment of Fig. 19, not only the connecting portion but also the entire bit line 13 is constituted by the p-type polycrystalline silicon layer. In addition, a high concentration n-type 14 is provided around the p-type emitter layer 9. Therefore, the breakdown voltage BV _BE between the base and the emitter of the pnp transistor can be lowered, thereby making writing easier.

20 shows a high concentration n-type layer 14 around the p-type emitter layer 9 similarly to that of FIG. 19 in the structure of FIG. 2 in which the bit line 10 is made of only metal.

In the embodiment of Fig. 21, in the embodiment in which the bit line 13 is formed by the p-type polycrystalline silicon layer, the high concentration n-type layer 15 is provided in the sidewall portion of the bit line connection hole. The high concentration n-type layer 15 functions as a solid resistance that substantially shorts the base and emitter of the pnp transistor. Therefore, it is effective as a means for realizing the structure of FIG.

In the embodiment of FIG. 22, the insulating film 16 is provided between the high concentration n-type layer 15 and the p-type layer of the connection portion of the bit line 13 in the structure of FIG.

In the embodiment of FIG. 23, the high concentration n-type layer 15 in the embodiment of FIG. 21 is disposed not only in the connection portion but also on the entire surface under the layer of the bit line 13.

The embodiment of FIG. 24 inserts an insulating film 16 such as a silicon oxide film between the bit line 13 and the highly concentrated n-type layer 15 by the p-type polycrystalline silicon in the embodiment of FIG.

In the embodiment of Fig. 25, the contact portion of the n-type drain 5 is convex to form the p-type emitter layer 9 on the surface of the convex portion.

FIG. 26 to FIG. 28 illustrate an embodiment in which the present invention is applied to a DRAM having a memory cell structure using a rounded gate transistor (SGT). By forming grooves in the silicon substrate 1, columnar silicon layers 20 are arranged in each memory cell region. An n-type source layer 6 serving as an accumulation node is formed around the bottom of each columnar silicon layer 20, and a plate 8 is buried in the bottom of the groove via a capacitor insulating film 7. A gate electrode 4 is formed through the gate insulating film 3 so as to surround a portion on the plate 8 of the columnar silicon layer, and an n-type drain layer 6 is formed on the columnar silicon layer 20. . The p-type emitter layer 9 of the pnp transistor is formed on the surface of the n-type drain layer 6, and the bit line 10 is connected thereto. FIG. 26 shows the case of the metal bit line 10 by A1 or the like, and FIG. 27 shows the case of the bit line 13 by p-type polycrystalline silicon. In FIG. 27, the bit line is arranged as a flat structure in which the surface of the p-type emitter layer 9 and the surface of the buried insulating film are aligned. In FIG. 28, the p-type emitter layer 9 protrudes from the surrounding buried insulating film. As a state, the bit line 10 is also connected to the side surface.

Next, an embodiment of the multi-division bit line method will be described.

29 shows a DRAM core circuit of the same embodiment. This embodiment is an example in which mxn memory cells are laid out in a known root bit line manner. In the figure, reference numeral 31 denotes a memory cell shown in FIG. 30, and reference numeral 32 denotes a bit line control circuit composed of an equivalent circuit and a restoration circuit of the bit line. The m main word lines 34 are connected to k sub word lines 35 through switching transistors 33, respectively. The transfer gate of the memory cell 31 is connected to the sub word line 35. In the switching transistor 33 is connected to the signal Φ _K decoded by the column address. This signal Φ _K is also used for the selection of the bit line control circuit 32.

As the operation of the core circuit, first, the main word line 34 is selected in the row address. Subsequently, the sub word line 35 and the bit line control circuit 32 are selected in the column address. That is, the transfer gate is opened to the n memory cells connected to the main word line 34 selected at the row address through the sub word line 35 so that the data of the memory cells are read out of 1 / k, that is, n / k. .

Next, the memory cell structure of FIG. 30 will be described. A gate 42 serving as a word line is formed by inserting an insulating film 41 into an n well 40 formed in an n-type substrate or a p-type substrate. Subsequently, a p-type diffusion layer 43 serving as a source and a drain is formed, and the capacitor memory electrode 44 is formed. In addition, the plate 46 is formed through the capacitor insulating film 45. In addition, the drain portion of the MOS transistor to be bit-connected forms a p-type polysilicon 47 serving as a resistance element by using a known sidewall residual technique. Then, n-type polysilicon 49 to be a bit line is formed through the insulating film 48. Since n ⁺ polysilicon 49 is in contact with the p-type diffusion layer 43 at the bit line connection portion, n ⁺ is diffused into p, and an npn bipolar transistor is formed at this portion.

Next, the write and read operations of the DRAM using the cell of this embodiment will be described with reference to FIG. Φ _P becomes low in the precharge cycle, and the bit line BL and the dummy word line / BL are set to Vp (= 0 V) through the MOS transistors M1 and M2. The dummy cell 51 is set to a potential V _DC lower than V _CC through the MOS transistor M3. At the time of writing, the input data D _in is cut into the I / O line through the MOS transistor M6 _in the input circuit 55 with Φ _W high. By making the column select signal CSL high, data is transferred to the bit line BL through the MOS transistor M4. This data is stored in the memory electrode 44 via the resistor 47.

At 0 (0V) read, the bit line potential does not change because the bipolar transistor 52 in the memory cell 31 does not operate. On the other hand, since the bipolar transistor 53 in the dummy cell 51 operates, the dummy bit line potential changes. Therefore, the bit line potential is lower than the dummy bit line potential. When reading 1 (Vcc), the bit line potential is higher than the dummy bit line potential. This is because the accumulated charge of the memory cell 31 is larger than that of the dummy cell 51. After the data of the cell is read out to the bit line, the restoration circuit 54 rewrites the data into the cell. By making the column select signal CSL high, data is transferred to the I / O line and the output circuit 56 through the MOS transistors M4 and M5 and output as the output data D _out .

In a DRAM using such a cell, the data of the cell appears on the bit line while being amplified by the bipolar transistors 52 and 53, so that the potential difference ΔV _BL between the bit line and the dummy bit line can be increased. Hereinafter, ΔV _BL is analytically determined.

First,? V _BL in the case of a conventional cell is obtained. The write potential of the dummy cell is set to V _CC / 2. In other words, V _DC = V _CC / 2. In addition, the precharge potential of the bit line is set to V _P. First, when V _CC is written into the cell storage capacitor C _S , the potential V _B1 of the bit line is V _B1 = (C _S V _CC + C _B V _P ) / (C _B + C _S ). Where C _B is the bit line capacitance. When 0 V is written, the potential V _B0 of the bit line is V _B0 = C _B V _P / (C _B + C _S ). The potential V _BD shown on the dummy bit line is V _BD = (C _S V _DC + C _B V _P ) / (C _B + C _S ). Therefore, the potential difference ΔVBL between the bit line and the dummy bit line becomes ΔV _BL = V _DC / (1 + C _B / C _S ) for both 1 and 0.

In the case of the cell of the present embodiment,? V _BL is obtained using FIG. First, assume that the VF is always constant between the base and the emitter when the bipolar transistor 52 is operating. Further, suppose that after the bipolar transistor operation, the potential of the bit line is V _B ', after which a current flows through the resistor 47, and finally V _B. First, the bit line BL is 0V, and the base of the bipolar transistor 52 is also 0V.

When V _CC is written in the cell's storage capacity C _S , the base potential becomes V _B '+ V _F after the operation of the bipolar transistor, so that the charge flowing into the base and the resistor 47 becomes C _S V _CC- (C _S + C _B ') (V _B ' + V _F ) Where C _B ′ is the parasitic capacity of the base. The charge transferred by the bipolar transistor 52 is (1 + β) times to charge the bit line capacitance C _B flowing into the bit line BL, so that [C _S V _CC- (C _S + C _B ') (V _B '+ V _F )] (1 + β) = C _B V _B '. However, β is a product of the current amplification factor of the bipolar transistor 52 multiplied by the ratio of the electric charges flowing through the bipolar transistor 52 among the charges classified into the bipolar transistor 52 and the resistor 47. Therefore, V _B '= (1 + β) [C _S V _CC- (C _S + C _B ') V _F ] / [(1 + β) (C _S + C _B ') + C _B ]. Next, find V _B. The base potential of the bipolar transistor 52 changes from V _B '+ V _F to V _B , and the bit line potential changes from V _B ' to V _B , while charge is preserved (C _S + C _B ') (V _B '+ V _F ) + C _B V _B ' = (C _S + C _B ') V _B = C _B V _B to V _B = V _B ' + [(C _S + C _B ') / (C _S + C _B '+ C _B )] V _F. When 0 V is written in the storage capacitor C _S of the cell, the bipolar transistor 52 does not operate, and since the charge exchange is accompanied with the bit line BL, the bit line potential does not change. That is, V _B = 0.

Dummy bit line potential has to think as the bit line potential in the case that in the write and the potential V _DC of the dummy cell is V _DC is written into the _{cell, V BD '= C S V} DC (+ β!) - (C S + C _B ') V _F ] / [(1 + β) (C _S + C _B ') + C _B ], V _BD = V _BD '+ [(C _S + C _B ') (C _S + C _B '+ C _B )] V _F. If C _B 'C _B , V _F V _CC , V _BD = (1/2) V _BL when V _DC = (1/2) V _CC .

In the above, the potential difference ΔV _BL between the bit line and the dummy bit line is either 1 or 0, ΔV _BL = {[1 + β-β (1 + C _B '/ C _S ) · V _F / V _CC ] / [(1+ β) (1 + C _B '/ C _S ) + C _B / C _S ]} V _DC .

33 shows the calculation result of the potential difference ΔV _BL between the bit line and the dummy bit line when the conventional cell and the cell of this embodiment are used. However, V _CC = 4 V, V _F = 0.7 V, C _B '= 8.5 fF. In a conventional cell design, a small ΔV _BL of approximately 200 mV obtained when C _B / C _S is 10 was amplified by a sense amplifier. However, by using the cell of the present embodiment, even if C _B / C _S is 200 times that of the conventional 20, sufficient ΔB _BL close to 300 mV can be obtained. Therefore, the bit line capacitance C _B can be increased.

Next, in the 64M DRAM using the conventional cell, the chip size in the case where the cell storage capacity C _S is designed to be 20 fF and the bit line capacity C _B is designed to be 200 fF is obtained. In order to set C _B to 200 fF, the number of cells connected to one bit line is 128. Therefore, the bit line number of the one-chip is ^226/128 = 524288 atoms. Using the shared sense amplifier, loop bit line method, the number of bit lines connected to one sense amplifier is four. Thus, the number of one-chip sense amplifiers is 524288/4 = 131072. In cell area 1.6㎛ ^2, a pattern area of a peripheral circuit for controlling a sense amplifier and the input-output gate, and this is 646㎛ ^2, a pattern area of the other peripheral circuit is 23mm2. Therefore, the chip area S is S = 1.6 µm ² × 2 ²⁶ + 646 µm ³ × 131072 + 23 mm 2 = 215 mm 2.

Next, the chip size when the cell of this embodiment is used for 64M DRAM is obtained. When the bit line is not divided, the number of sense amplifiers is 2 ¹³ = 8192 by using the public sense amplifier and the root bit line method. Therefore, the chip area S 'is S' = 1.6 mu m ² × 2 ²⁶ + 646 mu m ² × 8192 + 23 = 135.7 mm ² . As a result, the chip area is reduced by 63% compared with the conventional method.

As described above, according to this embodiment, even if the bit line capacity is increased due to high density, sufficient bit line amplitude can be obtained and stable DRAM can be supplied. As a result, the number of sense amplifiers and input / output gates of the bit lines can be reduced, and these pattern areas can be reduced. In addition, according to the present exemplary embodiment, an increase in power consumption of the chip is suppressed by dividing a cell connected to one word line into a plurality of blocks and selectively activating the same.

FIG. 34 shows a modification of the cell configuration of FIG. 30. In this example, n ⁺ buried layer 50 is provided in n well 40, and other parts are the same as FIG.

Electrons injected from the base in the emitter of the bipolar transistor flow through the collector [n well 40], but when the collector resistance is large, electrons are injected into the memory electrode 44 due to the voltage drop, thereby destroying data in the cell. Data destruction can be prevented by lowering the collector resistance by the n ⁺ buried layer 50. It is also advantageous to prevent data destruction when the collector potential is higher than one write level of the cell.

35 is another embodiment of lowering the collector resistance. The potential to the n well 40, which is a collector, is supplied not only from the periphery of the cell array, but also through the wiring 62 between the cell array blocks 61 of the negative word line. Alternatively, the cell array block 61 may be supplied via the wiring 62, or the n ⁺ buried layer 50 of FIG. 34 may be combined.

36 shows an example in which the n well 63 is divided to prevent the destruction of cell data in the adjacent wells of electrons in the emitter. Also in this case, the examples of FIGS. 34 and 35 may be combined.

In the SEA cell structure in which the bipolar transistor is inserted between the drain and the bit line of the cell transistor described above, the accumulated charge is amplified by the npn bipolar transistor present in the bit line bottom 11 and the substrate and supplied to the bit line. Enables fast writing and reading of data. Therefore, even a small C _{S with a} simple capacitor structure can be surely operated.

However, there are three factors that determine C _{S due} to high integration of DRAM: (i) read voltage and S / N ratio of the bit line sense amplifier, (ii) soft error, and (iii) refresh. The countermeasure against (i) was implemented. Therefore, for (ii) and (iii), a reduction effect of C _S is not obtained, and a relatively large capacitor memory node must be formed because some Cs is required as the integration proceeds in the future. Therefore, a large step may occur and processing of the bit line, which is the upper layer wiring, or the A1 wiring thereon, may be difficult.

It turns below the exemplary embodiment measures about the remaining two factors that determine the C _S (soft errors and refresh) to C reduced by reducing the _S to the limit to remove a capacitor to effectively or completely.

Therefore, using an SOI substrate serving as a barrier layer for carriers generated by α-rays incident on the substrate, a damage layer caused by high energy ion implantation, an n ⁺ buried layer or a p ⁺ buried layer, and the like, which contribute to refreshing Transistor isolation or the like for suppressing leakage current at the stage is used.

FIG. 37 is a plan view showing a DRAM configuration of an embodiment in which countermeasures against shift error and refreshing are performed. FIG. 38 is a cross section of arrow A-A ', a cross section of arrow BB', and a cross section of arrow C-C 'in FIG. Illustrated.

The damage layer or SOI oxide layer 72 formed on the p-type silicon substrate 71 by the high energy ion implantation is formed, and the n ⁺ buried layer 73 is formed thereon and the n well 74 thereon by high energy ion implantation or the like. To form. Using this substrate, a diffusion layer 75 'is formed on its surface by lithography and ion implantation techniques, and transistor isolation is formed by the polycrystalline silicon 77 and the insulating film 76. The capacitance between the diffusion layer 75 'and the separation electrode made of polycrystalline silicon or the like is the storage capacitance. The insulating film 76 may be any of an oxide film, an NO film, an ONO film, or a high dielectric film, depending on the required C _S. Thereafter, a word line MOS transistor is formed and a diffusion layer 75 is formed by ion implantation.

Subsequently, the p-type polycrystalline silicon layer 82 is formed in the bit line connection groove 81 so as to be electrically connected to the diffusion layer 75, and an insulating film 83 such as an oxide film is formed by the sidewall remaining. Thereafter, n ⁺ polycrystalline silicon 85 is deposited to form a diffusion layer 84 that becomes a bipolar emitter by impurity thermal diffusion. Next, the bit line is formed by depositing and patterning the silicide 86 or the like used as the bit wire. The collector of bipolar is the n ⁺ buried layer 73, the n well 74, the base is the diffusion layer P in common with the drain of the transfer gate transceiver 79, the emitters are the bit lines 85 and 86 and the diffusion layer 84. It consists of. The p-type layer 82 connected to the base 75 forms a pn junction with the bit line 85, and forms a resistor R through which charge passes.

By such a configuration, the accumulated charge is amplified by the npn bipolar and the sense amplifier sensitivity is increased. In addition, the carrier barrier layer 72 blocks the carriers generated in α-rays and the like, thereby increasing the resistance of soft errors. In addition, the use of transistor isolation suppresses the leakage current at the device isolation stage and significantly improves the refresh characteristics. As described above, the storage capacitance C _S can be made to the limit, and there is no need to prepare a capacitor structure in particular. That is, a very simple structure can further improve the process length or processability of the SEA cell.

The carrier barrier layer 72 of the above embodiment may be common to the n ⁺ buried layer 73 or may be common to the p ⁺ buried layer. In addition, although an npn bipolar transistor is used, a pnp transistor is also good. The conductivity type may also be reversed. In the above embodiment, other layouts such as a folded bit line layout or an open bit line layout may be used.

As described above, according to the present embodiment, C _S required in the read voltage and the S / N ratio of the sense amplifier, soft error, and refresh can be made almost zero, and thus C _S can be reduced to the limit, thereby effectively reducing the capacitor. Alternatively, it can be eliminated entirely to simplify or completely eliminate the capacitor process, which is a problem with SEA cells.

FIG. 39 is a plan view showing a DRAM configuration of another embodiment in which countermeasures against soft errors and refreshes are shown. FIG. 40 is a cross section of arrow A-A 'and a cross section of arrow B-B' of FIG. And the cross section of arrow C-C '.

This embodiment is a case where the MOS transistor and the capacitor are applied to a NAND type DRAM cell in which the MOS transistor and the capacitor are alternately arranged in series, unlike the case where the conventional DRAM of the embodiment of FIGS. 37 and 38 is used. The damage layer by injection or the oxide layer of SOI is used, and transistor isolation is used for device isolation. Also in this embodiment, C _S can be reduced to an extreme, and the accumulation capacity C _S is constituted only by the overlap capacitance between the diffusion layer 75 and the transistor isolation 77 and the junction capacitance between the diffusion layer 75 and the n well 74. .

14 shows a case where the space between the word lines 79 is narrowed by using a phase shift or the like. In this case, the coupling capacitance between word lines constitutes C _S.

In this case, the adhesion becomes very high. The carrier layer 72 of the carrier may be common with the n ⁺ buried layer or the p ⁺ buried layer 73 together with the embodiments of FIGS. 39 and 40 and 41. Moreover, you may reverse each conductivity type, such as a bipolar and a diffusion layer.

FIG. 42 shows a plan view showing a DRAM configuration of another embodiment, and FIG. 43 shows a cross section of arrow A-A ', a cross section of arrow B-B', and a cross section of arrow C-C 'of FIG.

This embodiment uses the overlapping capacitance of the diffusion layer 75 and the pass word line as the accumulation capacitor C _S , and uses a damage layer or SOI oxide film by high energy ion implantation as a barrier layer of the carrier, and trench isolation without damage as element isolation. This is the case. In particular, there is no need to use a capacitor structure such as a storage node. In order to further accumulate C _S , only the insulating film 78 ′ below the pass word line WL may be changed to an NO film or a high dielectric film.

FIG. 44 (a) is a plan view showing a DRAM configuration of still another embodiment, and FIG. 44 (b) is a cross-sectional view of arrow A-A 'in (a). 45 (a)-(c) are sectional views of some embodiments corresponding to the cross section of arrow A-A 'in FIG. 44 (a).

The embodiment of FIG. 44 (b) shows a case where only the junction capacitance between the diffusion layer 75 and the n well 74 is used as an accumulation capacitor. The embodiment of FIG. 45 (a) shows a barrier layer of a carrier using the coupling capacitance between the gate 7 formed by the polycrystalline silicon 88 formed on the sidewall of the word line and the insulating film 87 and the junction 75 as an accumulation capacitor. The case where n ⁺ buried layer 73 'is used as a figure is shown. The embodiment of the forty-seventh embodiment (b) uses a redundant capacitance between the transistor having the gate electrode 79 embedded in the trench 89 and the diffusion layer 75 as an accumulation capacitor and a p ⁺ type buried layer 72 'as a carrier barrier layer. ) Is used. In the embodiment of FIG. 45 (c), an improved source / drain structure transistor is used in which the silicon epitaxial layer 90 is grown and p-type diffused after the gate electrode 79 is formed as a source drain. ) And a redundancy capacitance between the diffusion layer 90 and the diffusion layer 90 as an accumulation capacitor and an oxide film layer 72 of the SOI is used as the barrier layer of the carrier. There is no need to construct a special capacitor structure in both the 44 and 45 embodiments.

46 is a cross sectional view showing a DRAM configuration of another embodiment. In this embodiment, a MOS transistor having a three-dimensional structure is used as the transistor. A trench 91 is formed in a p-type substrate on which a damaged layer by high energy ion implantation or a layer 72 formed by an SOI oxide film and a p ⁺ buried layer 73 are formed, and an n-type diffusion layer 75 'is formed on the sidewall thereof. After forming, the gate electrode 79 is formed to form the three-dimensional transistor 79. Further, a pn junction of an n layer 81 and a p ⁺ layer 85 made of a pnp bipolar transistor and a resistor R at the time of writing is formed on the silicon pillar. The storage capacitor is composed of a redundant capacitance between the n-type diffusion layer 75 'and the gate electrode 79.

FIG. 47 is a plan view showing a DRAM configuration of still another embodiment, and FIG. 48 is a cross sectional view taken along arrow A-A 'of FIG. 47. This embodiment shows software and refresh in the device configuration as shown in FIG. The countermeasures were taken. Basically, it is the same as the structure of FIG. 30, and in addition, in this embodiment, the damage layer or the layer 72 by SOI oxide film is provided in the board | substrate 71. FIG. Reference numeral 93 is a memory node electrode, 94 is a capacitor insulating film, and 95 is a plate electrode. Such a configuration can make the capacitor capacitor C _S small, so that the height of the storage node electrode 93 can be made low, and thus the surface level can be made small. Therefore, the bit line or the A1 wire thereon, which is the upper layer wiring, can be easily processed. In this embodiment, the bit line is formed after the accumulation capacitor processing. However, the accumulation capacitor may be formed after the bit line processing.

37 to 47, the barrier layer 72 of the carrier is a damage layer resulting from high energy ion implantation, an oxide layer of SOI, an n ⁺ buried layer, a p ⁺ buried layer, or other carrier barrier layer. Any layer may be used. As the storage capacitor, any of the capacitances such as the coupling capacitance with the transistor isolation, the coupling junction capacitance with the pass word lines, the redundant capacitance of the gate, and the coupling zero capacitance of the three-dimensional structure transistor may be used.

The conductive type of the bipolar transistor may be reversed, and the resistor R may or may not be present at the time of data writing. The cell layout may be a fold bit line, an open bit line, a NAND layout, an Ichimatsu layout, or the like. The material of each layer may also be changed within a range that does not impair operation as an SEA cell DRAM. Moreover, of course, the theory of the embodiment of Figures 37-48 can be applied to the embodiment of Figures 1-36.

As described above, according to the present invention, by inserting a bipolar transistor between a memory cell and a bit line and utilizing the current amplifying action thereof, it is possible to provide a DRAM capable of reading data with high reliability even with a small memory cell.

In addition, by providing a barrier layer for the carrier in the substrate or employing transistor isolation, C _S required for soft error or refresh can be made almost zero, effectively or completely eliminating the capacitor, thereby simplifying or completely eliminating the capacitor formation process. Can be.

Claims (10)

A first conductive substrate bonded to a semiconductor substrate, a memory cell comprising a MOS transistor and a capacitor arranged on the substrate, a first conductive substrate region of the MOS transistor as a collector, a drain as a second conductive base, and bonded to the base. A bipolar transistor having a type emitter, a bit line for exchanging data with the memory cell connected to the emitter of the bipolar transistor, and a word line for driving the memory cell connected to the gate of the MOS transistor; And a resistor is provided between the base and the bit line. A semiconductor substrate having a first conductivity type region, a second conductivity type source and drain formed at a distance from each other in the first conductivity type region of the substrate, and having a gate insulating film on the first conductivity type region between the source drains; A MOS transistor having a gate electrode formed as a word line, a capacitor formed on the substrate using a second conductive source of the MOS transistor as one electrode, and a first conductive type region in which the MOS transistor is formed, And a bit line connected to the emitter of the bipolar transistor and a bipolar transistor having a first conductivity type emitter bonded to the base as a second conductive drain base, wherein a resistor is provided between the base and the bit line. A dynamic semiconductor memory device, characterized in that. The dynamic semiconductor memory device according to claim 1, further comprising plate potential control means for clocking the plate of the capacitor with a potential difference of greater than or equal to the breakdown voltage between the base and the emitter of the bipolar transistor during data writing. 2. The memory cell unit according to claim 1, wherein a plurality of the memory cells are connected in series to form a memory cell unit, a drain of one end MOS transistor of the memory cell unit is connected to a base of the bipolar transistor, and the other end storage node is And a register which is connected to the bit line via a write MOS transistor and temporarily stores a plurality of data in the memory cell unit which are sequentially read out from the bit line sense amplifier section. A semiconductor substrate, a memory cell comprising a first MOS transistor and a capacitor arranged on the substrate, a first conductive substrate region of the first MOS transistor as a collector, a drain as a second conductive base, and a junction with the base. A bipolar transistor having a first conductivity type emitter, a bit line for exchanging data with the memory cell connected to the emitter of the bipolar transistor, and for driving the memory cell connected to the gate of the first MOS transistor And a second MOS transistor having a first word line, a first word line connected to a drain, a second word line connected to a source, and a signal for selecting the bit line connected to a gate. Dynamic semiconductor memory device. A semiconductor substrate having a barrier layer of a carrier, a memory cell comprising MOS transistors and capacitors arranged on the substrate, a first conductive substrate region of the MOS transistor as a collector, a drain as a second conductive base, and the base Driving a bipolar transistor having a first conductivity type emitter coupled to a bit line, a bit line for exchanging data with the memory cell connected to the emitter of the bipolar transistor, and the memory cell connected to a gate of the MOS transistor. And a word line, wherein a resistor is provided between the base and the bit line. 7. A dynamic semiconductor memory device according to claim 6, wherein an SOI substrate, a damage layer by high energy ion implantation, and an n ⁺ or p ⁺ buried layer are used as a barrier layer of the carrier. 7. The dynamic semiconductor memory device according to claim 6, wherein a capacitance between a pass word line and a diffusion layer, a capacitance between a transistor isolation and a diffusion layer, a fringe capacitance of a gate, or a junction capacitance is used as a capacitor of the memory cell. 3. The dynamic semiconductor memory device according to claim 2, further comprising plate potential control means for clocking the plate of the capacitor with a potential difference of at least a breakdown voltage between the base and the emitter of the bipolar transistor at the time of data writing. 3. The memory cell unit of claim 2, wherein the plurality of memory cells are connected in series to form a memory cell unit, and the drain of one end MOS transistor of the memory cell unit is connected to the base of the bipolar transistor, and the other end storage node. And a register for temporarily storing a plurality of data in a unit connected to the bit line through a write MOS transistor and sequentially read out from the bit line sense amplifier section.