KR0131545B1 - Fabrication method of super current gain hetero-junction bipolar transistor - Google Patents
Fabrication method of super current gain hetero-junction bipolar transistorInfo
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- KR0131545B1 KR0131545B1 KR1019940019490A KR19940019490A KR0131545B1 KR 0131545 B1 KR0131545 B1 KR 0131545B1 KR 1019940019490 A KR1019940019490 A KR 1019940019490A KR 19940019490 A KR19940019490 A KR 19940019490A KR 0131545 B1 KR0131545 B1 KR 0131545B1
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000000034 method Methods 0.000 title claims description 23
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 13
- 239000002184 metal Substances 0.000 claims abstract description 13
- 230000006798 recombination Effects 0.000 claims abstract description 10
- 238000005215 recombination Methods 0.000 claims abstract description 10
- 238000002347 injection Methods 0.000 claims abstract description 9
- 239000007924 injection Substances 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 239000010410 layer Substances 0.000 claims description 40
- 239000004065 semiconductor Substances 0.000 claims description 8
- 239000011241 protective layer Substances 0.000 claims description 7
- 150000001875 compounds Chemical class 0.000 claims description 6
- 229910021480 group 4 element Inorganic materials 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 4
- 238000002955 isolation Methods 0.000 claims description 4
- 238000004151 rapid thermal annealing Methods 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 2
- 229910008484 TiSi Inorganic materials 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 238000000151 deposition Methods 0.000 abstract 1
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000001451 molecular beam epitaxy Methods 0.000 description 1
- 230000027756 respiratory electron transport chain Effects 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
- H01L29/66318—Heterojunction transistors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02387—Group 13/15 materials
- H01L21/02395—Arsenides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0804—Emitter regions of bipolar transistors
- H01L29/0817—Emitter regions of bipolar transistors of heterojunction bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/452—Ohmic electrodes on AIII-BV compounds
Abstract
Description
제1도는 본 발명의 이종접합 바이폴라 트랜지스터를 구성하는 각 에피층들이 이종접합된 구조를 도시한 단면도.1 is a cross-sectional view showing a structure in which each epi layer constituting the heterojunction bipolar transistor of the present invention is heterojunction;
제2도는 제1도의 에피구조를 이용하여 제작된 이종접합 바이폴라 트랜지스터의 구조를 도시한 단면도이다.2 is a cross-sectional view showing the structure of a heterojunction bipolar transistor fabricated using the epitaxial structure of FIG.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반절연성 GaAs 기판 2 : 부콜렉터층1 Semi-Insulating GaAs Substrate 2 Sub Collector Layer
3 : 콜렉터층 4 : 베이스층3: collector layer 4: base layer
5 : 에미터층 6,7 : 에미터 보호층5: emitter layer 6,7 emitter protective layer
8 : 에미터전극 9 : 베이스전극8 emitter electrode 9 base electrode
10 : 콜렉터 전극 11 : 전극 절연막10 collector electrode 11 electrode insulating film
12 : 패드 금속12: pad metal
본 발명은 화합물 반도체를 이용한 이종접합 바이폴라 트랜지스터(HBT : Heterojunction Bipolar Transistor)의 제조방법에 관한 것으로서, 특히 큰 에너지 갭을 갖는 화합물 반도체를 에미터로 이용하고 작은 에너지 갭을 갖는 4족 원소를 베이스로 이용하여 고 전류이득(super current gain)을 갖는 이종접합 바이폴라 트랜지스터의 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a heterojunction bipolar transistor (HBT) using a compound semiconductor, and in particular, uses a compound semiconductor having a large energy gap as an emitter and based on a Group 4 element having a small energy gap. The present invention relates to a method of manufacturing a heterojunction bipolar transistor having a high current gain.
최근, 광 수신기, 전계효과 트랜지스터의 입력버퍼 및 고 집적회로의 출력단 등에 고 전류이득을 가진 HBT들이 요구되고 있다. HBT 소자는 실리콘 바이폴라 접합 트랜지스터(BJT : Bipolar Junction Transistor)에 비해 화합물 반도체 고유의 특성에 기인한 보다 짧은 전자전송시간을 가지기 때문에 전류이득이 증대되며, 차단주파수가 높고 동작전압의 조절이 용이하여, 고속의 디지털 회로, MMIC(Monolithic Microwave IC), 및 광전 집적회로(OEIC)등에 광범위하게 응용되고 있다.Recently, HBTs having a high current gain are required for an optical receiver, an input buffer of a field effect transistor, and an output terminal of a high integrated circuit. HBT devices have shorter electron transfer times due to the inherent characteristics of compound semiconductors compared to silicon bipolar junction transistors (BJTs), resulting in increased current gain, high cutoff frequency, and easy adjustment of operating voltage. It is widely applied to high-speed digital circuits, MMICs (Monolithic Microwave ICs), and photoelectric integrated circuits (OEICs).
이러한 HBT 소자에 있어서, 전류이득은 에미터 주입효율과 직접적인 관계가 있다. 에미터의 효율을 높이기 위한 방안으로 다음과 같은 방법들이 연구되고 있다. 에미터-베이스 접합에서 광폭의 에너지 갭을 갖는 에미터를 사용하는 방법, 베이스층의 두께를 감소시키는 방법, 및 에미터-베이스 접합에서 표면 누설전류와 계면 재결합 전류를 감소시키는 방법등이 있다.In such an HBT device, the current gain is directly related to the emitter injection efficiency. In order to improve the efficiency of the emitter, the following methods are studied. There is a method of using an emitter having a wide energy gap in the emitter-base junction, a method of reducing the thickness of the base layer, and a method of reducing surface leakage current and interfacial recombination current in the emitter-base junction.
그러나, 현재 가장 보편적으로 제작되고 있는 AlGaAs 에미터/GaAs 베이스 접합의 HBT 소자는 여러번의 메사 식각공정으로 인하여, 특히 GaAs 베이스층 표면의 일부까지 식각되는 메사 식각으로 인하여 소자의 표면 재결합 전류가 증가하게 되고, 그 결과 전류이득이 상당량 감소되는 문제가 있다. 이러한 GaAs 베이스층의 표면보호를 위해 AlGaAs 에미터층의 일부를 잔류시켜 표면 재결합 전류를 감소시키는 기술이 보고되고 있으나. 메사식각을 위한 습식 에칭시 수백 Å 정도의 미세층의 두께를 재현성 있게 조절한다는 것은 현재의 기술로는 불가능한 실정에 있다.However, HBT devices of AlGaAs emitter / GaAs base junctions, which are the most commonly fabricated at present, have an increased surface recombination current due to multiple mesa etching processes, especially mesa etching that is etched to a part of the GaAs base layer surface. As a result, there is a problem that the current gain is considerably reduced. In order to protect the surface of the GaAs base layer, a technique of reducing a surface recombination current by remaining part of the AlGaAs emitter layer has been reported. In wet etching for mesa etching, it is impossible to reproducibly adjust the thickness of the microlayers on the order of hundreds of micrometers.
본 발명은 상술한 문제점들을 해소하기 위해 안출된 것으로서, 그 목적은 큰 에너지 갭을 갖는 화합물 반도체로 구성된 에미터와 낮은 표면 재결합 전류와 작은 에너지 갭을 갖는 4족 원소로 이루어진 베이스와의 에너지 갭 차이를 이용하여 고 전류이득(super current gain)을 갖는 HBT의 제조방법을 제공하는 것이다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is an energy gap difference between an emitter composed of a compound semiconductor having a large energy gap and a base composed of a Group 4 element having a low surface recombination current and a small energy gap. By using to provide a method of manufacturing HBT having a high current gain (super current gain).
상기 목적을 달성하기 위하여 본 발명은 반절연성 GaAs 기판 위에 제1도전형의 고농도 GaAs 부콜렉터층, 제1도전형의 저농도 콜렉터층, 제2도전형의 베이스층 및 제1도전형의 에미터층들이 순차적으로 적층된 에피구조를 다수의 메사식각에 의해 에미터, 베이스, 콜렉터로 형성하고, 각각의 오믹접합에 의해 각 전극들을 형성하며, 소자 격리 및 전극절연을 통하여 금속배선하는 공정으로 이루어진 이종접합 바이폴라 트랜지스터의 제조방법에 있어서,In order to achieve the above object, the present invention provides a high concentration GaAs subcollector layer of a first conductive type, a low concentration collector layer of a first conductive type, a base layer of a second conductive type, and an emitter layer of a first conductive type on a semi-insulating GaAs substrate. A heterojunction consisting of a process of forming an epi-structure stacked sequentially into an emitter, a base, and a collector by a plurality of mesa etching, forming electrodes by respective ohmic junctions, and metal wiring through device isolation and electrode insulation. In the manufacturing method of a bipolar transistor,
상기 에미터는 에미터의 주입효율을 극대화 시킬 수 있도록 큰 에너지 갭을 갖는 GayIn-yP로 이루어지고, 상기 베이스는 높은 소수운반자 농도와 낮은 재결합 전류를 갖는 작은 에너지 갭의 Ge로 이루어져 GayIn1-yP에 미터와 Ge 베이스의 에너지 갭 차이를 이용하여 전류이득의 증가를 얻고, 화합물 반도체 에미터와 4족 원소 반도체 베이스간의 거의 완전한 격자정합으로 이종접합된 GayIn1-yP에 미터/Ge 베이스/GaAs 콜렉터로 이루어진 것을 특징으로 한다.The emitter to the emitter comprises an emitter Ga y In -y P having a large energy gap to maximize the efficiency of the injection, the base consists of Ge of a small energy gap having a high minority carrier concentration and a low recombination current Ga y The gain of the current gain is obtained by using the energy gap difference between the meter and the Ge base in In 1-y P, and the heterojunction of Ga y In 1-y P heterojunction by almost complete lattice matching between the compound semiconductor emitter and the Group 4 element semiconductor base. Emitter / Ge base / GaAs collector.
본 발명은 에미터 주입효율을 극대화 할 수 있는 큰에너지 갭의 GaInP를 n형 에미터로 하고, 높은 소수 운반자 농도, 낮은 표면 재결합 전류, 작은 접촉저항 및 작은 에너지 갭의 Ge을 p형 베이스로 하며, GaAs를 n형 콜렉터로 조합한 새로운 HBT를 제조하는 방법이다.In the present invention, GaInP having a large energy gap for maximizing emitter injection efficiency is an n-type emitter, and a p-base is used for Ge having a small minority carrier concentration, low surface recombination current, small contact resistance and small energy gap. , A new HBT that combines GaAs with an n-type collector.
본 발명에 따르면, 베이스-에미터 간의 큰 가전도대(valence band) 차이로 베이스에서 에미터로의 역 정공주입을 억제하며, 에미터 전자 주입효율을 낮추지 않으면서 베이스의 도핑농도를 매우 높일 수 있다. 그 결과, 고 전류이득을 얻을 수 있다.According to the present invention, due to the large difference in the valence band between the base and the emitter, the back hole injection from the base to the emitter can be suppressed, and the doping concentration of the base can be greatly increased without reducing the emitter electron injection efficiency. have. As a result, high current gain can be obtained.
이하, 본 발명의 바람직한 실시예를 첨부도면을 참조하여 보다 상세히 설명한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
제1도는 본 발명의 HBT를 구성하는 각 에피층들이 이종접합된 에피구조의 단면을 나타낸 것이고, 제2도는 제1도의 에피구조를 이용하여 제작된 이종접합 바이폴라 트랜지스터의 단면 구조를 도시한 도면이다.FIG. 1 is a cross-sectional view of an epi structure in which each epi layer constituting the HBT of the present invention is heterojunction. FIG. 2 is a cross-sectional view of a heterojunction bipolar transistor fabricated using the epi structure of FIG. .
제1도에 의거하여, 반절연성 GaAs 기판(1) 위에 이종접합의 다층 에피구조를 형성한다. 먼저, 상기 기판(1) 위에 유기금속 화학 증착법(MOCVD : Metal-Organic Chemical Vapor Deposition)이나 분자선 에피택시(MBE : Molecular Beam Epitaxy)등의 에피택셜 성장방법들을 이용하여 부콜렉터층(2), 콜렉터층(3), 베이스층(4), 에미터층(5), 및 에미터 보호층(6,7)을 순차적으로 에피 성장시킨다.Based on FIG. 1, a heterojunction multilayer epitaxial structure is formed on the semi-insulating GaAs substrate 1. First, the sub-collector layer 2 and the collector are formed on the substrate 1 using epitaxial growth methods such as metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE). The layer 3, the base layer 4, the emitter layer 5, and the emitter protective layers 6, 7 are sequentially grown epitaxially.
상기 부콜렉터층(2)은 5000Å의 두께와 5×1018/㎝3의 불순물 농도로 Si이 도핑(doping)된 n+ GaAs로 이루어지고, 상기 콜렉터층(3)은 약 4000Å 정도의 두께와 2×1016/㎝3의 Si 도핑농도로 n형의 GaAs로 이루어진다.The sub-collector layer 2 is made of n + GaAs doped with Si at a thickness of 5000 kPa and an impurity concentration of 5 x 10 18 / cm 3 , and the collector layer 3 has a thickness of about 4000 kPa and 2 It is made of n type GaAs with Si doping concentration of 10 16 / cm 3 .
상기 베이스층(4)의 재료로는 상기 n GaAs 콜렉터(3)와 거의 완전한 격자정합(lattice match)을 이루고, 표면 재결합 전류가 낮으며, 상온에서 약0.66eV의 작은 에너지 갭을 지니고 있는 p형의 Ge을 사용한다. Ge 베이스층(3)의 두께는 후술되는 에미터의 효율을 높일 수 있도록 1000Å 정도로 얇게 형성된다. 또한 에미터와의 계면에서의 재결합 전류를 감소시킴과 동시에 표면에서의 누설전류를 감소시킬 수 있도록 약 1×1019/㎤의 고농도로 붕소(B)가 도핑된 p+형 Ge층(4)을 베이스로 형성한다.The material of the base layer 4 is a p-type having a nearly complete lattice match with the n GaAs collector 3, a low surface recombination current, and a small energy gap of about 0.66 eV at room temperature. Use Ge. The thickness of the Ge base layer 3 is formed to be as thin as 1000 kPa so as to increase the efficiency of the emitter described later. In addition, the p + type Ge layer 4 doped with boron (B) at a high concentration of about 1 × 10 19 / cm 3 to reduce the recombination current at the interface with the emitter and at the same time reduce the leakage current at the surface. To form a base.
상기 에미터층(5)은 In 몰분율(1-y)로서 0.49를 사용한 GayIn1-yP로 구성된다. 이러한 몰분률에서의 GayIn1-yP(y=0.51)의 에너지 갭은 상온에서 약 1.87eV로서 매우 큰 값을 가지게 된다. 이러한 GaInP 에미터(5)는 에피성장의 관점에서, 상기 Ge 베이스(4)와 거의 완전한 격자정합을 이루기 때문에 전기적 특성이 향상된다.The emitter layer 5 is composed of Ga y In 1-y P using 0.49 as the In mole fraction (1-y). The energy gap of GayIn 1-y P (y = 0.51) at this mole fraction is about 1.87 eV at room temperature, which is very large. Since the GaInP emitter 5 is almost completely lattice matched with the Ge base 4 in terms of epitaxial growth, electrical characteristics are improved.
상기 GayIn1-yP 에미층(5)의 두께는 약 2000Å 정도이며, 5×1017/㎤의 불순물 농도로 실리콘(Si)이 도핑된 n형으로 형성된다.The GayIn1- y P emi layer 5 has a thickness of about 2000 GPa and is formed of n-type doped with silicon (Si) at an impurity concentration of 5 × 10 17 / cm 3.
상기 이중층으로 된 에미터 보호층(6,7)은 하부에 있는 에미터층(5)의 오믹접촉 향상을 위한 것으로서, 상기 에미터(5)와의 접촉 저항 감소 및 격자부정합에 대한 완충역할을 하는 조성비 Z=0∼0.5의 In2Ga1-2As에미터 보호층(6)과 그위에 Z=0.5인 In2Ga1-2As의 에미터 보호층(7)으로 구성된 이중층으로 형성된다.The double layer emitter protective layers 6 and 7 are for improving ohmic contact of the emitter layer 5 at the lower part, and a composition ratio for reducing contact resistance with the emitter 5 and buffering against lattice mismatch. Z = 0 to 0.5 are formed in the in 2 Ga 1-2 as emitter protection layer 6 and moreover is configured to protect the emitter layer 7 of Z = 0.5 is in 2 Ga 1-2 as bilayer.
다음은 이상의 에피구조 즉, n-GaInP 에미터(5)/p+-Ge 베이스(4)n-GaAs 콜렉터(3)를 통상적인 메사식각 공정과 오믹접합 공정을 이용하여 전극들을 형성하고, 소자격리 및 전극절연을 통하여 금속배선 공정을 수행하여 제2도에 도시된 바와 같이 고 전류이득 HBT를 제작한다.Next, the epitaxial structure, i.e., n-GaInP emitter (5) / p + -Ge base (4) n-GaAs collector (3), is formed using conventional mesa etching process and ohmic bonding process, and device isolation. And metallization process through electrode insulation to fabricate a high current gain HBT as shown in FIG.
이때, 반복적인 메사 식각후에 상기 에미터(5) 위에 형성되는 에미터 전극(8)으로서 사용되는 오믹접합 금속으로 Ti/Pt/Au의 다중 금속이 사용된다. 또한, 베이스 전극(9)으로 사용되는 오믹접합 금속은 TiSi2가 사용되며, 콜렉터(3)와 오믹접합 되는 콜렉터 전극(10)으로는 AuGe/Ni/Au의 다중금속이 사용된다.At this time, multiple metals of Ti / Pt / Au are used as the ohmic junction metal used as the emitter electrode 8 formed on the emitter 5 after repeated mesa etching. In addition, TiSi 2 is used as the ohmic bonded metal used as the base electrode 9, and multiple metals of AuGe / Ni / Au are used as the collector electrode 10 ohmic bonded to the collector 3.
각 전극들(8,9,10) 형성 후에는 400℃의 온도에서 약 10초 동안 금속 열처리(RTA, rapid thermal annealing)공정을 사용하여 합금화 시킴으로써 단 한번의 열처리 공정으로 각각의 오믹 접촉저항을 최소화시킬 수 있다.After forming the electrodes 8, 9, and 10, they are alloyed using a rapid thermal annealing (RTA) process at a temperature of 400 ° C. for about 10 seconds to minimize the ohmic contact resistance in a single heat treatment process. You can.
소자격리 후에는 전극절연막(dielectric layer)(11)을 플라즈마 화학증착법(PECVD)을 사용하여 각 활성층들을 전기적으로 절연시킨다. 이때 사용되는 바람직한 절연막으로, 실리콘 질화막(SiN)이나 실리콘 산화막(SiOX)등이 사용될 수 있다.After device isolation, the dielectric layer 11 is electrically insulated from each active layer by using plasma chemical vapor deposition (PECVD). In this case, a silicon nitride film (SiN), a silicon oxide film (SiO X ), or the like may be used.
C2F6/CHF3플라즈마를 이용한 반응성 이온식각(RIE : Reactive Ion Etching)에 의해 패드 연결부분을 오프닝(opening) 시킨 후, Ti/Au로 이루어진 패드 금속(12)으로 금속배선 공정을 수행함으로써 HBT의 제작이 완성된다.By opening the pad connection part by reactive ion etching (RIE) using C 2 F 6 / CHF 3 plasma, and performing a metal wiring process with a pad metal (12) made of Ti / Au. The production of the HBT is complete.
이상 설명한 바와 같이 본 발명의 제조방법에 의하면, 다음과 같은 효과를 발휘할 수 있다.As explained above, according to the manufacturing method of this invention, the following effects can be exhibited.
첫째, 본 발명의 GayIn1-yP(y= 0.51) 에미터(Eg = 1.87eV)와 Ge베이스(Eg = 0.66)의 에너지 갭 차이(DEg1)는 1.21eV인 반면, 종래 A1물분율(x)로서 0.3을 사용한 AlxGa1-xAS/GaAs HBT의 에너지 갭 차이(DEg2)는 0.37eV에 불과하다. 따라서, esp{(DEg1- DEg2)/kT}만큼의 전류이득 증가를 얻을 수 있다. 이 값은 이론치로 볼 때 1014에 해당하는 큰 값이다.First, the energy gap difference (DEg 1 ) of the Ga y In 1-y P (y = 0.51) emitter (Eg = 1.87eV) and the Ge base (Eg = 0.66) of the present invention is 1.21 eV, whereas the conventional A1 water The energy gap difference (DEg 2 ) of Al x Ga 1-x AS / GaAs HBT using 0.3 as the fraction (x) is only 0.37 eV. Therefore, an increase in current gain by esp {(DE g1 -DE g2 ) / kT} can be obtained. This value is a large value corresponding to 10 14 in theory.
둘째, 에미터-베이스 간의 큰 가전도대 차이로 베이스에서 에미터로의 역 정공 주입을 억제하고, 에미터의 전자 주입효율을 낮추지 않으면서 고농도의 베이스층을 형성할 수 있다.Second, due to the large difference in the home appliances between the emitter and the base, it is possible to suppress the reverse hole injection from the base to the emitter and to form a high concentration of the base layer without lowering the electron injection efficiency of the emitter.
세번째는 에피성장의 측면에서 볼 때, GaAs콜렉터와 Ge 베이스가 우수한 격자정합을 이루며, 또한 GayIn1-yP(y = 0.51) 에미터와 Ge 베이스가 거의 완전한 격자정합을 이루기 때문에 이 물질계의 결함이 전기적 성능에 미치는 영향을 배제할 수 있다.Third, in terms of epitaxial growth, the GaAs collector and the Ge base achieve excellent lattice matching, and the Ga y In 1-y P (y = 0.51) emitter and the Ge base form almost complete lattice matching. The effect of the defects on electrical performance can be ruled out.
따라서, 본 발명에 의한 HBT는 고 전류이득을 요구하는 광수신기와 광전 집적회로 등의 입력버퍼, 및 고집적 회로의 출력단에 유용하게 적용될 수 있다.Therefore, the HBT according to the present invention can be usefully applied to an input buffer such as an optical receiver and a photoelectric integrated circuit requiring high current gain, and an output terminal of a highly integrated circuit.
Claims (9)
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