KR0130954B1 - Semiconductor memory device - Google Patents

Abstract

An improved semiconductor memory device capable of improving the processing accuracy of the memory node and increasing the capacitor capacity can be obtained. The semiconductor memory device includes a plurality of first field regions 2a (a) formed at a predetermined pitch in the direction in which the bit lines 15 face. The plurality of second field regions 2a (b) are formed in parallel with and adjacent to the rows formed by the plurality of first regions 2a (a), and are formed at the same pitch as described above. The first field area 2a (a) and the second field area 2a (b) are formed shifted by a quarter pitch in the direction in which the bit lines 15 face. Stacked capacitors having buried bit lines 15 under the cell plate electrodes 11 are provided in the first field region 2a (a) and the second field region 2a (b).

Description

Semiconductor memory

1 is a block diagram showing the structure of a general DRAM.

2 is an equivalent circuit diagram of a memory cell of a general DRAM.

3 is a perspective view of a silicon semiconductor substrate 1 having a separated oxide film formed on its main surface.

4 is a plan view of a semiconductor memory device according to a first example of the prior art.

5 is a cross-sectional view taken along the line A-B of FIG.

6A is a plan view showing a part of the field region taken from the semiconductor memory device shown in FIG.

6b is a cross-sectional view taken along line B-B of 6a.

FIG. 7 is a layout view of a region adjacent to a sense amplifier of a close packaged folded bit line cell array in the semiconductor memory device of FIG.

8 is a plan view of a semiconductor memory device according to a second conventional example.

9 is a cross-sectional view taken along the line A-B of FIG.

10 is a cross-sectional view taken along the line C-D of FIG.

Fig. 11A is a manufacturing process diagram of a semiconductor memory device having no buried bit line under the cell plate.

FIG. 11B is a manufacturing process diagram of a semiconductor memory device having a buried bit line structure under a cell plate. FIG.

12 is a plan view of a semiconductor memory device according to a third conventional example.

13 is a cross-sectional view taken along the line A-B of FIG.

FIG. 14 is a view showing field areas taken from the semiconductor memory device shown in FIG.

FIG. 15 is a perspective view showing problems of the main manufacturing process of the semiconductor memory device shown in FIG.

FIG. 16 is a cross-sectional view showing a problem of main steps in the manufacture of the semiconductor memory device shown in FIG.

FIG. 17 is a plan view showing a variation (memory nodes formed by shifting each other) of the prior art shown in FIG.

FIG. 18 is a sectional view of FIG. 17 along line D-D. FIG.

19 is a plan view of a semiconductor memory device according to an embodiment of the present invention.

FIG. 20 is a cross sectional view along line B-B in FIG. 19; FIG.

Fig. 21 is a layout view of a field region in the vicinity of a sense amplifier of a closed packaged folded bit line cell array in the semiconductor memory device according to the present invention.

22 is a perspective view showing the main steps in the manufacture of a semiconductor memory device according to the present invention;

23 is a plan view showing a modification of the semiconductor memory device of the 19th embodiment.

24 is a plan view near the end of the strain field region of FIG.

25 is a cross-sectional view of FIG. 24 taken along line B-B.

Fig. 26 is a relation between the width Wd of the field region and the length of the bird beak.

FIG. 27 is a plan view near the end of the field region of the embodiment of FIG. 19; FIG.

FIG. 28 is a difference diagram between the end region of the semiconductor device field region of FIG. 19 and the end region of the field region of the semiconductor device of FIG.

29 is a layout view of a field pattern according to another embodiment of the present invention.

* Explanation of symbols for main parts of the drawings

1: semiconductor substrate 2: field oxide film

2a (b): field region 4: transfer gate

6: source / drain area 11: memory node

13: cell plate 15: bit line

18, 19: interlayer insulating film 32: memory node contact hole

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a general semiconductor memory device, and more particularly, to an embedded bit line type semiconductor memory device for improving the processing accuracy of a memory node.

In recent years, the demand for semiconductor memory devices is rapidly increasing with the proliferation of information devices such as computers.

Functionally, there is a demand for a semiconductor memory device having a large memory capacity and operating at high speed.

Therefore, technology development for high integration, fast response, and high reliability of semiconductor memory devices has been in progress.

Among semiconductor memory devices, a dynamic random access memory (hereinafter referred to as DRAM) capable of random input and output of memory information is well known.

In general, a DRAM includes a memory cell, which is a storage area for storing a large amount of memory information, and peripheral circuits necessary for input and output to and from the outside.

1 is a block diagram showing the structure of a general DRAM.

Referring to FIG. 1, the DRAM 50 opens with a memory cell array 51 storing a data signal of storage information and a row for receiving an external address signal (a signal for selecting a memory cell constituting a unit memory circuit). Inputs a dress buffer 52, a row decoder 53 and a column decoder 54 that decode an address signal to designate a memory cell, a sense refresh amplifier 55 that amplifies and reads a signal stored in a specified memory cell, and data. And a data input buffer 56 and a data output buffer 57 for outputting, and a clock generator 58 for generating a clock signal.

The memory cell array 51 occupies a large area on the semiconductor chip.

Each of the plurality of memory cells that store the unit memory information is provided in a matrix in the memory cell array 51.

2 is an equivalent circuit diagram of a 4-bit memory cell constituting the memory cell array 51.

The illustrated memory cell is a structure consisting of one field effect transistor and one capacitor connected to the field effect transistor, a so-called one transistor to one capacitor type memory cell.

Since the memory cell of the above type has a simple structure so that the high density of the memory cell array can be easily improved, it is frequently used for DRAMs requiring a large capacity.

Referring to FIG. 3, transistors and capacitors are formed in the field region 2a of the surface of the semiconductor substrate 1.

One field region 2a is separated from the other field region 2a by the separation oxide film 2.

Table (1) below describes the characteristics of the various semiconductor devices described herein.

Hereinafter, the present invention will be described following the conventional first, second and third embodiments.

[Conventional Example 1]

4 is a plan view of a semiconductor device according to a first example of the prior art, and FIG. 5 is a cross-sectional view taken along line A-B in FIG.

Referring to the drawings, the semiconductor device includes a word line 4 and a bit line 15 that cross each other.

The transfer gate transistor and the stacked capacitor are provided near the word line 4 and the bit line 15 that cross each other.

The transfer gate transistor includes a pair of source / drain regions 6 and 6 formed on the surface of the silicon substrate 1 and a gate electrode (word line) 4 formed on the silicon substrate 1 via an insulating layer. Include.

The stacked capacitor includes a storage node (bottom electrode) 11 that contacts one source / drain region 6 and extends over the gate electrode 4.

The contact portion of the memory node 11 and the source / drain region 6 is called a memory node contact 50.

The capacitor insulating film 12 covers the surface of the memory node 11.

The cell plate 13 is provided on the storage node 11 with the capacitor insulating film 12 interposed therebetween.

An interlayer insulating film 20 is provided on the silicon substrate 1 to cover the transfer gate and the multilayer capacitor.

The bit line contact hole 52 is provided in the interlayer insulating film 20 exposing the bit line contact 51.

The bit line 15 is connected to one source / drain region 6 through the bit line contact hole 52.

The source / drain regions 6, the bit line contacts 51, and the storage node contacts 50 are formed in the field region 2a.

One field region 2a is separated from the other field region 2a by the field oxide film 2.

FIG. 6A is a plan view of the semiconductor device showing the entire field region taken from FIG. 4 for ease of understanding.

FIG. 6B is a cross-sectional view taken along line B-B in FIG. 6A.

4, 6A, and 6B, the plurality of field regions 2a are positioned at a predetermined pitch in the direction in which the bit lines 15 travel.

The field area 2a indicated by the reference letter b is provided in parallel after the line of the field area 2a indicated by the reference letter a.

Further, the field area 2a indicated by the reference character b is provided in parallel after the line of the field area 2a indicated by the reference character (b).

The field area 2a indicated by the reference character a and the field area 2a indicated by the reference character b are shifted by 1/2 pitch in the direction in which the bit lines travel.

Relationship between the line of the field area indicated by the reference letter (b) and the field area indicated by the reference letter (c), the field area 2a indicated by the reference letter (b) and the field area 2a indicated by the reference letter (c). Moreover, they are shifted from each other by 1/2 pitch and formed.

FIG. 7 shows the arrangement of the field regions in the vicinity of the contact portions of the sense amplifier 54 and the bit line 15 of the close packed folded bit line cell array.

In a semiconductor memory device having a half pitch array structure as well as a non-embedded bit line stacked cell structure as shown in FIG. 4 (first conventional example), a dimension SNx (memory node) is used to increase the capacitance of a capacitor. It is necessary to increase the length) and the dimension SNy (the width of the memory node).

However, since SNmin (distance between two adjacent storage nodes) and SNcp (distance from the end of the storage node to the end of the cell plate) of a predetermined dimension must be secured, there is a limit to the increase of SNx.

Further, in the semiconductor memory device according to the first conventional example, it is difficult to secure a sufficient capacity of the capacitor because SNx cannot be increased.

Although closed packaged folded bitline cell arrays are arranged in quarter pitches to minimize noise (Japan Institute of Electronics and Information Engineers, 1991 C-665 Puncture Meeting: The Institute of Electronnics, Information) and Communication Engineers of Japan, National Spring Meeting, 1991, C-665), a field region and a buried bit line stacked cell of a quarter pitch structure are not disclosed.

[Conventional Example 2]

In order to solve the problem of the first conventional example, a semiconductor memory device having a buried bit line stacked cell structure and a half pitch arrangement structure as shown in FIG. 8 has been proposed as the second conventional example.

9 is a cross-sectional view taken along the line A-B of FIG. 8, and FIG. 10 is a cross-sectional view taken along the line C-D of FIG.

In the figures, reference numerals are given to the same or corresponding parts as those shown in FIGS. 4 and 5.

Referring to the drawings, the bit line 15 is buried under the cell plate 13 due to the feature of the semiconductor memory device according to the second conventional example in which the cell plate 13 is formed on the bit line 15.

In such a structure, since there is no restriction on the dimension SNcp, the dimensions SNx, SNy can be increased.

However, if the dimensions SNx and SNy are increased in order to limit the processing accuracy of the storage node 11, the processing accuracy of the storage node 11 is deteriorated because the end of the storage node 11 is located close to the contact portion 51. Will be.

In order to solve the above problem, a semiconductor device according to the third conventional example has been proposed.

Before describing the semiconductor device according to the third conventional example, the manufacturing process of the non-embedded bit line semiconductor device shown in FIG. 4 and the manufacturing process of the buried bit line semiconductor device shown in FIG. 8 are compared with each other below. Explain.

FIG. 11A schematically illustrates a manufacturing process of an unfilled bit linear stacked cell.

The non-embedded bit linear semiconductor device is manufactured by sequentially forming the field oxide film 155, the transfer gate 156, the storage node 157, the cell plate 158, and the bit line 159.

Meanwhile, as shown in FIG. 11B, the buried bit linear semiconductor device sequentially forms the field oxide film 155, the transfer gate 156, the bit line 156, the memory node 157, and the cell plate 158. It is manufactured through a step.

[Conventional Example 3]

12 is a plan view of a semiconductor memory device according to the third conventional example,

FIG. 13 is a cross-sectional view taken along the line A-B of FIG.

In FIG. 12, it is assumed that the memory node 11 does not appear in the cross-sectional view cut along the A-B line.

However, although the memory node 11 deviates from the rules of drawing, it is conveniently shown in FIG. 13 to clarify the feature portion.

The third conventional example has a buried bit linear stacked cell structure and a half pitch arrangement structure as in the second conventional example.

14 shows a field area.

In the third conventional example, the rows of the field region a and the adjacent rows of the field region b are shifted with each other by a half pitch in the advancing direction of the bit line 15, and the field region 2a is formed by the bit lines ( And 15) arranged in an inclined shape in the advancing direction.

In FIG. 14, the area shown by the dotted line to clarify the shift in pitch indicates a virtual arrangement of the field areas assuming that the field areas 2a are not arranged in an oblique manner.

In the third conventional example, the source / drain regions 2a, the memory node contacts, and the bit line contacts are formed in the field regions arranged in an inclined manner, and the detailed description is described with reference to FIGS. 12 and 13.

12, 13, and 14, the field regions 2a are arranged in an inclined shape in the advancing direction of the bit line 15.

The gate electrode 4 is formed on the silicon substrate 1.

The interlayer insulating film 20 is formed to cover the gate electrode 4.

The bit line contact hole 51h is formed in the interlayer insulating film 20 so as to expose the bit line contact 51.

The bit line 15 is connected to one of the source / drain regions 6 via the bit line contact hole 51h.

The interlayer insulating film 18 is formed on the silicon substrate 1 so as to cover the bit line 15.

The storage node 11, which is the lower electrode of the capacitor, is formed on the interlayer insulating film 18.

The memory node 11 is connected to the other side of the source / drain region 6 by the memory node contact 50 through the memory node contact holes 50h formed in the interlayer insulating films 18 and 20.

Hereinafter, a problem of the semiconductor memory device according to the third conventional example will be described.

FIG. 15 is an enlarged perspective view of an end portion 11a of the memory node 11 of FIG.

12, 13 and 15, the dimensions SNx and SNy should be increased in order to limit the machining precision for widening the planar area of the storage node 11.

When the dimensions SNx and SNy are increased, it is assumed that the end 11a of the storage node 11 is located on the bit line contact hole 51h.

16 shows a cross-sectional view of the semiconductor device while patterning the memory node 11.

Since the end portion 11a of the storage node is located on the bit line contact hole 51h, the remaining portion 11b of the storage node 11 easily adheres to the inclined portion 18a in the recess of the interlayer insulating film 18. do.

Since the memory node 11 and the memory node 11 adjacent to each other are connected by the remaining portion 11b of the memory node 11, the memory nodes 11 and 11 will be short circuited.

The problem that the residual portion is present in the inclined portion 18a is also found in FIG. 17 in which the memory nodes 11 are formed in a shifted manner from each other.

More specifically, referring to FIG. 18 along the line D-D in FIG. 17, the end 11a of the storage node 11 is formed on the inclined portion 18a on the interlayer insulating film 18. As shown in FIG.

Therefore, an arrangement structure of 1/2 pitch length is used, and the problem of the residual portion in the inclined portion 18a is unavoidable even if the storage nodes are shifted with respect to each other.

On the other hand, in the buried bit linear semiconductor memory device shown in FIG. 13, in the buried bit linear memory cell shown in FIG. 13, since the word line 4 and the bit line 15 are close to each other, the word line 4 and The problem arises that the line capacitance between the bit lines 15 is increased.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide an improved buried bit linear semiconductor memory device capable of improving processing accuracy of a storage node.

Another object of the present invention is to provide a buried bit linear semiconductor memory device having an improved processing accuracy of a memory node whose memory node can be increased in a closed packaged folded bit line cell array.

It is another object of the present invention to provide an embedded bit linear semiconductor memory device in which the signal propagation delay time of a word line is shorter than that of an embedded bit linear capacitor.

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor memory device which performs input / output of memory information by a meery cell providing an intersection of a word line as a transfer gate and a bit line as a data line.

The semiconductor device includes a semiconductor substrate having a major surface.

The field oxide film is provided on the main surface of the semiconductor substrate.

On the main surface of the semiconductor substrate, a plurality of first field regions are provided which are separated from each other by the field oxide film and formed at predetermined pitches in the traveling direction of the bit lines.

Furthermore, the semiconductor memory device includes a plurality of second field regions formed by the plurality of first field regions described above and adjacent to and connected in parallel to rows formed at the same pitch as described above.

The first and second field areas are shifted from each other by a quarter pitch in the advancing direction of the bit line.

Each of the first and second field regions includes (a) a transfer gate provided on the field region, (b) a pair of source / drain regions provided on the main surface of the semiconductor substrate on both sides of the transfer gate, and (c) A first interlayer insulating film formed on the semiconductor substrate covering the transfer gate; (d) a bit line contact hole provided on the first interlayer insulating film to expose one surface of the source / drain region; and (e) the first interlayer insulating film; A bit line disposed on the interlayer insulating film and contacting one of the source / drain regions through the bit line contact hole, (f) a second interlayer insulating film formed on the semiconductor substrate and covering the bit line, and (g) the A memory node contact hole provided in the second interlayer insulating film to expose the other surface of the source / drain region, and (h) the other side of the source / drain region through the memory node contact hole. A memory node provided on the second interlayer insulating film so as to be connected, (i) a capacitor insulating film covering the surface of the memory node, and (j) interposed therebetween to cover the memory node with the capacitor insulating film interposed therebetween. It includes a cell plate.

According to a preferred embodiment of the present invention, the first and second field regions are arranged obliquely in the direction of travel of the bit lines.

According to a more preferred embodiment of the present invention, the transfer gate has a polyside structure in which a high melting point metal silicide is formed on polycrystalline silicon.

The semiconductor memory device of the present invention having a buried bit line under the cell plate has a plurality of first field regions formed in a predetermined pitch in the advancing direction of the bit lines, and adjacent to rows of the first field region in parallel. A plurality of second field regions formed at the same pitch as described above is included.

The first field area and the second field area are formed shifted by a quarter pitch in the traveling direction of the bit line.

More specifically, the field regions are arranged so that they do not appear above the bit line contact holes when the ends of the storage nodes pattern the storage nodes.

The above and other objects, features, aspects, and advantages will become more apparent from the following detailed description of the invention in conjunction with the accompanying drawings.

EXAMPLE

19 is a plan view showing a semiconductor memory device having a buried bit linear stacked cell structure according to an embodiment of the present invention.

FIG. 20 is a cross-sectional view taken along line B-B in FIG. 17, and FIG. 21 is a plan view showing the arrangement of the field regions in the vicinity of the sense amplifier of the closed-packed folded bit line cell array.

On the main surface of the semiconductor substrate 1, a plurality of first field regions 2a indicated by (a) are formed at predetermined pitches in the advancing direction of the bit line 15.

The plurality of second field regions 2a denoted by (b) are formed in parallel adjacent to the plurality of first field regions 2a denoted by (a) and are formed at the same pitch as described above.

The first field region 2a indicated by (a) and the second field region 2a indicated by (b) are formed shifted by 1/4 pitch in the traveling direction of the bit line 15.

The structure of the semiconductor memory device according to the embodiment will also be described with reference to FIG.

The transfer gate 4 is provided on the field region 2a.

Source / drain region pairs 6 and 6 are arranged on both sides of the transfer gate 4 and on the major surface of the silicon substrate 1.

Referring to FIG. 20, the source / drain region pairs 6 and 6 are formed to extend in an oblique manner in the traveling direction of the bit line 15.

The transfer gate 4 has a lamination structure of the polycrystalline silicon film 4b and the high melting point metal silicide film 4a.

The high melting point metal silicide film 4a is made of, for example, MoSi2, WSi2, TaSi2, or TiSi2.

The first interlayer insulating film 19 is provided on the silicon substrate so as to cover the transfer gate 4.

The bit line contact hole 31 is provided in the first interlayer insulating film 19 so as to expose one surface of the source / drain region 6.

The bit line 15 is provided on the first interlayer insulating film 19 so as to contact (bit line contact) one side of the source / drain region 6 via the bit line contact hole 31.

The second interlayer insulating film 18 is provided on the silicon substrate 1 so as to cover the bit line 15.

The memory node contact holes 32 are provided in the first and second interlayer insulating films 19 and 18 so as to expose the surface of the other source / drain regions 6 (memory node contacts 17).

The patterned memory node 11 is provided in a second interlayer insulating film connected to another source / drain region 6 (memory node contact 17) through the memory node contact hole 32.

The capacitor insulating film 12 covers the surface of the memory node 11.

The cell plate 13 is provided on the storage node 11 with the capacitor insulating film 12 therebetween.

22 is an enlarged perspective view showing the vicinity of the end 11a of the storage node 11.

Referring to Figs. 19, 20, 21, and 22, since the rows of adjacent field regions are formed shifted with each other by a quarter pitch, the dimensions SNx and SNy limit the processing accuracy of the storage node. It will not be formed on top of the bit line contact hole even if it is increased.

As a result, the surface of the interlayer insulating film 18 positioned below the end 11a of the memory node 11 becomes flat, and the remaining portion of the memory node 11 is placed on the interlayer insulating film 18 when the memory node 11 is patterned. It will not be left behind.

In addition, since the gate electrode 4 has a polyside structure, its internal connection resistance will be lowered and the signal propagation delay time will be shorter.

In the above embodiment with reference to FIG. 19, in the case where the planar structure of the field region 2a is shown in a hexagonal shape extending in an obliquely extending manner, the memory node contact hole 17 is surrounded by two adjacent sides. It is installed in the hexagonal part.

In contrast, a planar structure of the field region 2a may be an octagonal structure including a quadrangle 50, a parallelogram 51, and a quadrangle 52, as shown in FIG.

However, the formation of the field region 2A in the structure of FIG. 23 causes the problem described below.

Referring to FIG. 24, the structure of the field region 2a is octagonal, and the end portion 2ab of the field region is surrounded by three sides by the field oxide film 2.

The field oxide film 2 has a beak 2b as shown in FIG. 25 (sectional view taken along the line A-A in FIG. 24).

Therefore, when the end portion 2ab of the field region is surrounded on three sides by the field oxide film 2 as shown in FIG. 24, the end portion 2ab region of the field region is defined by the occupied region of the beak 2b. Is reduced.

In contrast, if the structure of the field region has a hexagon, the end portion 2ab of the field region is surrounded on two sides by the field oxide film 2 as shown in FIG.

Thus, as shown in FIG. 28, the end 2ab of the field region when surrounded by two sides is the end 2ab of the field region when surrounding the region S1 of the shade portion with the field oxide film 2, as shown in FIG. Greater than the area of).

The increase in the area of the end 2ab of the field region means that the area of the end 2ab of the field region can be made larger than the diameter of the storage node contact hole formed in the end 2ab of the field region.

This allows for an increase in the contact area between the memory node and the substrate, resulting in smaller resistance therebetween.

Therefore, the arrangement of the field regions as shown in FIG. 19 provides an advantage of easier writing in the memory cells of the DRAM formed in the regions as compared with the case of the arrangement of the field regions in FIG.

In the above-described embodiment, referring to Fig. 21, the field regions 2a are arranged obliquely in the direction of travel of the bit lines.

However, the present invention is not limited to the above.

As shown in FIG. 29, when the field regions 2a are arranged in parallel in the advancing direction of the bit lines 15, the same effects as in the above embodiment can be obtained.

As described above, the semiconductor memory device according to the present invention having a buried bit line under the cell plate has a plurality of first field regions formed at a predetermined pitch in the advancing direction of the bit lines, and adjacent to and parallel to the rows of the first field region. And a plurality of second field regions formed at the same pitch as described above.

The first field area and the second field area are shifted from each other by 1/4 pitch in the advancing direction of the bit line.

In other words, the field regions are arranged so that the ends of the storage nodes do not appear above the bit line contact holes when patterning the storage nodes. Therefore, the processing accuracy of the storage node is improved, and a highly reliable semiconductor memory device can be obtained.

Although the invention has been described and illustrated in detail, it is to be understood that the spirit and scope of the invention is the same as that of the description and illustration, and without limitation, being limited only by the appended claims.

Claims (7)

1. A semiconductor memory device for inputting and outputting storage information using a memory cell having a word line as a transfer gate and a bit line as a data line, comprising: a semiconductor substrate 1 having a main surface and a main surface of the semiconductor substrate 1; The plurality of first field regions 2a (a) separated from each other by the provided field oxide films 2 and formed at a predetermined pitch in the advancing direction of the bit lines 15, and the plurality of first field regions 2a. a plurality of second field regions 2a (b) formed in parallel adjacent to the row formed by (a)) and formed at the same pitch as the pitch, and including the first field regions 2a (a). ) And the second field area 2a (b) are shifted from each other by 1/4 pitch in the traveling direction of the bit line, and the first and second field areas 2a and 2a are respectively (a) fields. A transfer gate 4 provided on an area, and (b) the peninsulas on both sides of the transfer gate 4; A pair of source / drain regions 6 and 6 provided on the main surface of the substrate 1, (c) a first interlayer insulating film 19 provided on the semiconductor substrate 1 covering the transfer gate, and (d) A bit line contact hole 31 provided in the first interlayer insulating film 19 to expose one surface of the source / drain region 6, and (e) a bit line contact hole provided on the first interlayer insulating film. A bit line 15 contacting one of the source / drain regions through a hole 31, and (f) a second interlayer insulating film 18 provided on the semiconductor substrate 1 to cover the bit line 15. And (g) a memory node contact hole 32 provided in the second interlayer insulating film 18 to expose the other surface of the source / drain region 6, and (h) the memory node contact hole (h). A storage node 11 provided on the second interlayer insulating film 18 so as to be connected to the other side of the source / drain region through 32), and (i) A capacitor insulating film 12 covering the surface of the memory node 11 and (j) a cell plate 13 disposed on the semiconductor substrate to cover the memory node with the capacitor insulating film 12 interposed therebetween. A semiconductor memory device, characterized in that. The semiconductor memory device according to claim 1, wherein the planar structure of the first and second field regions is hexagonal. 3. The semiconductor memory device according to claim 2, wherein said memory node contact hole (32) is formed in a portion surrounded by two adjacent side surfaces of said hexagon. 2. The semiconductor memory device according to claim 1, wherein said first and second field regions (2a (a), 2a (b)) are arranged in an oblique shape in a direction in which said bit lines travel. 2. The semiconductor memory device according to claim 1, wherein said transfer gate (4) has a polyside structure in which high melting point metal silicide is formed on polycrystalline silicon. 4. The polyside structure according to claim 3, wherein the transfer gate 4 comprises MoSi ₂ / poly-Si, Wsi ₂ / poly-Si, TaSi ₂ / poly-Si, and TiSi ₂ / poly-Si. It has a semiconductor memory device characterized by the above-mentioned. The semiconductor memory device according to claim 1, wherein the memory node (11) is patterned such that one end of the memory node (11) is located in a region other than the region where the bit line contact hole (31) is formed.