KR0129203B1 - Crc computation circuit - Google Patents

Crc computation circuit

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KR0129203B1
KR0129203B1 KR1019940033312A KR19940033312A KR0129203B1 KR 0129203 B1 KR0129203 B1 KR 0129203B1 KR 1019940033312 A KR1019940033312 A KR 1019940033312A KR 19940033312 A KR19940033312 A KR 19940033312A KR 0129203 B1 KR0129203 B1 KR 0129203B1
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data
parallel
flip
seed
output
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KR1019940033312A
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Korean (ko)
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KR960025168A (en
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이원로
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문정환
금성일렉트론주식회사
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1004—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's to protect a block of data words, e.g. CRC or checksum
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17306—Intercommunication techniques
    • G06F15/17312—Routing techniques specific to parallel machines, e.g. wormhole, store and forward, shortest path problem congestion

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Computer Security & Cryptography (AREA)
  • Quality & Reliability (AREA)
  • Detection And Correction Of Errors (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

A high speed receiving clock is an octal divided thru D type flip-flops(111-114). The flip-flops(121-128) clocked by the divided clock signal latches receiving data which keeps high speed data rate. The data latched by the flip-flop(121-128) respectively are output in parallel data thru flip-flop(131-138). The parallel data output from a series/parallel converter(100) and CRC input data are exclusive or operated thru exclusive or calculated and formed as CRC output data.

Description

고속병렬 씨알씨 계산회로High speed parallel grain seed calculation circuit

제1도는 본 발명위 고속병렬 씨알씨 계산회로에 대한 블록도.1 is a block diagram of a high-speed parallel grain seed calculation circuit according to the present invention.

제2도는 제1도에서 직렬/병렬변환부 상세 회로도.FIG. 2 is a detailed circuit diagram of a serial / parallel converter in FIG.

제3도는 제1도에서 병렬씨알씨 계산부의 상세 회로도.3 is a detailed circuit diagram of the parallel grain calculator in FIG.

제4도는 제1도에서 씨알씨에러 판정부의 상세 회로도.4 is a detailed circuit diagram of the seed error determining unit in FIG.

제5도는 제2도 각부의 파형도.5 is a waveform diagram of each part of FIG.

제6도는 제3도의 출력데이타 산출 테이블.6 is an output data calculation table of FIG.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

100 : 직렬/병렬변환부 200 : 병렬씨알씨 계산부100: serial / parallel converter 200: parallel grain calculator

300 : 씨알씨에러 판정부300: seed error determination unit

본 발명은 고속의 근거리통신망 콘트롤러에서 요구되는 CRC계산기술에 관한 것으로, 특히 고속의 데이터를 레이트를 갖는 데이터 통신에서 CRC(CRC: Cyclic Rrdundancy Ccheck)계산에 적당하도록한 고속병렬 씨알씨 계산회로에 관한 것이다.The present invention relates to a CRC calculation technique required in a high-speed local area network controller, and more particularly, to a high-speed parallel grain seed calculation circuit suitable for calculating a CRC (Cyclic Rrdundancy Ccheck) in high-speed data communications. will be.

일반적인 CRC계산방법으로서 익스클루시브 오아 게이트와 시프트레지스터를 이용한 직렬 CRC계산방법 이 사용되는데, 입력 데이터 레이트가 고속화되면서 보다 향상된 CRC계산방법과 병렬 CRC계산방법이 제안되었다.As a general CRC calculation method, a serial CRC calculation method using an exclusive oar gate and a shift register is used. As the input data rate is increased, an improved CRC calculation method and a parallel CRC calculation method have been proposed.

이와 같은 병렬 CRC계산방법은 수학적으로 증명되어 발표되었고 이를 기반으로 최적화된 여러 가지의 병렬 CRC계산방법이 특허로 등록되었으며 참고자료는 하가와 같다.Such parallel CRC calculation method has been mathematically proved and published, and several optimized parallel CRC calculation methods have been registered as patents, and reference materials are as follows.

① IEEE Transactions on Communication VOL.40,NO.4.April 1992 High-Speed Parallel Circuits in VLSI P653~657① IEEE Transactions on Communication VOL.40, NO.4.April 1992 High-Speed Parallel Circuits in VLSI P653 ~ 657

② Method and Apparatus for CRC Computation(5,130,991)1992② Method and Apparatus for CRC Computation (5,130,991) 1992

③ :CRC calculation apparatus having reduced ouput bus size(4,720,830)외 3편(4,712,215,4,720,831,4,723,243) 1988③: CRC calculation apparatus having reduced ouput bus size (4,720,830) and 3 films (4,712,215,4,720,831,4,723,243) 1988

그러나 이와 같은 일반적인 CRC계산방법은 고속의 수신클럭에 동기되거나 병렬CRC로직이 복잡하여 많은 게이트들을 사용하고 이로 인하여 처리시간이 많이 소요될 뿐더러 칩사이즈면에서 불리한 점을 갖게 된다.However, such a general CRC calculation method uses a large number of gates because it is synchronized to a high-speed reception clock or a complicated parallel CRC logic, which requires a lot of processing time and disadvantages in terms of chip size.

따라서 본 발명의 목적은 고속 데이터 클럭(100MHZ)에 동기되어 입력되는 데이터를 위상이 다른 8분주클럭을 발생시켜 낮은 주파수로도 병렬 처리 할 수 있도록 하고, 병렬 알고리즘을 이용 하여 전체 CRC게산로직을 최적화 시켜 사용 게이트수를 줄인 CRC계산회로를 제공함에 있다.Accordingly, an object of the present invention is to generate data in synchronization with a high speed data clock (100MHZ) to generate parallel dividing clocks with different phases at low frequencies, and to optimize the overall CRC calculation logic using a parallel algorithm. The present invention provides a CRC calculation circuit which reduces the number of gates used.

제1도는 상기의 목적을 달성하기 위해 일실시예를 보인 고속병렬 씨알씨 계산회로에 대한 블록도로서 이에 도시한 바와 같이, 고속의 수신클럭(RXC)를 분주하고, 그 분주된 클럭신호에 의해 클럭킹되는 플립플롭으로 고속의 데이터 레이트를 갖는 수신데이타(RXD)를 레치한 후 바이트단위로 클럭킹되는 바이트클럭신호(Byte-CLK)를 이용하여 병렬데이타 PARA7:0로 출력하는 직렬/병렬변환부(100)와, 상기 직렬/병렬변환부(100)에서 출력도는 병렬데이타 PARA7:0와 씨알씨에러 판정부(300)에서 귀환되는 씨알씨 입력데이타 CRC7:0를 병렬씨알씨 알고리즘으로 익스클루시브오아연산하여 씨알씨출력데이타 oCRCl7:0를 생성하는 병렬씨알씨 계산부와 Byte 단위로 클럭킹되는 클럭신호 (RX_CLK8)를 이용하여 상기 병렬씨알씨 계산부(200)에서 출력되는 데이터 oCRC7:0를 래치한후 앤드조합하여 에러유무를 판정하는 씨알씨 에러 판정부(300)로 구성한 것으로, 이와 같이 구성한 본 발명의 작용 및 효과를 첨부한 제2도 내지 제6도를 참조하여 상세히 서명하면 다음과 같다.FIG. 1 is a block diagram of a high-speed parallel CR calculation circuit showing an embodiment for achieving the above object. As shown in FIG. 1, a high-speed receiving clock RXC is divided, and the divided clock signal is divided by the divided clock signal. Serial / parallel conversion unit which latches received data (RXD) having a high data rate with the flip-flop clocked and outputs the parallel data PARA7: 0 using the byte clock signal (Byte-CLK) clocked in bytes. 100), and the output diagram of the serial / parallel conversion unit 100 includes the parallel data PARA7: 0 and the seed input data CRC7: 0 returned from the seed error determining unit 300 by the parallel seed algorithm. Data oCRC7: 0 output from the parallel seed calculation unit 200 is obtained by using the parallel seed calculation unit generating OCRCl7: 0 by OA calculation and the clock signal RX_CLK8 clocked in byte units. It is composed of the seed error determination unit 300 to determine the presence of the error by the end combination after the molarization, and in detail with reference to FIGS. 2 to 6 attached to the operation and effect of the present invention configured as described above is as follows. .

입력동기신호(SYN)의 하이액티브점을 시작점으로 하여 제5도의 (나)와 같은 고속의 수신클럭(RXC)이 D형 플립플롭(이하, 플립플롭이라 칭함)(111-114)을 통해 제5도의 (다)-(차)와같이 8분주 되고, 그 분주된 클럭신호에 의해 클럭킹되는 플립플롭(121-128)은 고속의 데이터 레이트(RATE)를 갖는 제 5도의 (가)와 같은 수신 데이터(RXD)를 래치하게 된다.With the high active point of the input synchronization signal SYN as a starting point, a fast receiving clock RXC as shown in (b) of FIG. 5 receives a D-type flip-flop (hereinafter referred to as flip-flop) 111-114. Flip-flops 121-128, which are divided by 8 as shown in (C)-(D) of 5 degrees and clocked by the divided clock signal, receive as shown in (A) of FIG. 5 having a high data rate (RATE). The data RXD is latched.

또한 상기 플립플롭(121-128)에 각기 래치된 데이터들은 바이트단위로 클럭킹되는 바이트클럭신호(Byte- CLK)에 의해 플립플롭(131-138)을 통해 병렬데이타 PARA7:0로 출력된다.In addition, the data latched to the flip-flops 121-128 are output as parallel data PARA7: 0 through the flip-flops 131-138 by the byte clock signal Byte-CLK clocked in byte units.

상기 직렬/병렬변환부(100)에서 출력되는 병렬데이타 PARA7:0와 씨알씨 입력 데이터 oCRC7:0를 익스클루시브오아게이트(201-233)를 통해 익스클루시브오아연산하여 씨알씨 출력데이타 CRC7:0를 생성하게 되며, 여기서, 하기와 같은 계산로직을 이용히여 최적화할 수 있게 하였다.The parallel data PARA7: 0 and the seed input data oCRC7: 0 outputted from the serial / parallel conversion unit 100 are subjected to exclusive operation through the exclusive oar gates 201-233 to receive the seed output data CRC7: It generates 0, where it can be optimized using the following calculation logic.

단 상기는 익스클루시브오아연산을 의미하며, A8-H8은 씨알씨출력데이타 oCRC7:0을 의미한다.Only above Means Exclusive O-Acid, and A8-H8 means CR output data oCRC7: 0.

byte단위로 클럭킹되는 클럭신호 RX_CLK8에 의하여 상기 병렬씨알씨계산부(200)에서 병렬씨알씨 계산되어 출력되는 데이터CRC7:0가 플립플롭(301-309)에 래치되고 그 래치된 데이터가 수신클럭신호(RX_CLKS)에 의해 출력되는데 이때 그 플립플롭(301-309)의 비반전출력단자(Q)를 통해 출력되는 씨알씨 데이터CRC7:0는 상기 병렬씨알씨 계산부(200)의 입력으로 귀환되고 반전출력단자(QN)을 통해 출력되는 데이터는 앤드게이트(312)에 의해 앤드조합한 후 래치(314)의 입력 데이터로(D)로 공급된다.Data CRC7: 0, which is parallel-calculated by the parallel CAL calculator 200 and outputted by the clock signal RX_CLK8 clocked in byte units, is latched to the flip-flops 301-309 and the latched data is received. The CR data CRC7: 0 outputted through the non-inverting output terminal Q of the flip-flops 301-309 is fed back to the input of the parallel seed calculation unit 200 and inverted. Data output through the output terminal QN is AND-combined by the AND gate 312 and then supplied to the input data D of the latch 314.

그런데 패킷의 최종데이타가 입력될 때 액티브 로우로 되는 입력신호 LABIT에 의해 상기 래치(314)에 래치된 데이터가 출력되므로 결과적으로 상기 플립플롭(301-309)에 래치된 데이터가 모두 0이면 그 래치(314)에서 CRC_OUT가 하이로 출력되어 정상임을 나타내고 그렇지 않으면 로우로 나타내어 에러임을 나타내게 된다.However, when the last data of the packet is input, the latched data is output to the latch 314 by the input signal LABIT which becomes active low. As a result, when the data latched to the flip-flops 301-309 is all 0, the latch is latched. At 314, CRC_OUT is output high, indicating that it is normal, otherwise it indicates low, indicating an error.

이상에서 상세히 설명한 바와 같이 본 발명은 고속의 데이터 클럭에 동기되어 입력되는 데이터를 위상이 다른 8분주클럭을 발생시켜 낮은 주파수로도 병렬처리할 수 있도록 하고 병렬 알고리즘을 이용하여 전체CRC계산로직을 최적화시킴으로써 안정된 동작을 보장하고 칩사이즈를 줄일 수 있는 효과가 있다.As described in detail above, the present invention generates 8-division clocks having different phases in synchronization with a high-speed data clock to perform parallel processing at low frequencies and optimizes the overall CRC calculation logic using a parallel algorithm. This ensures stable operation and reduces chip size.

Claims (3)

고속의 수신클럭(RXC)을 분주하고 그 분주된 클럭신호에 의해 클럭킹되는 플립플롭으로 고속의 데이터레이트를 갖는 수신데이타(RXD)를 레치한 후 바이트 단위로 클럭킹되는 바이트클럭신호(Byte-CLK)를 이용하여 병렬데이타 PARA7:0로 출력하는 직렬/병렬변환부(100)와, 상기 직렬/병렬변환부(100)에서 출력되는 병렬데이타 PARA7:0를 씨알씨에러 판정부(300)에서 귀환하는 씨알씨입력데이타 CRC7:0를 병렬씨알씨 알고리즘으로 익스클루시브오아연산하여 씨알씨출력데이타 oCRC7:0를 생성하는 병렬씨알씨 계산부(200)와 Byte단위로 클럭킹되는 클럭신호(RX_CLK8)를 이용하여 상기 병렬씨알씨 계산부(200)에서 출력되는 데이터 CRC7:0를 래치한 후 앤드 조합하여 에러 유무를 판정하는 씨알씨에러 판정부(300) 로 구성한 것을 특징으로 하는 고속병렬 씨알씨 계산회로.A byte clock signal (Byte-CLK) that is clocked by byte unit after dividing the fast reception clock RXC and latching the reception data RXD having a high data rate with a flip-flop clocked by the divided clock signal. Serial-parallel conversion unit 100 outputting parallel data PARA7: 0 and parallel data PARA7: 0 output from serial-parallel conversion unit 100 by using Using the parallel seed calculation unit 200 to generate the seed output data oCRC7: 0 by using the parallel seed algorithm with the parallel seed seed algorithm CRC7: 0, the clock signal (RX_CLK8) clocked in byte units is used. And a CR error determining unit 300 which latches the data CRC7: 0 output from the parallel seed calculation unit 200 and then combines the AND to determine whether there is an error. 제 1항에 있어서 직렬/병렬변화부(100)는 고속의 수신클럭(RCX)을 8분주하는 플립플롭(111-114)과 상기 플립플롭(111-114)의 출력신호에 의해 클럭킹되어 고속의 데이터 레이트를 갖는 수신데이타(RXD)를 래치하는 플립플롭(121-128)과, 상기 플립플롭(121-128)에 래치된 데이터를 전달받아 바이트단위로 클럭킹되는 바이트글럭신호(Byte-CLK)에 의해 병렬데이타 PARA7:0로 출력하는 플립플롭(131-138)로 구성한 것을 특징으로 하는 고속병렬 씨알씨 계산회로.The serial / parallel changer 100 is clocked by the flip-flops 111-114 and the output signals of the flip-flops 111-114. The flip-flops 121-128 latching the reception data RXD having a data rate, and the byte-block signals Byte-CLK are clocked in byte units by receiving the data latched in the flip-flops 121-128. A high-speed parallel grain seed calculation circuit comprising: flip-flops (131-138) outputting parallel data PARA7: 0. 제 1항에 있어서, 씨알씨에러 판정부(300)는 상기 직렬/병렬변환부(100)에서 출력되는 테이타 oCRC(7:0)를 래치하여 비반전출력단자(Q)를 통해서는 씨알씨 데이터 CRC(7:0)로 출력하고, 반전출력단자(QN)를 통해서는 앤드케이트(312)의 입력으로 출력하는 플립플롭(301-309)와, 입력신호(LABIT)에 의해 상기 앤드게이트(312)에서 출력되는 데이터를 래치하여 에러판정신호를 출력하는 래치(314)로 구성한 것을 특징으로 하는 고속병렬 씨알씨 계산회로.The seed error determining unit 300 latches the data oCRC (7: 0) outputted from the serial / parallel conversion unit 100 and through the non-inverting output terminal (Q). Flip-flops 301-309 that output to the CRC (7: 0) and output to the input of the end gate 312 through the inverting output terminal QN, and the AND gate 312 by the input signal LABIT. And a latch (314) for latching the data outputted from the circuit) and outputting an error determination signal.
KR1019940033312A 1994-12-08 1994-12-08 Crc computation circuit KR0129203B1 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100439225B1 (en) * 2000-07-13 2004-07-05 엘지전자 주식회사 A circuit of error inspection for high rate data

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100439225B1 (en) * 2000-07-13 2004-07-05 엘지전자 주식회사 A circuit of error inspection for high rate data

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