KR0126778B1 - Offset detector apparatus of image signal - Google Patents

Abstract

A device of detecting offset that is the difference in reference levels between video signals includes first and second voltage-current converters for receiving two video signals to be compared, respectively, and generating current signals corresponding to the video signals, a switch for receiving the outputs of the voltage-current converters and outputting them only during the synchronous signal period of the video signal, first and second current mirrors for generating duplicated currents identical to the reference currents, a feedback controller for feedback-controlling the reference current of the second current mirror to allow the first and second duplicated currents to be identical to each other according to the difference between them, and an output means for obtaining the difference between the duplicated currents generated by the first and second current mirrors during the period when current of the switch is not supplied to the reference current of the first and second current mirror, and outputting the difference as a current value corresponding to the offset of the video signal received by an input port.

Description

Device for detecting offset of video signal

1 is a circuit diagram showing a preferred embodiment of the offset detection apparatus according to the present invention.

FIG. 2 is a waveform diagram illustrating the operation of the apparatus shown in FIG.

3 is another waveform diagram for explaining the operation of the apparatus shown in FIG.

The present invention relates to an apparatus for detecting an offset between video signals.

In analog video signal processing such as correlation detection between scan lines and drop out compensation, it is important to match the reference levels of the two video signals. For example, in detecting the correlation between the scanning lines, a difference between the input signal and the output signal of the 1H (H is a horizontal scanning period) delay element is detected. At this time, an error occurs if the reference signals between the two signals are not matched.

For this purpose, an offset detection apparatus for accurately and stably detecting the difference between the reference levels between the two video signals, that is, the offset, is required.

Accordingly, an object of the present invention is to provide an offset detection device for accurately detecting an offset between video signals.

According to an aspect of the present invention, there is provided an offset detection apparatus comprising: first and second voltage current converters for respectively introducing two video signals to be compared and generating a current signal corresponding to each video signal; A switching unit for inputting an output of the voltage-current converting unit and outputting it only during a synchronization signal section of the image signal; First and second current mirrors for introducing a current signal output from the switching unit to the reference current side and generating a radiated current equivalent to the reference current; Feedback control unit for feedback-controlling the reference current of the second current mirror so that the first and second radiated currents become equal by the difference between the first and second radiated currents generated in the first and second current mirrors. ; And obtaining a difference between the radiated currents generated in the first and second current mirrors during a period in which the current at the switching unit is not provided on the reference current side of the first and second current mirrors, and the image signal flowing into the input terminal. And an output unit for outputting a current value corresponding to an offset of.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a circuit diagram showing a preferred embodiment of the offset detection apparatus according to the present invention. In FIG. 1, QN3 and QN5 constitute a voltage-current conversion unit in the gist of the present invention, and are NPN BIPOLAR transistors for voltage current-converting the video signals VB1 and VB2 to be compared, respectively.

MN88, NM89, MN92, and MN93 constitute a switching unit in the gist of the present invention, and are N-channel MOS transistors for outputting the current signal converted by QN3 and QN5 only in a synchronous signal section of a video signal.

MP10 and MP15 constitute a first current mirror according to the gist of the present invention. The currents corresponding to the synchronous ends of the current-converted second video signal VB2 are respectively inputted as reference currents, and the corresponding radiated currents are input. It is a generating P-channel MOS transistor.

MP14 and MP2 constitute a second current mirror according to the gist of the present invention. The currents corresponding to the synchronous ends of the current-converted first video signal VB1 are respectively inputted as reference currents, and the corresponding radiated currents are input. It is a generating P-channel MOS transistor.

QN7 and QN12, capacitors C9 and C28, N-channel MOS transistors MN90 and MN91, and transmission gates I23 and I27 constitute the feedback control unit of the present invention, and are the first and second in MP2 and MP15. The reference current of MP14 is feedback-controlled so that the first and second radiated currents are equal by the difference of the radiated currents.

The operation of the apparatus shown in FIG. 1 will be described in detail with reference to FIGS. 2 and 3. 2A and 2B are diagrams showing the first video signal VB1 and the second video signal VB2 to be compared, respectively, while FIGS. 2C and 2D are generated in the synchronization section of the video signal shown in FIGS. 2A and 2B. The pulse signal CLPP and the inverted pulse signal CLPM are shown. Here, the first video signal VB1 and the second video signal VB2 shown in FIGS. 2A and 2B have a difference by an offset voltage Voffset.

As is well known, the reference level of the video signal includes a synchromatic tip and a pedestal, but since the pedestal is a part affected by the direct current of the video signal, in the present invention, the level of the synchini of the video signal is sampled. The offset value is used as the difference value of the values.

The two video signals VB1 and VB2 to be compared are converted into current signals by QN3 and QM5.

If the collector current of QN3 is Iin, the collector current of QN5 can be expressed as (Iin + Ioffset). Here, Ioffset is a current generated by the offset of the video signals VB1 and VB2.

The switching unit including four N-channel MOS transistors (MN88, MN89, MN92, and MN93) intercepts the collector currents of QN3 and QN5 by a sampling pulse (CLPP) generated only in the synchronization period of the video signal. Output the current signal corresponding to. That is, the synchronization level of the voltage-current image signal is sampled.

Here, CLPP is a normal pulse signal used for clamping, and the CLPM signal is a pulse signal in which the CLPP signal is inverted. As shown in FIGS. 2C and 2D, the CLPP and CLPM signals are signals that stand or fall in the synchronization section of VB1 and VB2. The section where the CLPP signal becomes high is called Ts, and the section that becomes low is Th. It is called.

During the Ts period, MN93 and MN89 are turned off and MN88 and MN92 are turned on. As a result, the drain current of MN88 becomes the collector current Iin of QN3, and the drain current of MN92 becomes the collector current Iin + Ioffset of QN5.

The drain current of MN88 and the drain current of MN92 are provided to MP10 and MP14, respectively.

Accordingly, the drain current Imp10d of MP10 becomes (Iin + Imn90d), and the drain current Imp14d of MP14 becomes (Iin + Ioffset + Imn91d).

Here, Imn90d and Imn91d are drain currents of MN90 and MN91, respectively.

The drain current Imd15d of MP15 and the drain current Imp2d of MP2 become Imp15d- (Iin + Imn90d) and Imp2d = (Iin + Ioffset + Imn91d) by the current mirror relationship between MP10 and MP14, respectively. Imp2d and Imp15d are provided to QN7 and QN12 as reference and radiated currents, respectively.

On the other hand, the transmission gates I23 and I27 are turned on during the period Ts at which the CLPP signal becomes high level so that the reference voltage Vref is applied to the gate (gat) side of the MN90, and the drain current of MP2 and the drain current of MP15 are applied to the gate side of the MN91. The charging voltage Vs generated by charging the capacitor C9 by the difference signal is applied.

The charging current for charging the capacitor C9 includes the drain current of MP2 and the drain current of MP15 flowing through the transmission gate I23 from the collector side of QN12 so that the collector current of QN7 and QN12 constituting the current mirror maintains the same value. Is the difference signal.

On the other hand, Vref is charged in the capacitor C8 so that Vref is maintained on the gate side of the MN90.

Here, the transmission gates I23, I24, and I27 are known bidirectional control elements whose transmission directions are determined by signals applied to two control terminals.

The drain current Imp14d of the MP14 is changed by the charging voltage Vs of the capacitor C8, and as a result, the drain current Imp2d of the MP2 is changed. As a result, the charging current flowing into the capacitor C8 changes. This operation is continued until the drain current Imp2d of MP2 and drain current Imp15d of MP15 become equal.

3A to 3C are waveform diagrams showing changes in Vh and Vs during the Ts section shown in FIG. 2C. FIG. 3A shows a change in the Vh signal, FIG. 3B shows a change in the Vs signal, and FIG. 3C shows a wave form showing the change in the CLPP signal.

In FIG. 3B, Vss represents a potential when the drain current Imp2d of MP2 and the drain current Imp15d of MP15 are equal.

When the potential of Vs becomes Vss, Imp2d = Imp15d, so (Iin + Ioffset + Imn91d) = (Iin + Imn90d). In other words,

Ioffset = Imn90d-Imn91d (1)

Becomes

When the Ts period passes and the Th period passes, the first and second transmission gates I23 and I27 are turned off, and the third transmission gate I24 is turned on.

MN88 and MN92 are turned off, and MN89 and MN92 are turned on. Accordingly, the drain current Imp10d of the MP10 is equal to the drain current Imn90d of the MN90, and the drain current Imp14d of the MP14 is equal to the drain current Imn91d of the MN91.

This is again Imp2d = Imp14d = Imn91 and Imp15d = Imn90d by the current mirror relationship.

Since there is a relationship of Imn90d-Imn91d = Ioffset immediately before the Th period, the current Io output through the transmission gate I24 becomes the same as Ioffset in Equation (1).

In addition, if the leakage currents of the capacitors C8 and C28 connected to the gate sides of MN90 and MN91 are kept extremely small, the value of Ioffset remains stable until the next Ts section.

As described above, the offset detection apparatus according to the present invention has the advantage of sampling the synchronization leading level of the video signal to be compared and calculating the offset value based on the difference value, thereby outputting the correct offset value.

In addition, since the offset detection device according to the present invention provides a very stable offset value, it is possible to implement a correlation detection device, a dropout compensation device, etc., which requires little external adjustment, thereby increasing the productivity of these devices. Have

Claims (1)

An apparatus for detecting an offset, which is a difference of a reference level between video signals, comprising: first and second voltage current converting means for respectively introducing two video signals to be compared and generating a current signal corresponding to each video signal; A switching means for inputting an output of the voltage current converter and outputting the output only during a synchronization signal section of the video signal; First and second current mirrors for introducing a current signal output from the switching unit to a reference current side and generating a radiated current equivalent to the reference current; Feedback control of the reference current of the second current mirror such that the first and second radiated currents are equalized by the difference between the first and second radiated currents generated in the first and second current mirrors. Feedback control means; And obtaining a difference between the radiated currents generated in the first and second current mirrors during a period in which the current in the switching unit is not provided on the reference current side of the first and second current mirrors, and using the input terminals. And an output means for outputting a current value corresponding to an offset of an incoming video signal.