KR0123059B1 - Output circuit - Google Patents
Output circuitInfo
- Publication number
- KR0123059B1 KR0123059B1 KR94020530A KR19940020530A KR0123059B1 KR 0123059 B1 KR0123059 B1 KR 0123059B1 KR 94020530 A KR94020530 A KR 94020530A KR 19940020530 A KR19940020530 A KR 19940020530A KR 0123059 B1 KR0123059 B1 KR 0123059B1
- Authority
- KR
- South Korea
- Prior art keywords
- gate
- inverting
- source
- pmos transistor
- drain
- Prior art date
Links
Landscapes
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Abstract
An output terminal circuit is disclosed. The circuit comprises a supply power supply source; a ground power supply source; a first inverting gate for inverting an input signal; a first PMOS transistor having a source connected to the supply power supply source and a gate connected to a gate of the first inverting gate; a second inverting gate for inverting the output signal from the output signal from the first inverting gate; a first NMOS transistor having a source connected to the ground power supply source and a gate connected to the first inverting gate; a second NMOS transistor having a drain connected to the drain of the first PMOS transistor and a gate connected to the output of the second inverting gate; a second PMOS transistor having a source connected to the source of the second NMOS transistor, a gate connected to the gate of the second inverting gate and a drain connected to the drain of the first NMOS transistor; a third inverting gate for inverting the source signal from the second PMOS transistor; a third PMOS transistor having a source connected to the first PMOS transistor and a gate connected to the output of the third inverting gate; and a third NMOS transistor having a drain connected to the third PMOS transistor, a gate connected to the output of the third inverting gate and a source connected to the drain of the first NMOS transistor. Thereby, a stable output signal can be obtained.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR94020530A KR0123059B1 (en) | 1994-08-19 | 1994-08-19 | Output circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR94020530A KR0123059B1 (en) | 1994-08-19 | 1994-08-19 | Output circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR960009407A KR960009407A (en) | 1996-03-22 |
| KR0123059B1 true KR0123059B1 (en) | 1997-12-05 |
Family
ID=19390747
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR94020530A KR0123059B1 (en) | 1994-08-19 | 1994-08-19 | Output circuit |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR0123059B1 (en) |
-
1994
- 1994-08-19 KR KR94020530A patent/KR0123059B1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR960009407A (en) | 1996-03-22 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E902 | Notification of reason for refusal | ||
| E701 | Decision to grant or registration of patent right | ||
| GRNT | Written decision to grant | ||
| FPAY | Annual fee payment |
Payment date: 20050824 Year of fee payment: 9 |
|
| LAPS | Lapse due to unpaid annual fee |