KR0122112B1 - Nbi-cmos logic circuit - Google Patents

Abstract

A circuit that low level input signal is transferred to a node(2) and a 1st PMOS transistor(MP21) is powered but a 1st NMOS transistor(MN21) is turned off. As a high voltage is charged to an output node(4), a bi-polar transistor(Q21) for pulling up is powered, and a high level pull up voltage appears in an output node(8). But a 2nd NMOS transistor(MN22), a 4th NMOS transistor(MN24) and a pull-down bi-polar transistor(Q22) are all turned off. While, when a high level input signal is transferred to an input node(2) the 1st NMOS transistor(MN21) is powered.

Description

NBCMMOS logic circuit

1 is a circuit diagram showing an example of a bicymos logic circuit according to the prior art.

2 is a circuit diagram showing another example of a bicymos logic circuit according to the prior art.

Figure 3 is a circuit diagram showing an embodiment of the NBC CMOS logic circuit constituting the inverter logic according to the present invention.

4 is a waveform diagram showing the respective output characteristics of FIG. 1, FIG. 2, and FIG. 3 under a supply voltage of 5.0V.

5 is a waveform diagram showing the respective output characteristics of FIG. 1, FIG. 2 and FIG. 3 under a supply voltage of 3.3V.

6 is a circuit diagram showing an embodiment of an NBC logic logic circuit constituting Noah logic according to the present invention.

7 is a circuit diagram showing an embodiment of an NB CMOS logic circuit constituting the NAND logic according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to logic circuits, and is particularly stable under low power supply and high power supply voltages by forming a single circuit consisting of an NMOS transistor, a CMOS transistor, and a bipolar transistor. The present invention relates to a logic circuit for implementing a high speed operation characteristic.

For example, a semiconductor memory device such as a dynamic RAM or a static RAM is a logic such as an inverter logic or a NOR logic for an input buffer or an output buffer. It constitutes a circuit. Such a logic circuit should have an operation characteristic according to the device characteristic of the application apparatus. Thus, where high speed signal transmission is required, the logic circuit should perform a logic operation such as having a high speed output characteristic with respect to the input signal. On the other hand, according to the trend of low power supply voltage of integrated circuits, the logic circuits used here are required to exhibit excellent driving capability even under low power supply voltage.

In this regard, FIG. 1 shows an example of a conventional logic circuit.

Prior to the description, in the following description, the PMOS transistor is denoted by MPi (i = 1, 2, 3, ...), and the enmo transistor is denoted by '' MNi. Note that the bipolar transistor is represented by Qi.

The configuration of FIG. 1 shows a bicymoss circuit of air. The configuration of FIG. 1 is composed of the PMO transistors MP1, the NMO transistors MN1, MN2, MN3, and the bipolar transistors Q1, Q2. Such a configuration feature has advantages in that high driving capability and high speed can be realized by using bipolar transistors Q1 and Q2 at the output stage, as compared with a circuit which is usually composed only of the CMOS transistors. However, the bicymoss circuit shown in FIG. 1 has a problem that an output waveform that is ideal for a low power supply voltage level, i. For example, in the circuit of FIG. 1, when the output terminal Vout is at a low level, the output voltage value does not reach the ideal ground level GND. This is because the potential difference VBE between the base and the emitter of the bipolar transistor Q2 is generated. Accordingly, when the output terminal Vout becomes low level, the voltage value does not reach the ground level GND but instead of the potential difference VBE. The same voltage level is obtained.

Another example of a logic circuit as a prior art for solving this problem is disclosed in US Patent No. 4,882,534 (name of the invention: BIPOLAR COMPLEMENTARY METAL OXIDE SEMI-CONDUCTOR INVERTER), which is registered in the United States on November 21, 1989. 2 shows the technique disclosed in the patent. The circuit shown in FIG. 2 is composed of a bipolar transistor and an MOS transistor at an output stage, which may also be referred to as a bi-n-MOS circuit in the art. As shown in FIG. 2, by forming the PMO transistor transistor MP11 and the ENMO transistor transistor MN11, and the bipolar transistor Q11 and the pull-down terminal at the pull-up portion of the output terminal, The low level of the output stage can be reduced to the ideal voltage level, that is, ground level GND. However, this has a limitation on the driving capability of the output stage to the low level, and the width of the pull-down transistor MN12 of the output stage is shown in FIG. 2 in order to realize the driving capability and the switching speed similar to the bicymos circuit shown in FIG. In addition, it is difficult to realize a driving capability and a switching speed similar to the BCM mode circuit shown in FIG. 2 even if it is assumed that the width of the MN12 is increased.

Accordingly, an object of the present invention is to provide a logic circuit having stable operation characteristics and maintaining high speed output characteristics.

Another object of the present invention is to provide a logic circuit having a high speed driving capability at a low level.

It is still another object of the present invention to provide a logic circuit capable of realizing a low level of the output stage at the same level as the ground level while having the same driving capability and switching speed as the BCM module. In order to achieve the objects of the present invention, the present invention is directed to a logic circuit consisting of an NMOS transistor, a CMOS (CM0S) transistor, and a bipolar transistor. The NBMOS logic circuit according to the present invention includes a first power supply terminal, a second power supply terminal, an input node supplied with a predetermined input signal, and a voltage level of an input signal supplied to the input node. A pull-down control unit that operates; a pull-down control unit that operates in response to the voltage level of the input signal supplied to the input node; and a switching between the second power terminal and the output node; A pull-down bipolar transistor for operation, a pull-down bipolar transistor formed between the second power terminal and the output node and switching in response to an output signal of the pull-down control unit, and the output node and the second power terminal. An enbar formed between and provided with a pull-down enmo transistor for switching operation in response to the input signal applied to the input node. It is characterized by the logic circuit of NCI (NBiCMOS).

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Herein, the term NBSIMOS logic circuit is a novel term in the present invention while symbolizing the gist of the present invention, and has a configuration in which an NMOS transistor is added to a conventional BICMOS logic circuit. Defines that this is a logic circuit.

In the NVMOS logic circuit according to the present invention described below, an NVMOS logic circuit operating in inverter logic, NOA logic, and NAND logic, respectively, will be described. It can be easily predicted to those skilled in the art that other logic configurations can be implemented in addition to the above-mentioned logic with reference to the following description. 3 illustrates an inverter logic circuit that forms an inverter logic, that is, an inversion logic, as an embodiment of an ENVIMOS logic circuit according to the present invention. The configuration is as follows. A first PIO transistor MP21 having a channel formed between the input node 2 to which the input signal Vin is input, the first power supply terminal VDD to which the power supply is applied, and the connection node 4, and switching in response to the voltage level of the input node 2. And a first NMOS transistor MN21 having a channel formed between the second power supply terminal GND to which the ground power is applied and the connection node 4 and switching in response to the voltage level of the input node 2, and the first power supply terminal VDD and the output. A current path is formed between the node 8 and a channel is formed between the pull-up bipolar transistor Q21 for switching in response to the voltage level of the connection node 4, and the output node 8 and the connection node 6. And a channel is formed between the second NMOS transistor MN22 which switches in response to the voltage level of the input node 2, and the connection node 6 and the second power supply terminal GND. A pull-down switching current in response to the voltage level of the connection node 6 is provided with a current path formed between the third NMOS transistor MN23 that operates switching in response to the voltage level, and the output node 8 and the second power supply terminal GND. A fourth NMO transistor MN24 is formed between the bipolar transistor Q22 and the output node 8 and the second power supply terminal GND, and switches in response to the voltage level of the input node 2. In this configuration, the first PMO transistor MP21 and the first NMO transistor MN21 operate as a pull control unit. The second NMO transistor MN22 and the third NMO transistor MN23 operate as pull-down controllers. The characteristic feature of FIG. 3 is that the fourth NMOS transistor MN24, which acts as a pull-down means for the output voltage Vout, is provided at the output node 8. The fourth NMOS transistor MN24 is a bicymos circuit (i.e., a fourth signal). It is to be noted that the gist of the present invention is provided in the remaining portion except for the Enmo transistor MN24). Referring to the configuration of FIG. 3, the gate of the fourth ENMO transistor is directly connected to the input node 12, so that the switching operation of the fourth ENMO transistor MN24 is pulled down and pulled down with respect to the input signal Vin. It can be seen that it is faster than the switching operation of the bipolar transistors Q21 and Q22. Several new operational effects will be described later, such as the improvement of the operating characteristics such as the improvement of the driving capability of the logic circuit and the improvement of the switching speed by the provision of the fourth NMOO transistor MN24 at the output terminal of the logic circuit.

The operating characteristics of the NCMOS logic circuit of FIG. 3 will be described as follows. First, when the input signal Vin is applied to the input node 2 at a low level, the first PMO transistor MP21 is switched on, that is, turned on, and the first enmo transistor MN21 is switched off, that is, non-active. It is turned off. Thus, the output node 4 is charged with a high voltage, and in response thereto, the pull-up bipolar transistor Q21 is turned on, and the output node 8 shows the high level output voltage Vout. At this time, the second NMOS transistor MN22, the fourth NMOS transistor MN24, and the pull-down bipolar transistor Q22 are all non-conductive. On the other hand, when the input signal Vin is applied to the input node 2 as a high level, the first PMO transistor MP21 is not conducting and the first enmo transistor MN21 is conducting. Thus, the pull-up bipolar transistor Q21 is cut-off because the base is grounded. The second NMO transistor MN22 is turned on and thus the pull-down bipolar transistor Q22 is turned on. Then, the fourth ENMO transistor MN24 is turned on so that the output node 8 is discharged and the output voltage Vout is at the contact level. Here, when the output voltage Vout level becomes low level, the charge charged to the output terminal is first discharged by the fourth NMOS transistor MN24, and successively, a high-speed switching operation and high driving capability can be obtained by the pull-down bipolar transistor Q22. In addition, the EnMOS transistor MN24 allows the output stage voltage level to be achieved at an ideal low voltage level of 0V.

On the other hand, the NBCMOS logic circuit according to the present invention shown in FIG. 3 has an operational effect having an output stage performing complementary driving capability against temperature changes. In other words, it has a high driving capability by bipolar transistor Q21,22 in hot temperature environment, and it has a high driving ability by ANMO transistor MN24 in cold temperature environment. Complementary output levels can be obtained.

The waveforms shown in FIGS. 4 and 5 are waveform diagrams showing the low output characteristics of the first and second and the third and third embodiments of the present invention as described above. 4 and 5 are waveform diagrams confirmed by the present inventors simulation, and FIG. 4 is a waveform diagram showing the respective output characteristics of the first and second drawings and the third and third drawings under a supply voltage of 5.0 V, 5 is a waveform diagram showing the respective output characteristics of the first, second and third diagrams under a supply voltage of 3.3V. As shown in FIG. 4 and FIG. 5, it can be seen that the NBC logic circuit according to the present invention at the `` low '' output is outputted by sufficiently lowering the output level of the Vout to the ground level.

Referring to FIGS. 3, 4, and 5, the NBMOS circuit according to the present invention can obtain an ideal low level by using the fourth ENMO transistor MN24 at the output stage. That is, when the output node 8 is discharged, the fourth enmo transistor MN24 is discharged before the pull-down bipolar transistor Q22, and then the pull-down bipolar transistor Q22 is operated so that the start-point at which the pull-down bipolar transistor Q22 is discharged. You must do it quickly. Thus, the NBC circuit shown in FIG. 3 can obtain an output waveform faster than that of the prior art. In particular, high-speed switching, high driving capability, and ideal output low level can be obtained for both existing 5V products and low voltage products, and thus can be used as a combination of 5V products and low voltage products. It also has complementary drive capability against temperature changes.

FIG. 6 is a circuit diagram showing an embodiment of an NBC logic circuit that constitutes NOR logic according to the present invention. 6 is a circuit configured to implement a noah logic circuit based on the above-described technical concept of the present invention. As is well known in the art, most noah logic circuits have two inputs. The circuit is starting. The configuration of FIG. 6 is as follows. The source terminal is connected to the first input node 12 to which the first input signal V _in 1 is inputted, the second input signal V _in 2 to the input node second input node 20, and the first power terminal VDD to which the power supply is applied. A channel is formed between the first PMO transistor transistor MP31 connected to and connected in response to the voltage level of the first input node 12 and the connection node 14 of the drain terminal of the first PMO transistor transistor MP31. A channel is formed between the second PMOS transistor MP32 that switches in response to the voltage level of the second input node 20, the second power supply terminal GND to which the ground power is applied, and the connection node 14, and the voltage of the first input node 12. A second NMOS that switches in response to the voltage level of the second input node 20 and a channel is formed between the first NMOS transistor MN31 and the second power supply terminal GND and the connection node 14. Tran A pull-up bipolar transistor Q31 and an output node 18 which are provided with a current path between the master MN32 and the first power supply terminal VDD and the output node 18 and switch in response to the voltage level of the connection node 14. A channel is formed between the first node 16 and the connection node 16, and a channel is formed between the third NMOS transistor MN33 which switches in response to the voltage level of the first input node 12, and the output node 18 and the connection node 16. A channel is formed between the fourth NMOS transistor MN34 that operates switching in response to the voltage level of the second input node 20 and the connection node 16 and the second power supply terminal GND, and switches in response to the voltage level of the output node 18. A pull-down switching current in response to the voltage level of the connecting node 16 is formed between the MN35 of the fifth MOS transistor which is operated and the output node 18 and the second power supply terminal GND. A sixth MOS transistor MN36 having a channel formed between the bipolar transistor Q32 and the output node 18 and the second power supply terminal GND, and switching in response to the voltage level of the first input node 12, and the output node 18. A channel is formed between the second power supply terminal GND and the seventh enMOS transistor MN37 performs a switching operation in response to the voltage level of the second input node 20. In such a configuration, the first and second Fimotransistors MP31 and MP32 and the first and second Enmotransistors MN31 and MN32 operate as pull-over controls. The third, fifth and fifth NMO transistors MN33, MN34 and MN35 operate as pull-down control units. The configuration characteristic of FIG. 6 is that the output node 18 is provided with the 6th and 7th MOS transistors MN36 and MN37 which act as a pull-down means of the output voltage Vout in the structure of the bicymos noah logic circuit. Referring to the operation characteristics of Figure 6 as follows. When the low level signals are supplied to the first input node 12 and the second input node 20, the first and second PMO transistors MP31 and MP32 are turned on, respectively, and the first and second enmo transistors MN31 and MN32 are connected, respectively. Non-conductive, connection node 14 is charged to a high level. In response to the connection node 14 being charged to a high level, the pull-up bipolar transistor Q31 is turned on so that the output node 18 outputs a high level Vout. On the other hand, when a signal having a `` high '' level is supplied to the first input node 12 and / or the second input node 20, the first and / or second enmotransistors MN31 and / or MN32, and the third and / or The 4 NMO MOS transistor MN33 and / or MN34 are turned on, and the pull-down bipolar transistor Q32 is turned on. In this case, when any one of the input signals V _in 1 or V _in 2 is input as the high signal, the sixth and seventh enmo transistors MN36 and MN37 perform a high-speed switching operation by switching correspondingly. High drive capability is achieved by bipolar transistors Q31 or Q32 for pull-down or pull-down. In addition, the conduction of the sixth or seventh MOS transistor MN36 or MN37 causes the low level of the output voltage Vout to become an ideal voltage level, that is, a level equivalent to the ground level. It can be expected that the waveform at the low level output of FIG. 6 will be similar to those of FIGS. 4 and 5 described above. The NBMOS logic circuit of FIG. 6 discloses a two-input noah logic circuit, but for those skilled in the art, a three-input or four-input noah logic circuit based on the configuration of FIG. Could be done.

FIG. 7 is a circuit diagram showing an embodiment of an NBMOS logic circuit constituting NAND logic according to the present invention. 6 is a circuit configured to implement a noah logic circuit based on the technical idea of the present invention described above. As is well known in the art, most NAND logic circuits have two inputs. The circuit is starting. The configuration of FIG. 7 is as follows. Between the first input node 22 to which the first input signal V _in 1 is input, the second input node 30 to which the second input signal V _in 2 is input, and the first power supply terminal VDD to which the power supply is applied, and the connection node 24. A channel is formed and a channel is formed between the first PMOS transistor MP41 that switches in response to the voltage level of the first input node 22, the first power supply terminal VDD, and the connection node 24. A second PMO transistor transistor MP42 for switching in response to a voltage level, a first terminal of the first EnMOS transistor MN41 for switching in response to the voltage level of the first input node 22, and a drain terminal connected to the connection node 24; A second NMOS transistor MN42, a channel is formed between the source terminal of the first NMOS transistor MN41 and the second power supply terminal GND, and is switched in response to the voltage level of the second input node 30; A current path is formed between the output node 28 and the pull bipolar transistor Q41 for switching operation in response to the voltage level of the connection node 24, and the drain terminal is connected to the output node 28, and the voltage level of the first input node 22 is connected. A fourth channel is formed between the third NMOS transistor MN43 and the third ENMO transistor MN43 and the connection node 26 in response to the switching operation in response to the voltage level of the second input node 30. A sixth MOS transistor MN45 having a channel formed between the MOS transistor MN44 and the connection node 26 and the second power supply terminal GND, and switching in response to the voltage level of the output node 28, the output node 28, and the second power source. A current path is formed between the terminal GND and the pull-down bipolar transistor Q42 for switching in response to the voltage level of the connecting node 26 and the output node 28. A drain terminal is connected and a channel is formed between the sixth MOS transistor MN46 and the sixth MOS transistor MN46 and the second power supply terminal GND which are switched in response to the voltage level of the first input node 22. The seventh EnMOS transistor MN47 switches in response to the voltage level of the second input node 30. In such a configuration, the first and second PMO transistors MP41 and MP42, and the first and second enmo MOS transistors MN41 and MN42 operate as pull-down controllers. The third, fourth and fifth enmo transistors MN43, MN44 and MN45 operate as pull-down control units. The configuration characteristic of FIG. 7 is that the output node 28 is provided with the 6th and 7th MOS transistors MN46 and MN47 which act as a pull-down means of the output voltage Vout in the structure of the BiCMOS NAND logic circuit. The operational characteristics of FIG. 7 are as follows. When either the low level signal is supplied to the first input node 22 or the second input node 30, at least one of the first and second PIM transistors MP41 and MP42 is turned on. And any one of the first and second enmotransistors MN41 and MN42 is at least non-conductive. Thus, connection node 24 is charged to a high level. In response to the connection node 24 being charged to the high level, the pull-up bipolar transistor Q41 is turned on so that the output node 28 outputs a high level Vout. On the other hand, when a high level signal is supplied to both the first input node 12 and the second input node 20, the first second NMOS transistors MN41 and MN42, and the third and fourth NMOS transistors MN43 and MN44 are turned on. The pull-down bipolar transistor Q42 is turned on. At this time, the sixth and seventh & Mootransistors MN46 and MN47 are both conductive, but before the pull-down bipolar transistor Q42. Therefore, the NBCMOS logic circuit of FIG. 7 performs a high-speed switching operation, and high driving force can be realized by the bipolar transistor Q41 or Q42 for pull-down or pull-down. In addition, the conduction of the sixth and seventh MOS transistors MN46 and MN47 causes the low level of the output voltage Vout to become an ideal voltage level, that is, a level equivalent to the ground level. It can be expected that the waveform at the low '' level output of FIG. 7 will be similar to those of FIGS. 4 and 5 described above. Although the NBMOS logic circuit of FIG. 7 discloses a two-input NAND logic circuit, those skilled in the art realize various three-input or four-input NAND logic circuits based on the configuration of FIG. Could be done.

The above-described NBMOS logic circuits according to the present invention shown in FIGS. 3, 6, and 7 are the best embodiments implemented based on the above-described technical spirit of the present invention. However, some modifications may be made in consideration of the logic. However, the configuration of the ENMO transistor which is directly controlled by the input signal to the output node will be particularly carried out according to the configuration disclosed in the drawings.

As described above, the ENBSIMOS logic circuit according to the present invention includes an ENMOMOS transistor controlled directly to an input signal at an output terminal of the BSIMOS logic circuit, thereby providing high-speed switching, high driving capability, and an ideal output low. There is an advantage to get a level. It also has the effect of obtaining complementary output levels as the temperature changes.

Claims (4)

A logic circuit comprising: a first power supply terminal and a second power supply terminal. An input node supplied with a predetermined input signal, a pull-up control unit operating in response to the voltage level of the input signal supplied to the input node, a pull-down control unit operating in response to the voltage level of the input signal supplied to the input node; And a bipolar transistor for switching between the first power supply terminal and the output node and switching in response to the output signal of the pull control unit. And a pull-down bipolar transistor formed between the second power supply terminal and the output node and switching in response to an output signal of the pull-down control unit. An enciMOS logic circuit formed between the output node and the second power supply terminal and having a pull-down enmo transistor for switching in response to the input signal applied to the input node. In the logic circuit, a channel is formed between an input node to which a predetermined input signal is input, a first power terminal to which supply power is applied, and a predetermined first connection node, and a switching operation is performed in response to the voltage level of the input node. A first MOS transistor comprising a channel formed between the first PMOS transistor, a second power terminal receiving ground power, and the first connection node and switching in response to a voltage level of the input node; A current path is formed between the first power supply terminal and the output node, and a pull bipolar transistor for switching in response to the voltage level of the first connection node, and a channel between the output node and the predetermined second connection node. Is formed and a channel is formed between the second NMOS transistor and the switching operation in response to the voltage level of the input node, and between the second connection node and the second power supply terminal. And a current path is formed between the third NMOS transistor and the output node and the second power supply terminal. The switching operation is performed in response to the voltage level of the second connection node. And a fourth NMOS transistor, each having a channel formed between the output node and the second power supply terminal and switching in response to the voltage level of the input node, to perform inverter logic. Envy CMOS logic circuit. A logic circuit comprising: a first input node to which a first input signal is input, a second input node to which a second input signal is input, and a first input signal and a first input signal supplied to the first input node and the second input node. A pull-down control unit operating in response to the voltage level of the second input signal, a pull-down control unit operating in response to the voltage levels of the first input signal and the second input signal supplied to the first input node and the second input node, and supplying A current path is formed between the first power supply terminal to which the power is applied and the predetermined output node, and the pull-up bipolar transistor for switching operation in response to the output signal of the pull-out control unit, the second power supply terminal to which the grounding power is applied, and the output A current path is formed between the node and a pull-down bipolar transistor for switching in response to the output signal of the pull-down control unit, and a channel is formed between the output node and the second power supply terminal. And a channel is formed between the first NMOS transistor and a switching operation in response to the voltage level of the first input node, the output node and the second power supply terminal, and switching in response to the voltage level of the second input node. And an NMOS transistor, each of which operates a second NMOS transistor, and performs noah logic. A logic circuit comprising: a first input node to which a first input signal is input, a second input node to which a second input signal is input, a first input signal supplied to the first input node and a second input node, and a first input node. A pull-down control unit operating in response to the voltage level of the second input signal, a pull-down control unit operating in response to the voltage levels of the first input signal and the second input signal supplied to the first input node and the second input node, and supplying A current path is formed between the first power supply terminal to which the power is applied and the predetermined output node, and the pull-up bipolar transistor for switching operation in response to the output signal of the pull-out control unit, the second power supply terminal to which the grounding power is applied, and the output A pull-down bipolar transistor for switching current in response to an output signal of the pull-down control unit; a drain terminal is connected to the output node; A channel is formed between the first ENMO transistor and the source terminal of the first ENMO transistor and the second power supply terminal which are switched in response to the voltage level of the node, and in response to the voltage level of the second input node. An NBMOS logic circuit comprising a second NMOS transistor which operates switching to perform NAND logic.