JPWO2025004499A1 - - Google Patents

Info

Publication number
JPWO2025004499A1
JPWO2025004499A1 JP2025529462A JP2025529462A JPWO2025004499A1 JP WO2025004499 A1 JPWO2025004499 A1 JP WO2025004499A1 JP 2025529462 A JP2025529462 A JP 2025529462A JP 2025529462 A JP2025529462 A JP 2025529462A JP WO2025004499 A1 JPWO2025004499 A1 JP WO2025004499A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2025529462A
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2025004499A1 publication Critical patent/JPWO2025004499A1/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Laminated Bodies (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP2025529462A 2023-06-29 2024-04-12 Pending JPWO2025004499A1 (enrdf_load_stackoverflow)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2023107353 2023-06-29
PCT/JP2024/014762 WO2025004499A1 (ja) 2023-06-29 2024-04-12 配線板の製造方法

Publications (1)

Publication Number Publication Date
JPWO2025004499A1 true JPWO2025004499A1 (enrdf_load_stackoverflow) 2025-01-02

Family

ID=93938558

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2025529462A Pending JPWO2025004499A1 (enrdf_load_stackoverflow) 2023-06-29 2024-04-12

Country Status (3)

Country Link
JP (1) JPWO2025004499A1 (enrdf_load_stackoverflow)
TW (1) TW202504397A (enrdf_load_stackoverflow)
WO (1) WO2025004499A1 (enrdf_load_stackoverflow)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005008909A (ja) * 2003-06-16 2005-01-13 Canon Inc 構造体の製造方法
JP5000112B2 (ja) * 2005-09-09 2012-08-15 東京応化工業株式会社 ナノインプリントリソグラフィによるパターン形成方法
JP6337363B1 (ja) * 2016-10-05 2018-06-06 国立大学法人北陸先端科学技術大学院大学 複合部材及びその製造方法

Also Published As

Publication number Publication date
TW202504397A (zh) 2025-01-16
WO2025004499A1 (ja) 2025-01-02

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Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20250820

A871 Explanation of circumstances concerning accelerated examination

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Effective date: 20250820