JPWO2023013649A1 - - Google Patents

Info

Publication number
JPWO2023013649A1
JPWO2023013649A1 JP2023540369A JP2023540369A JPWO2023013649A1 JP WO2023013649 A1 JPWO2023013649 A1 JP WO2023013649A1 JP 2023540369 A JP2023540369 A JP 2023540369A JP 2023540369 A JP2023540369 A JP 2023540369A JP WO2023013649 A1 JPWO2023013649 A1 JP WO2023013649A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2023540369A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2023013649A1 publication Critical patent/JPWO2023013649A1/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2023540369A 2021-08-06 2022-08-02 Pending JPWO2023013649A1 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2021129531 2021-08-06
PCT/JP2022/029689 WO2023013649A1 (ja) 2021-08-06 2022-08-02 データキャッシュ装置およびプログラム

Publications (1)

Publication Number Publication Date
JPWO2023013649A1 true JPWO2023013649A1 (ja) 2023-02-09

Family

ID=85155661

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023540369A Pending JPWO2023013649A1 (ja) 2021-08-06 2022-08-02

Country Status (2)

Country Link
JP (1) JPWO2023013649A1 (ja)
WO (1) WO2023013649A1 (ja)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0844625A (ja) * 1994-07-28 1996-02-16 Nec Software Ltd バッファキャッシュ機構
JP4304974B2 (ja) * 2002-12-12 2009-07-29 富士ゼロックス株式会社 キャッシュメモリのデータ管理方法、及び情報処理装置
US20140095778A1 (en) * 2012-09-28 2014-04-03 Jaewoong Chung Methods, systems and apparatus to cache code in non-volatile memory
JP7144670B2 (ja) * 2017-12-22 2022-09-30 富士通株式会社 演算処理装置及び演算処理装置の制御方法
WO2019127487A1 (zh) * 2017-12-29 2019-07-04 华为技术有限公司 一种数据预取方法、装置和存储设备
JP6791540B2 (ja) * 2019-02-28 2020-11-25 Ｎｅｃプラットフォームズ株式会社 畳み込み演算処理装置および畳み込み演算処理方法

Also Published As

Publication number Publication date
WO2023013649A1 (ja) 2023-02-09

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