JPWO2022215173A5 - - Google Patents

Download PDF

Info

Publication number
JPWO2022215173A5
JPWO2022215173A5 JP2022527871A JP2022527871A JPWO2022215173A5 JP WO2022215173 A5 JPWO2022215173 A5 JP WO2022215173A5 JP 2022527871 A JP2022527871 A JP 2022527871A JP 2022527871 A JP2022527871 A JP 2022527871A JP WO2022215173 A5 JPWO2022215173 A5 JP WO2022215173A5
Authority
JP
Japan
Prior art keywords
fixed
bit width
point
verification
calculation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2022527871A
Other languages
Japanese (ja)
Other versions
JPWO2022215173A1 (en
JP7235171B2 (en
Filing date
Publication date
Application filed filed Critical
Priority claimed from PCT/JP2021/014649 external-priority patent/WO2022215173A1/en
Publication of JPWO2022215173A1 publication Critical patent/JPWO2022215173A1/ja
Publication of JPWO2022215173A5 publication Critical patent/JPWO2022215173A5/ja
Application granted granted Critical
Publication of JP7235171B2 publication Critical patent/JP7235171B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Description

本開示の固定小数点演算ビット幅の検証システムは、演算情報に基づいて数式(1)の検証保証精度内のパラメータδ及びεでベルヌーイ試行による区間推定を用いて検証データセットのデータ数を決定して目標値を含む生成仕様を定義する仕様定義部と、生成仕様に基づいて検証データセットを生成する生成部と、検証データセットを用いて固定小数点演算による演算結果を生成する固定小数点演算部と、演算結果及び生成仕様の数式(1)に基づいて固定小数点演算が仕様を満たしているか否かを検証する検証部とを備えている。 The fixed-point arithmetic bit width verification system of the present disclosure determines the number of data in the verification data set using interval estimation by Bernoulli trials with parameters δ and ε within the verification guaranteed accuracy of Equation (1) based on the arithmetic information. a specification definition part that defines a generation specification including a target value, a generation part that generates a verification data set based on the generation specification, and a fixed-point calculation part that generates a calculation result by fixed-point calculation using the verification data set , and a verification unit that verifies whether or not the fixed-point calculation satisfies the specification based on the calculation result and the expression (1) of the generation specification.

また、本開示の固定小数点演算ビット幅の決定システムは、演算の重要度が定義された演算情報に基づいて数式(1)の検証保証精度内のパラメータδ及びεでベルヌーイ試行による区間推定を用いて検証データセットのデータ数と重要度から固定小数点ビット幅と目標値とを含む生成仕様を定義する仕様定義部と、生成仕様に基づいて検証データセットを生成する生成部と、検証データセットを用いて固定小数点演算による演算結果を生成する固定小数点演算部と、演算結果及び生成仕様の数式(1)に基づいて固定小数点演算が仕様を満たしているか否かを検証し検証結果を生成する検証部と、検証結果に応じて生成仕様の更新判定を行う更新部とを備えている。
In addition, the fixed-point arithmetic bit width determination system of the present disclosure uses interval estimation by Bernoulli trials with parameters δ and ε within the verification guarantee accuracy of Equation (1) based on arithmetic information in which the importance of arithmetic is defined. A specification definition part that defines a generation specification including a fixed-point bit width and a target value from the number and importance of data in the verification data set, a generation part that generates a verification data set based on the generation specification, and a verification data set A fixed-point calculation unit that generates calculation results by fixed-point calculation using a fixed-point calculation unit, and a verification that verifies whether the fixed-point calculation satisfies the specifications based on the calculation results and formula (1) of the generation specifications, and generates verification results. and an update unit that determines whether to update the generation specification according to the verification result.

Claims (10)

演算情報に基づいて数式(1)の検証保証精度内のパラメータδ及びεでベルヌーイ試行による区間推定を用いて検証データセットのデータ数を決定して目標値を含む生成仕様を定義する仕様定義部と、
前記生成仕様に基づいて前記検証データセットを生成する生成部と、
前記検証データセットを用いて固定小数点演算による演算結果を生成する固定小数点演算部と、
前記演算結果及び前記生成仕様の数式(1)に基づいて前記固定小数点演算が仕様を満たしているか否かを検証する検証部と
を備えることを特徴とする固定小数点演算ビット幅の検証システム。
Figure 2022215173000001
Specification definition that determines the number of data n in the verification data set using interval estimation by Bernoulli trial with parameters δ and ε within the verification guaranteed accuracy of formula (1) based on the calculation information and defines the generation specification including the target value Department and
a generation unit that generates the verification data set based on the generation specification;
a fixed-point calculation unit that generates calculation results by fixed-point calculation using the verification data set;
A fixed-point operation bit width verification system, comprising: a verification unit that verifies whether the fixed-point operation satisfies a specification based on the operation result and the expression (1) of the generation specification.
Figure 2022215173000001
請求項1に記載の固定小数点演算ビット幅の検証システムであって、
前記検証部は、検証結果が前記目標値を達成している場合には前記仕様を満たしていると判定し、前記検証結果が前記目標値を達成していない場合には前記仕様を満たしていないと判定する
ことを特徴とする固定小数点演算ビット幅の検証システム。
The fixed-point arithmetic bit width verification system according to claim 1,
The verification unit determines that the specification is satisfied when the verification result achieves the target value, and determines that the specification is not satisfied when the verification result does not achieve the target value. A fixed-point arithmetic bit width verification system characterized by determining that:
請求項1又は請求項2に記載の固定小数点演算ビット幅の検証システムであって、
前記演算情報には、前記固定小数点演算部での演算内容と、前記固定小数点演算でのビット幅となる仮定ビット幅と、前記演算結果として求められる小数点の桁数である出力保証桁数とが含まれる
ことを特徴とする固定小数点演算ビット幅の検証システム。
The fixed-point arithmetic bit width verification system according to claim 1 or 2,
The calculation information includes the content of calculation in the fixed-point calculation unit, an assumed bit width that is the bit width in the fixed-point calculation, and the guaranteed number of output digits that is the number of decimal places obtained as the calculation result. A fixed-point arithmetic bit width verification system, comprising:
請求項1から3のいずれか1項に記載の固定小数点演算ビット幅の検証システムであって、
前記生成部は、前記演算情報からランダムに前記データ数の検証データを生成する
ことを特徴とする固定小数点演算ビット幅の検証システム。
A fixed-point arithmetic bit width verification system according to any one of claims 1 to 3,
The fixed-point arithmetic bit width verification system, wherein the generator randomly generates the verification data of the number n of data from the arithmetic information.
請求項1から3のいずれか1項に記載の固定小数点演算ビット幅の検証システムであって、
前記固定小数点演算部は、前記検証データセットの数だけ前記固定小数点演算を行う
ことを特徴とする固定小数点演算ビット幅の検証システム。
A fixed-point arithmetic bit width verification system according to any one of claims 1 to 3,
The fixed-point operation bit width verification system, wherein the fixed-point operation unit performs the fixed-point operation by the number of the verification data sets.
演算の重要度が定義された演算情報に基づいて数式(2)の検証保証精度内のパラメータδ及びεでベルヌーイ試行による区間推定を用いて検証データセットのデータ数と前記重要度から固定小数点ビット幅と目標値とを含む生成仕様を定義する仕様定義部と、
前記生成仕様に基づいて前記検証データセットを生成する生成部と、
前記検証データセットを用いて固定小数点演算による演算結果を生成する固定小数点演算部と、
前記演算結果及び前記生成仕様の数式(2)に基づいて前記固定小数点演算が仕様を満たしているか否かを検証し検証結果を生成する検証部と、
前記検証結果に応じて前記生成仕様の更新判定を行う更新部と
を備えることを特徴とする固定小数点演算ビット幅の決定システム。
Figure 2022215173000002
Based on the calculation information in which the importance of the calculation is defined , the parameters δ and ε within the verification guarantee accuracy of Equation (2) are used to estimate the interval by Bernoulli trial, and the number of data n of the verification data set and the above-mentioned importance are fixed point a specification definition section that defines a production specification including bit widths and target values;
a generation unit that generates the verification data set based on the generation specification;
a fixed-point calculation unit that generates calculation results by fixed-point calculation using the verification data set;
a verification unit that verifies whether the fixed-point calculation satisfies the specification based on the calculation result and the expression (2) of the generation specification, and generates a verification result;
and an updating unit that determines whether to update the generation specification according to the verification result.
Figure 2022215173000002
請求項6に記載の固定小数点演算ビット幅の決定システムであって、
前記演算情報には、前記固定小数点演算部での演算内容と、前記固定小数点演算でのビット幅となる仮定ビット幅と、前記演算結果として求められる小数点の桁数である出力保証桁数と、再検証時のビット幅探索方法が記載されたビット幅探索モードとが含まれる
ことを特徴とする固定小数点演算ビット幅の決定システム。
7. The fixed-point arithmetic bit width determination system according to claim 6,
The calculation information includes the content of calculation in the fixed-point calculation unit, an assumed bit width that is the bit width in the fixed-point calculation, and the number of guaranteed output digits that is the number of decimal places obtained as the calculation result , and a bit width search mode in which a bit width search method during reverification is described.
請求項6又は請求項7に記載の固定小数点演算ビット幅の決定システムであって、
第1の前記ビット幅探索モードは、前記重要度と前記検証結果とで仮定ビット幅を決めて、前記検証結果に応じて前記仕様より許容条件を緩和し、
前記仕様定義部は、前記データ数と前記目標値とを決定する
ことを特徴とする固定小数点演算ビット幅の決定システム。
The system for determining the fixed-point arithmetic bit width according to claim 6 or 7,
In the first bit width search mode, an assumed bit width is determined by the importance and the verification result, and the allowable condition is relaxed from the specification according to the verification result,
The fixed-point arithmetic bit width determination system, wherein the specification definition unit determines the number of data n and the target value.
請求項6又は請求項7に記載の固定小数点演算ビット幅の決定システムであって、
第2の前記ビット幅探索モードは、前記データ数と前期目標値と固定小数点ビット幅とを変更せずに固定小数点の整数部と小数部との境界を変更する
ことを特徴とする固定小数点演算ビット幅の決定システム。
The system for determining the fixed-point arithmetic bit width according to claim 6 or 7,
In the second bit width search mode, the boundary between the integer part and the decimal part of the fixed point is changed without changing the number of data n , the target value and the fixed point bit width. Arithmetic bit width determination system.
請求項6又は請求項7に記載の固定小数点演算ビット幅の決定システムであって、
第3の前記ビット幅探索モードは、前記データ数と前期目標値とを変更せずに固定小数点ビット幅を変更する
ことを特徴とする固定小数点演算ビット幅の決定システム。
The system for determining the fixed-point arithmetic bit width according to claim 6 or 7,
3. A system for determining a fixed-point operation bit width, wherein the bit width search mode changes the fixed-point bit width without changing the number of data n and the target value.
JP2022527871A 2021-04-06 2021-04-06 Verification system and determination system for fixed-point arithmetic bit width Active JP7235171B2 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2021/014649 WO2022215173A1 (en) 2021-04-06 2021-04-06 Verification system and determination system for fixed-point arithmetic bit width

Publications (3)

Publication Number Publication Date
JPWO2022215173A1 JPWO2022215173A1 (en) 2022-10-13
JPWO2022215173A5 true JPWO2022215173A5 (en) 2023-03-07
JP7235171B2 JP7235171B2 (en) 2023-03-08

Family

ID=83545329

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2022527871A Active JP7235171B2 (en) 2021-04-06 2021-04-06 Verification system and determination system for fixed-point arithmetic bit width

Country Status (2)

Country Link
JP (1) JP7235171B2 (en)
WO (1) WO2022215173A1 (en)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4861087B2 (en) * 2006-07-31 2012-01-25 富士通株式会社 Arithmetic program conversion device, arithmetic program conversion program, arithmetic program conversion method
JP2009099084A (en) 2007-10-19 2009-05-07 Kyocera Corp Conversion device
US9916130B2 (en) * 2014-11-03 2018-03-13 Arm Limited Apparatus and method for vector processing
JP6540770B2 (en) 2017-10-17 2019-07-10 富士通株式会社 Arithmetic processing circuit, arithmetic processing unit including arithmetic processing circuit, information processing apparatus including arithmetic processing unit, and method
JP2020098469A (en) 2018-12-18 2020-06-25 富士通株式会社 Arithmetic processing device and method for controlling arithmetic processing device
JP7188237B2 (en) 2019-03-29 2022-12-13 富士通株式会社 Information processing device, information processing method, information processing program

Similar Documents

Publication Publication Date Title
NO20065938L (en) Digital signing of data by a computable asymmetric hash function
JP2019079535A (en) Method and apparatus for processing parameters
JP2008547086A5 (en)
Datta et al. A solution of the affine quadratic inverse eigenvalue problem
Novara et al. Building blocks for designing arbitrarily smooth subdivision schemes with conic precision
JP2003033828A (en) Method and program for forming die model
US11972238B2 (en) Propagating reduced-precision on computation graphs
WO2010027046A1 (en) Information processing device, information processing method, information storage medium, and program
Sulaiman et al. The convergence properties of some descent conjugate gradient algorithms for optimization models
JPWO2022215173A5 (en)
JP6366033B2 (en) Optimization method of IF statement in program
WO2022044465A1 (en) Information processing method and information processing system
WO2021186685A1 (en) Simulation execution system, simulation execution method, and simulation execution program
Ostrin et al. Elementary arithmetic
Xu et al. On the Convergence of (Stochastic) Gradient Descent with Extrapolation for Non-Convex Minimization.
Juan et al. Fast median search in metric spaces
CN114818203A (en) Reducer design method based on SWA algorithm
Shoid et al. A modification of classical conjugate gradient method using strong Wolfe line search
CN113031510B (en) B-spline curve calculation acceleration method for complex multi-axis system
Maitin-Shepard Optimal software-implemented Itoh–Tsujii inversion for F _ 2^ m F 2 m
CN110795227B (en) Data processing method of block chain and related equipment
Abd Rasid et al. Formulation of a new implicit method for group implicit BBDF in solving related stiff ordinary differential equations
Gheorghiu et al. Accurate spectral solutions to a phase-field transition system
JP2000315244A (en) Method for statistically estimating device performance
Boklan A note on identities for elementary symmetric and power sum polynomials