JPWO2022130951A5

JPWO2022130951A5 -

Info

Publication number: JPWO2022130951A5
Application number: JP2022569832A
Authority: JP
Filing date: 2021-11-29
Publication date: 2023-02-20
Anticipated expiration: 2041-11-29

Description

図４において、ゲート端子接続部９６とＸ軸方向の距離が最も近い絶縁基板２１－１と接続する個別ゲート調整配線９２－１は、最も近い絶縁基板２１－１と個別ゲート調整配線９２－１との接続位置（図４の位置０）と、最も遠い絶縁基板２１－６と個別ゲート調整配線９２－６との接続位置（図４の位置５）と、のおおよそ中央（図４の位置２と３の間）で共通ゲート調整配線９４に接続されている。つまり、最も近い絶縁基板２１－１と接続する配線は、共通ゲート調整配線９４において最も近い絶縁基板２１－１の位置（位置０）から、最も近い絶縁基板２１－１と最も遠い絶縁基板２１－６との距離のおおよそ半分（位置２と３の間）まで行って、最も近い絶縁基板２１－１の位置（位置０）まで折り返す配線となっている。また、ゲート端子接続部９６とＸ軸方向の距離が最も遠い絶縁基板２１－６と接続する個別ゲート調整配線９２－６は、接続位置（図４の位置５）の上方で共通ゲート調整配線９４に接続されている。そして、絶縁基板２１－１と絶縁基板２１－６との間の絶縁基板２１－２～５に接続される個別ゲート調整配線９２－２～５は、個別ゲート調整配線９２－１と個別ゲート調整配線９２－６との間で均等な間隔で共通ゲート調整配線９４と接続されている。つまり、絶縁基板２１－１と絶縁基板２１－６との間の絶縁基板２１－２～５に接続される配線は、共通ゲート調整配線９４において最も近い絶縁基板２１－１の位置（位置０）から、最も近い絶縁基板２１－１と最も遠い絶縁基板２１－６との距離のおおよそ半分（位置２と３の間）より長く、最も遠い絶縁基板２１－６との位置（位置５）より短い位置まで行って、それぞれの絶縁基板２１－２～５の位置（位置０）まで折り返す配線となっている。 In FIG. 4, the individual gate adjustment wiring 92-1 connecting the gate terminal connection portion 96 to the insulating substrate 21-1 closest in the X-axis direction is connected to the closest insulating substrate 21-1 and the individual gate adjustment wiring 92-1. (position 0 in FIG. 4) and the connection position (position 5 in FIG. 4) between the furthest insulating substrate 21-6 and the individual gate adjustment wiring 92-6 (position 2 in FIG. 4). and 3) are connected to the common gate adjustment wiring 94 . In other words, the wiring connected to the nearest insulating substrate 21-1 is the closest insulating substrate 21-1 and the farthest insulating substrate 21- from the position (position 0) of the nearest insulating substrate 21-1 in the common gate adjustment wiring 94. 6 (between positions 2 and 3), and is turned back to the position (position 0) of the nearest insulating substrate 21-1. In addition, the individual gate adjustment wiring 92-6 connecting the gate terminal connection portion 96 to the insulating substrate 21-6, which is the farthest in the X-axis direction, is located above the connection position (position 5 in FIG. 4). It is connected to the. The individual gate adjustment wirings 92-2 to 92-5 connected to the insulating substrates 21-2 to 21-5 between the insulating substrates 21-1 and 21-6 are connected to the individual gate adjustment wirings 92-1 and 92-1. It is connected to the common gate adjustment wiring 94 at equal intervals with the wiring 92-6. That is, the wiring connected to the insulating substrates 21-2 to 21-5 between the insulating substrate 21-1 and the insulating substrate 21-6 is located at the position (position 0) of the insulating substrate 21-1 closest to the common gate adjustment wiring 94. , longer than approximately half the distance between the nearest insulating substrate 21-1 and the farthest insulating substrate 21-6 (between positions 2 and 3) and shorter than the position with the farthest insulating substrate 21-6 (position 5) The wiring goes to the position and turns back to the position (position 0) of each of the insulating substrates 21-2 to 21-5.

本例において、第１のセンスエミッタ端子６０の距離が近いほど、第１の半導体チップ４０に接続する個別センス調整配線９３の配線は長い。図５において、センスエミッタ端子接続部９７とＸ軸方向の距離が近い絶縁基板２１に配置された半導体チップ４０と接続する個別センス調整配線９３ほど、配線は長い。本例では、個別センス調整配線９３－６、個別センス調整配線９３－５、個別センス調整配線９３－４、個別センス調整配線９３－３、個別センス調整配線９３－２、個別センス調整配線９３－１の順に配線が長くなっている。配線が長いほど配線のインダクタンスを大きくすることができる。このような構成にすることで、各半導体チップ４０と第１のセンスエミッタ端子６０間の配線長の相違を調整することができる。 In this example, the closer the first sense emitter terminal 60 is, the longer the individual sense adjustment wiring 93 connected to the first semiconductor chip 40 is. In FIG. 5 , the individual sense adjustment wiring 93 connected to the semiconductor chip 40 arranged on the insulating substrate 21 closer to the sense emitter terminal connection portion 97 in the X-axis direction has a longer wiring. In this example, individual sense adjustment wiring 93-6, individual sense adjustment wiring 93-5, individual sense adjustment wiring 93-4, individual sense adjustment wiring 93-3, individual sense adjustment wiring 93-2, and individual sense adjustment wiring 93- The wiring becomes longer in the order of 1. The longer the wiring, the greater the inductance of the wiring. With such a configuration, the difference in wiring length between each semiconductor chip 40 and the first sense emitter terminal 60 can be adjusted.

図５において、センスエミッタ端子接続部９７とＸ軸方向の距離が最も近い絶縁基板２１－１と接続する個別センス調整配線９３－１は、最も近い絶縁基板２１－１と個別センス調整配線９３－１との接続位置（図５の位置０）と、最も遠い絶縁基板２１－６と個別センス調整配線９３－６との接続位置（図５の位置５）と、のおおよそ中央（図５の位置２と３の間）で共通センス調整配線９５に接続されている。つまり、最も近い絶縁基板２１－１と接続する配線は、共通センス調整配線９５において最も近い絶縁基板２１－１の位置（位置０）から、最も近い絶縁基板２１－１と最も遠い絶縁基板２１－６との距離のおおよそ半分（位置２と３の間）まで行って、最も近い絶縁基板２１－１の位置（位置０）まで折り返す配線となっている。また、センスエミッタ端子接続部９７とＸ軸方向の距離が最も遠い絶縁基板２１－６と接続する個別センス調整配線９３－６は、接続位置（図５の位置５）の上方で共通センス調整配線９５に接続されている。そして、絶縁基板２１－１と絶縁基板２１－６との間の絶縁基板２１－２～５に接続される個別センス調整配線９３－２～５は、個別センス調整配線９３－１と個別センス調整配線９３－６との間で均等な間隔で共通センス調整配線９５と接続されている。つまり、絶縁基板２１－１と絶縁基板２１－６との間の絶縁基板２１－２～５に接続される配線は、共通センス調整配線９５において最も近い絶縁基板２１－１の位置（位置０）から、最も近い絶縁基板２１－１と最も遠い絶縁基板２１－６との距離のおおよそ半分（位置２と３の間）より長く、最も遠い絶縁基板２１－６との位置（位置５）より短い位置まで行って、それぞれの絶縁基板２１－２～５の位置（位置０）まで折り返す配線となっている。 In FIG. 5, the individual sense adjustment wiring 93-1 connecting the sense emitter terminal connection portion 97 to the insulating substrate 21-1 closest in the X-axis direction is connected to the closest insulating substrate 21-1 and the individual sense adjustment wiring 93-1. 1 (position 0 in FIG. 5) and the connection position (position 5 in FIG. 5) between the furthest insulating substrate 21-6 and the individual sense adjustment wiring 93-6 (position 5 in FIG. 5) (position 2 and 3) are connected to the common sense adjustment wiring 95. In other words, the wiring connected to the nearest insulating substrate 21-1 is the closest insulating substrate 21-1 and the farthest insulating substrate 21- from the position (position 0) of the nearest insulating substrate 21-1 in the common sense adjustment wiring 95. 6 (between positions 2 and 3), and is turned back to the position (position 0) of the nearest insulating substrate 21-1. The individual sense adjustment wiring 93-6 connecting the sense emitter terminal connection portion 97 to the insulating substrate 21-6, which is the farthest in the X-axis direction, is located above the connection position (position 5 in FIG. 5). 95. The individual sense adjustment wirings 93-2 to 93-5 connected to the insulating substrates 21-2 to 21-5 between the insulating substrates 21-1 and 21-6 are connected to the individual sense adjustment wirings 93-1 and 93-1. It is connected to the common sense adjustment wiring 95 at equal intervals with the wiring 93-6. That is, the wires connected to the insulating substrates 21-2 to 21-5 between the insulating substrate 21-1 and the insulating substrate 21-6 are located at the position (position 0) of the insulating substrate 21-1 closest to the common sense adjustment wiring 95. , longer than approximately half the distance between the nearest insulating substrate 21-1 and the farthest insulating substrate 21-6 (between positions 2 and 3) and shorter than the position with the farthest insulating substrate 21-6 (position 5) It is a wiring that goes to the position and turns back to the position (position 0) of each of the insulating substrates 21-2 to 21-5.

第２の調整センス配線８９は、複数の第２の半導体チップ４０と第２のセンスエミッタ端子６１間の配線長の相違を調整する。本例において、第２の調整センス配線８９は、絶縁基板２１－１、絶縁基板２１－２、絶縁基板２１－３、絶縁基板２１－４、絶縁基板２１－５および絶縁基板２１－６上に配置された各半導体チップ４０－４と第２のセンスエミッタ端子６１間の配線長の相違を調整する。第２の調整センス配線８９を備えることにより、より正確にセンス電流を測定することができる。 The second adjustment sense wiring 89 adjusts the wiring length difference between the plurality of second semiconductor chips 40 and the second sense emitter terminals 61 . In this example, the second adjustment sense wiring 89 is formed on the insulating substrate 21-1, the insulating substrate 21-2, the insulating substrate 21-3, the insulating substrate 21-4, the insulating substrate 21-5 and the insulating substrate 21-6. The difference in wiring length between each arranged semiconductor chip 40-4 and the second sense emitter terminal 61 is adjusted. By providing the second adjustment sense wiring 89 , the sense current can be measured more accurately.

上面視における第２の調整ゲート配線８７の延伸方向は、上面視における第２の調整センス配線８９の延伸方向と平行であってよい。本例において、第２の調整ゲート配線８７の延伸方向と第２の調整センス配線８９の延伸方向は、いずれもＸ軸方向である。第２の調整ゲート配線８７の延伸方向と第２の調整センス配線８９の延伸方向を平行にすることにより、半導体モジュール１００を小型化することができる。また、上面視における第２の調整ゲート配線８７の延伸方向は、上面視における第１の調整ゲート配線８６の延伸方向と平行であってよい。上面視における第２の調整センス配線８９の延伸方向は、上面視における第１の調整センス配線８８の延伸方向と平行であってよい。 The extension direction of the second adjustment gate wiring 87 in top view may be parallel to the extension direction of the second adjustment sense wiring 89 in top view. In this example, both the extension direction of the second adjustment gate wiring 87 and the extension direction of the second adjustment sense wiring 89 are the X-axis direction. By making the extension direction of the second adjustment gate wiring 87 and the extension direction of the second adjustment sense wiring 89 parallel, the semiconductor module 100 can be miniaturized. Further, the extension direction of the second adjustment gate wiring 87 in top view may be parallel to the extension direction of the first adjustment gate wiring 86 in top view. The extension direction of the second adjustment sense wiring 89 when viewed from the top may be parallel to the extension direction of the first adjustment sense wiring 88 when viewed from the top.

図１０は、本発明の他の実施形態に係る半導体モジュール３００の一例を示す図である。半導体モジュール３００は、第１の調整ゲート配線８６および第１の調整センス配線８８の構成が半導体モジュール１００とは異なる。半導体モジュール３００のそれ以外の構成は、半導体モジュール１００と同一であってよい。 FIG. 10 is a diagram showing an example of a semiconductor module 300 according to another embodiment of the invention. Semiconductor module 300 differs from semiconductor module 100 in the configuration of first adjustment gate wiring 86 and first adjustment sense wiring 88 . Other configurations of the semiconductor module 300 may be the same as those of the semiconductor module 100 .

図２１においてＩＧＢＴである半導体チップ４０がオンするに伴い、印加電圧が跳ね上がる。この際、絶縁基板２１－１上の半導体チップに流れる電流の跳ね上がり量は、絶縁基板２１－６上の半導体チップに流れる電流の跳ね上がり量に比べて小さい。一方で、図２２において、絶縁基板２１－１上の半導体チップに流れる電流の跳ね上がり量と絶縁基板２１－６上の半導体チップに流れる電流の跳ね上がり量は、ほぼ同一である。これは、第１の調整ゲート配線８６および第１の調整センス配線８８により、各絶縁基板２１上の各半導体チップ４０と接続する配線の配線長が揃うことでインダクタンスが揃えられ、各絶縁基板２１上の各半導体チップ４０のゲート－エミッタ間電圧の過渡変化が、ほぼ同じになるためである。したがって、図２２は、図２１と比べ、絶縁基板２１－６上の半導体チップ４０を流れる電流と絶縁基板２１－１上の半導体チップ４０を流れる電流の過渡的な通電電流をそろえることができる。したがって、半導体チップ４０の破壊、スイッチング損失の増加を防ぐことができる。 In FIG. 21, as the semiconductor chip 40, which is an IGBT, is turned on, the applied voltage jumps up. At this time, the jumping amount of the current flowing through the semiconductor chip on the insulating substrate 21-1 is smaller than the jumping amount of the current flowing through the semiconductor chip on the insulating substrate 21-6. On the other hand, in FIG. 22, the jumping amount of the current flowing through the semiconductor chip on the insulating substrate 21-1 and the jumping amount of the current flowing through the semiconductor chip on the insulating substrate 21-6 are substantially the same. This is because the first adjustment gate wiring 86 and the first adjustment sense wiring 88 align the wiring lengths of the wirings connected to the respective semiconductor chips 40 on the respective insulating substrates 21 , thereby aligning the inductances of the respective insulating substrates 21 . This is because the transient change of the voltage between the gate and the emitter of each semiconductor chip 40 is almost the same. Therefore, in FIG. 22, compared with FIG. 21, the transient conduction currents of the current flowing through the semiconductor chip 40 on the insulating substrate 21-6 and the current flowing through the semiconductor chip 40 on the insulating substrate 21-1 can be aligned. Therefore, destruction of the semiconductor chip 40 and an increase in switching loss can be prevented.

Claims

a plurality of first semiconductor chips;
a resin case surrounding an accommodation space that accommodates the plurality of first semiconductor chips;
a first gate terminal connected to the gate pads of the plurality of first semiconductor chips;
a plurality of first main gate wirings provided in the housing space and respectively connected to the gate pads of the plurality of first semiconductor chips;
arranged between at least one of the plurality of first main gate wirings and the first gate terminal to adjust a difference in wiring length between the plurality of first semiconductor chips and the first gate terminal; and a semiconductor module comprising:

2. The semiconductor module according to claim 1, wherein at least part of said first adjustment gate wiring is embedded in said resin case.

further comprising one or more insulating substrates, each on which one or more of the plurality of first semiconductor chips are disposed;
3. The semiconductor module according to claim 1, wherein said plurality of first main gate wirings are wiring patterns provided on said insulating substrate.

4. The semiconductor module according to claim 3, wherein said first adjustment gate wiring has a flat plate shape and has a main surface perpendicular to the main surface of said insulating substrate and parallel to the direction in which said plurality of insulating substrates are arranged.

a first sense emitter terminal connected to the main electrodes of the plurality of first semiconductor chips;
a plurality of first main sense wirings provided in the housing space and respectively connected to the main electrodes of the plurality of first semiconductor chips;
a difference in wire length between the plurality of first semiconductor chips and the first sense emitter terminal, and arranged between at least one of the plurality of first main sense wires and the first sense emitter terminal; The semiconductor module according to any one of claims 1 to 4, further comprising: a first adjustment sense wiring that adjusts

6. The semiconductor module according to claim 5, wherein at least part of said first adjustment sense wiring is embedded in said resin case.

further comprising one or more insulating substrates, each on which one or more of the plurality of first semiconductor chips are disposed;
7. The semiconductor module according to claim 5, wherein the plurality of first main sense wirings are wiring patterns provided on the insulating substrate.

a plurality of second semiconductor chips;
a second gate terminal connected to the gate pads of the plurality of second semiconductor chips;
a plurality of second main gate wirings provided in the housing space and respectively connected to the gate pads of the plurality of second semiconductor chips;
arranged between at least one of the plurality of second main gate wirings and the second gate terminal to adjust a difference in wiring length between the plurality of second semiconductor chips and the second gate terminal; 8. The semiconductor module according to any one of claims 1 to 7, further comprising: a second adjustment gate wiring that

Further comprising a base plate having a first edge and a second edge facing the first edge,
The first adjustment gate wiring is provided on the first edge side of the base plate,
9. The semiconductor module according to claim 8, wherein said second adjustment gate wiring is provided on said second edge side of said base plate.

a second sense emitter terminal connected to the main electrodes of the plurality of second semiconductor chips;
a plurality of second main sense wirings provided in the housing space and respectively connected to the main electrodes of the plurality of second semiconductor chips;
a difference in wire length between the plurality of second semiconductor chips and the second sense emitter terminal, the wire being arranged between at least one of the plurality of second main sense wires and the second sense emitter terminal; 10. The semiconductor module according to claim 8 or 9, further comprising a second adjustment sense wiring that adjusts the .

comprising a plurality of the first adjustment gate wirings;
The semiconductor module according to any one of claims 1 to 10, wherein the plurality of first adjustment gate wirings are connected to the plurality of first semiconductor chips, respectively.

The first adjustment gate wiring is
a plurality of individual gate adjustment wirings provided for each of the plurality of first semiconductor chips;
The semiconductor module according to any one of claims 1 to 10, further comprising a common gate adjustment wiring connected to the plurality of individual gate adjustment wirings.

13. The semiconductor module according to claim 12, wherein said common gate adjustment wiring is arranged above said plurality of individual gate adjustment wirings in a height direction perpendicular to the upper surfaces of said plurality of first semiconductor chips.

The closer the distance between one of the plurality of first semiconductor chips and the first gate terminal, the closer the connection is to the first semiconductor chip among the plurality of individual gate adjustment wirings. 13. The semiconductor module according to claim 12 , wherein the individual gate adjustment wiring is long.

8. The semiconductor module according to claim 5, wherein the extending direction of the first adjustment gate wiring when viewed from the top is parallel to the extending direction of the first adjustment sense wiring when viewed from the top.