JPWO2022004274A1 - - Google Patents

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Publication number
JPWO2022004274A1
JPWO2022004274A1 JP2022533770A JP2022533770A JPWO2022004274A1 JP WO2022004274 A1 JPWO2022004274 A1 JP WO2022004274A1 JP 2022533770 A JP2022533770 A JP 2022533770A JP 2022533770 A JP2022533770 A JP 2022533770A JP WO2022004274 A1 JPWO2022004274 A1 JP WO2022004274A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2022533770A
Other versions
JP7539173B2 (ja
JPWO2022004274A5 (ja
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Publication of JPWO2022004274A5 publication Critical patent/JPWO2022004274A5/ja
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Publication of JP7539173B2 publication Critical patent/JP7539173B2/ja
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Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06NCOMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/40Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/57Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computing Systems (AREA)
  • Computational Mathematics (AREA)
  • Artificial Intelligence (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Data Mining & Analysis (AREA)
  • Evolutionary Computation (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
JP2022533770A 2020-06-30 2021-06-04 コンピュータシステム及び制御装置 Active JP7539173B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2020112273 2020-06-30
JP2020112273 2020-06-30
PCT/JP2021/021357 WO2022004274A1 (ja) 2020-06-30 2021-06-04 コンピュータシステム及び制御装置

Publications (3)

Publication Number Publication Date
JPWO2022004274A1 true JPWO2022004274A1 (ja) 2022-01-06
JPWO2022004274A5 JPWO2022004274A5 (ja) 2023-02-16
JP7539173B2 JP7539173B2 (ja) 2024-08-23

Family

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Also Published As

Publication number Publication date
US20230229953A1 (en) 2023-07-20
WO2022004274A1 (ja) 2022-01-06

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