JPWO2021247633A5

JPWO2021247633A5 -

Info

Publication number: JPWO2021247633A5
Application number: JP2022574358A
Authority: JP
Publication date: 2024-06-04

Claims

1. An integrated circuit device, comprising:
a chip having metal interconnect levels including a final copper interconnect level;
a chip-to-package interconnect overlying and connected to said final copper interconnect level,
a via connected to a first element of the final copper interconnect level, the via having a barrier material on the sidewalls and bottom and tungsten filling the via ;
a copper conductive structure coupled through the via to a first element of the final copper interconnect level ;
the chip-to-package interconnect having
13. An integrated circuit device comprising :

2. The integrated circuit device of claim 1,
the copper conductive structure is an under-bump metallurgy;
The integrated circuit device, wherein the chip-to-package interconnect further comprises a solder bump on the under-bump metal structure.

2. The integrated circuit device of claim 1,
An integrated circuit device , wherein the copper conductive structures are copper pillars.

2. The integrated circuit device of claim 1,
An integrated circuit device, wherein said copper conductive structure is a copper structure with an overlying Ni/Pd layer.

2. The integrated circuit device of claim 1,
The copper conductive structure is
a copper structure extending over a first element of the final copper interconnect level and a portion of the chip adjacent to the first element;
a copper post overlying and connected to the copper structure, the copper post being offset from the first element;
13. An integrated circuit device comprising:

2. The integrated circuit device of claim 1,
the copper conductive structure includes a copper structure extending over a first element of the final copper interconnect level and a portion of the chip adjacent to the first element;
the chip-to-package interconnect comprises:
an under-bump metal structure offset from the first element;
a solder bump on the under-bump metal structure;
The integrated circuit device further comprises :

2. The integrated circuit device of claim 1,
The via extends through a passivation layer.

8. An integrated circuit device according to claim 7,
The integrated circuit device, wherein the passivation layer comprises an oxide layer and a silicon nitride layer over the oxide layer .

8. An integrated circuit device according to claim 7,
The integrated circuit device, wherein the passivation layer comprises an oxide layer and a silicon oxynitride layer over the oxide layer.

2. The integrated circuit device of claim 1,
The integrated circuit device, wherein the vias include one or more vias connected between a first element of the final copper interconnect level and the copper conductive structure.

2. The integrated circuit device of claim 1,
The integrated circuit device, wherein the chip-to-package interconnect further comprises a barrier layer disposed between the via and the copper conductive structure, the barrier layer comprising TiW or Ti.

2. The integrated circuit device of claim 1,
an integrated circuit device, wherein the chip-to-package interconnect further comprises a protective dielectric layer disposed between the via and the copper conductive structure, the protective dielectric layer having an opening through which the via is connected to the copper conductive structure.

13. An integrated circuit device as claimed in claim 12, comprising:
An integrated circuit device, wherein the protective dielectric layer comprises polyimide, polybenzoxazole (PBO), or bisbenzocyclobutene (BCB).

2. The integrated circuit device of claim 1,
the copper conductive structure includes a redistribution layer;
the integrated circuit device comprising:
a polyimide layer on the redistribution layer;
an under-bump metal structure connected to the redistribution layer through an opening in the polyimide layer;
a solder bump on the under-bump metal structure;
The integrated circuit device further comprises:

2. The integrated circuit device of claim 1,
1. An integrated circuit device comprising: an integrated circuit device including a first interconnect layer and a second interconnect layer, the first interconnect layer being electrically connected to a first element of the integrated circuit device; a first interconnect layer being electrically connected to a second element of the integrated circuit device;

16. An integrated circuit device as claimed in claim 15,
The integrated circuit device, wherein the probe contact area further comprises a probe metal stack on the tungsten.

17. An integrated circuit device according to claim 16, comprising:
An integrated circuit device, wherein the probe metal stack comprises a layer of Ni and a layer of Pd.

2. The integrated circuit device of claim 1,
an integrated circuit device, the via having a first width at the bottom and a second width at a top of the via, the first width and the second width being the same;

1. A method of manufacturing an integrated circuit device, comprising:
forming a final metal interconnect level of an integrated circuit chip using a damascene copper process;
depositing a passivation layer over said final metal interconnect level;
Forming a chip-to-package interconnect, comprising :
forming a first opening and a second opening wider than the first opening in the passivation layer;
depositing a barrier layer over the passivation layer and into the first and second openings;
depositing tungsten over the barrier layer, the tungsten filling the first opening and lining but not filling the second opening;
removing the tungsten and the barrier layer from over the passivation layer by chemical mechanical polishing , leaving the tungsten and the barrier layer in the first and second openings;
depositing a probe metal stack over the passivation layer and the first opening, the probe metal stack extending into the second opening but not into the first opening;
removing the probe metal stack from over the passivation layer and the first opening , leaving the probe metal stack in the second opening; and
forming copper conductive structures over the first openings, each copper conductive structure being electrically coupled to the final metal interconnect level by the tungsten in the first opening;
forming the chip-to-package interconnect by
A method comprising :

20. The method of claim 19 ,
The method, wherein the probe metal stack comprises a layer of Ni and a layer of Pd.

21. The method of claim 20 ,
The method, wherein the barrier layer comprises Ti, TiN, Ta, TaN, or a combination thereof .

20. The method of claim 19 ,
The method further includes probing the integrated circuit chip by contacting the probe metal stack in at least some of the second openings.

20. The method of claim 19 ,
The method, wherein the copper conductive structure is a copper bump.

20. The method of claim 19 ,
The method, wherein the copper conductive structure is an under-bump metal structure underlying a solder bump.

20. The method of claim 19 ,
The method, wherein the copper conductive structures are copper pillars.

20. The method of claim 19 ,
the conductive layer is a redistribution layer ,
The method,
forming a polyimide layer on the redistribution layer;
forming an under-bump metal structure through the polyimide layer to the redistribution layer;
forming a solder bump on the under-bump metal structure;
The method further comprises:

20. The method of claim 19 ,
singulating the integrated circuit chips from other integrated circuit chips on a wafer;
attaching the integrated circuit chip to a leadframe via the chip-to-package interconnect;
applying a molding compound to the integrated circuit chip attached to the lead frame;
The method further comprises:

1. An integrated circuit device, comprising:
a chip having metal interconnect levels including a final copper interconnect level;
a chip-to-package interconnect overlapping and connected to said final copper interconnect level,
a via connected to a first element of the final copper interconnect level, the via having a barrier material on the sidewalls and bottom and tungsten filling the via , the barrier material comprising: Ti, TiN, Ta, TaN, or combinations thereof;
a copper conductive structure coupled through the via to a first element of the final copper interconnect level ;
the chip-to-package interconnect having
13. An integrated circuit device comprising :

30. The integrated circuit device of claim 28,
an integrated circuit device, the via having a first width at the bottom and a second width at a top of the via, the first width and the second width being the same;