JPWO2021201940A5

JPWO2021201940A5 -

Info

Publication number: JPWO2021201940A5
Application number: JP2022559551A
Authority: JP
Publication date: 2023-11-28

Claims

A method of processing a substrate, the method comprising:
forming a high aspect ratio (HAR) channel through the substrate , the HAR channel having an aspect ratio greater than 50:1 ;
depositing a layer of polycrystalline silicon on the sidewalls of the HAR channel;
delivering an oxidizing agent into the HAR channel to oxidize an uncovered surface of the layer of polycrystalline silicon, the oxidizing agent causing the formation of an oxidized layer; a layer has a uniform thickness on the uncovered surface of the layer of polycrystalline silicon ;
delivering a removal agent into the HAR channel to remove the oxidized layer from the HAR channel ;
repeating the steps of oxidizing the uncovered surface and removing the oxidized layer until a predetermined amount of the layer of polycrystalline silicon is removed.

2. The method of claim 1, wherein oxidizing the uncovered surface is carried out using a solution containing the oxidizing agent.

2. The method of claim 1, wherein the removal agent comprises a solution containing HF.

2. The method of claim 1, wherein forming the HAR channel includes forming the channel through a stack of alternating layers of dielectric material as part of a NAND memory manufacturing process.

2. The method of claim 1, wherein the oxidizing agent comprises an aqueous hydrogen peroxide solution.

2. The method of claim 1, wherein the oxidizing agent comprises a solution containing ozone.

2. The method of claim 1, wherein the polycrystalline silicon is doped with phosphorus.

2. The method of claim 1, further comprising rinsing the oxidized layer with deionized water before removing the oxidized layer.

2. The method of claim 1, further comprising rinsing the oxidized layer with deionized water after removing the oxidized layer.

2. The method of claim 1, wherein after removing the predetermined amount of the layer of polycrystalline silicon, the layer of polycrystalline silicon on the sidewall has a final thickness of between 5 nm and 50 nm.

A method of forming a 3D NAND device, the method comprising:
forming a high aspect ratio (HAR) channel in a 3D NAND dielectric stack;
depositing a layer of polysilicon having a first thickness on the sidewalls of the HAR channel;
performing a periodic etching process , each period comprising:
forming an oxide layer on the layer of polysilicon by wetting an exposed surface of the layer of polysilicon in the HAR channel with a first solution containing an oxidizing agent;
removing the oxidized layer in the HAR channel from the layer of polysilicon using a second solution containing an oxide etchant, the periodic etching process having a second thickness on the sidewall of the HAR channel, the second thickness being a predetermined thickness less than the first thickness.

rinsing the oxidized silicon-based material with deionized water before etching the oxidized silicon-based material ; and deionizing the silicon-based material after etching away the oxidized silicon-based material. 12. The method of claim 11 , further comprising rinsing with water.

12. The method of claim 11 , wherein the first solution is an aqueous hydrogen peroxide solution having a concentration of about 1-30% by weight.

12. The method of claim 11 , wherein the second solution is an aqueous hydrogen fluoride solution having a concentration of about 0.1-10% by weight.

A method of forming a 3D NAND device, the method comprising:
forming a high aspect ratio (HAR) channel in a 3D NAND dielectric stack;
depositing a layer of polysilicon having a first thickness on the sidewalls of the HAR channel;
performing a periodic etching process, each period comprising:
forming an oxide layer on the layer of polysilicon by wetting an exposed surface of the layer of polysilicon in the HAR channel with a first solution containing an oxidizing agent;
rinsing the oxide layer with deionized water;
removing the oxidized layer in the HAR channel from the layer of polysilicon using a second solution containing an oxide etchant;
rinsing the polysilicon with deionized water, the periodic etching process being stopped after the layer of polysilicon has a second thickness on the sidewalls of the HAR channel; The second thickness is thinner than the first thickness by a predetermined thickness.

16. The method of claim 15, wherein the first solution is an aqueous hydrogen peroxide solution having a concentration of about 1-30% by weight.

16. The method of claim 15, wherein the second solution is an aqueous hydrogen fluoride solution having a concentration of about 0.1-10% by weight.

The exposed surface of the layer of polysilicon is wetted with the first solution by immersion in a first bath, and the oxide layer is oxide etched by immersion in a second bath. 16. The method of claim 15, wherein the method is wetted with a solution.

4. The exposed surface of the layer of polysilicon is wetted with the first solution by immersion in a bath, and the oxide layer is wetted with an oxide etch solution in a wet spray etch tool. 15. The method described in 15.

5. The exposed surface of the layer of polysilicon is wetted with the first solution in a wet spray etch tool, and the oxide layer is wetted with the second solution in the wet spray etch tool. 15. The method described in 15.