JPWO2021171480A1 - - Google Patents

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Publication number
JPWO2021171480A1
JPWO2021171480A1 JP2020566305A JP2020566305A JPWO2021171480A1 JP WO2021171480 A1 JPWO2021171480 A1 JP WO2021171480A1 JP 2020566305 A JP2020566305 A JP 2020566305A JP 2020566305 A JP2020566305 A JP 2020566305A JP WO2021171480 A1 JPWO2021171480 A1 JP WO2021171480A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2020566305A
Other versions
JP6841393B1 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
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Application filed filed Critical
Application granted granted Critical
Publication of JP6841393B1 publication Critical patent/JP6841393B1/ja
Publication of JPWO2021171480A1 publication Critical patent/JPWO2021171480A1/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06G—ANALOGUE COMPUTERS
    • G06G7/00—Devices in which the computing operation is performed by varying electric or magnetic quantities
    • G06G7/48—Analogue computers for specific processes, systems or devices, e.g. simulators
    • G06G7/60—Analogue computers for specific processes, systems or devices, e.g. simulators for living beings, e.g. their nervous systems ; for problems in the medical field
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/049—Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G06N3/065—Analogue means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Health & Medical Sciences (AREA)
  • Biomedical Technology (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Biophysics (AREA)
  • General Health & Medical Sciences (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Neurology (AREA)
  • Software Systems (AREA)
  • Artificial Intelligence (AREA)
  • Evolutionary Computation (AREA)
  • Data Mining & Analysis (AREA)
  • Computational Linguistics (AREA)
  • Molecular Biology (AREA)
  • Power Engineering (AREA)
  • Neurosurgery (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Physiology (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Hall/Mr Elements (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Semiconductor Memories (AREA)
JP2020566305A 2020-02-27 2020-02-27 演算回路及びニューロモーフィックデバイス Active JP6841393B1 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2020/008025 WO2021171480A1 (ja) 2020-02-27 2020-02-27 演算回路及びニューロモーフィックデバイス

Publications (2)

Publication Number Publication Date
JP6841393B1 JP6841393B1 (ja) 2021-03-10
JPWO2021171480A1 true JPWO2021171480A1 (ja) 2021-09-02

Family

ID=74845336

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020566305A Active JP6841393B1 (ja) 2020-02-27 2020-02-27 演算回路及びニューロモーフィックデバイス

Country Status (4)

Country Link
US (1) US20220261559A1 (ja)
JP (1) JP6841393B1 (ja)
CN (1) CN114127970A (ja)
WO (1) WO2021171480A1 (ja)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20240074323A1 (en) * 2021-01-12 2024-02-29 Tdk Corporation Magnetic array, magnetic array control method, and magnetic array control program
KR20230012882A (ko) * 2021-07-16 2023-01-26 삼성전자주식회사 자기 저항체를 포함하는 프로세싱 장치
KR20230053976A (ko) * 2021-10-15 2023-04-24 삼성전자주식회사 뉴로모픽 메모리 회로 및 그 동작 방법

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5160304B2 (ja) * 2008-05-22 2013-03-13 シャープ株式会社 抵抗変化型可変抵抗素子を備えた積演算装置、及び積和演算装置、これらの装置を各ニューロン素子に備えるニューラルネットワーク、並びに積演算方法
CN103460220A (zh) * 2012-01-23 2013-12-18 松下电器产业株式会社 神经网络电路的学习方法
JP6501146B2 (ja) * 2014-03-18 2019-04-17 パナソニックＩｐマネジメント株式会社 ニューラルネットワーク回路およびその学習方法
US9842646B2 (en) * 2015-04-28 2017-12-12 Hewlett Packard Enterprise Development Lp Memristor apparatus with variable transmission delay
WO2019189895A1 (ja) * 2018-03-30 2019-10-03 国立大学法人東北大学 ニューラルネットワーク回路装置

Also Published As

Publication number Publication date
CN114127970A (zh) 2022-03-01
US20220261559A1 (en) 2022-08-18
JP6841393B1 (ja) 2021-03-10
WO2021171480A1 (ja) 2021-09-02

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