JPWO2021156954A1 - - Google Patents

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Publication number
JPWO2021156954A1
JPWO2021156954A1 JP2021575142A JP2021575142A JPWO2021156954A1 JP WO2021156954 A1 JPWO2021156954 A1 JP WO2021156954A1 JP 2021575142 A JP2021575142 A JP 2021575142A JP 2021575142 A JP2021575142 A JP 2021575142A JP WO2021156954 A1 JPWO2021156954 A1 JP WO2021156954A1
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JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Application number
JP2021575142A
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Japanese (ja)
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JP7363930B2 (ja
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Publication of JPWO2021156954A1 publication Critical patent/JPWO2021156954A1/ja
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Publication of JP7363930B2 publication Critical patent/JP7363930B2/ja
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Anticipated expiration legal-status Critical

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Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00General purpose image data processing
    • G06T1/20Processor architectures; Processor configuration, e.g. pipelining
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00Arrangements for software engineering
    • G06F8/40Transformation of program code
    • G06F8/41Compilation
    • G06F8/45Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
    • G06F8/451Code distribution
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00Arrangements for software engineering
    • G06F8/40Transformation of program code
    • G06F8/41Compilation
    • G06F8/44Encoding
    • G06F8/443Optimisation
    • G06F8/4441Reducing the execution time required by the program code
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00Arrangements for software engineering
    • G06F8/40Transformation of program code
    • G06F8/41Compilation
    • G06F8/45Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
    • G06F8/451Code distribution
    • G06F8/452Loops

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Devices For Executing Special Programs (AREA)
JP2021575142A 2020-02-04 2020-02-04 オフロードサーバ、オフロード制御方法およびオフロードプログラム Active JP7363930B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2020/004201 WO2021156954A1 (ja) 2020-02-04 2020-02-04 オフロードサーバ、オフロード制御方法およびオフロードプログラム

Publications (2)

Publication Number Publication Date
JPWO2021156954A1 true JPWO2021156954A1 (https=) 2021-08-12
JP7363930B2 JP7363930B2 (ja) 2023-10-18

Family

ID=77200425

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2021575142A Active JP7363930B2 (ja) 2020-02-04 2020-02-04 オフロードサーバ、オフロード制御方法およびオフロードプログラム

Country Status (3)

Country Link
US (1) US12033235B2 (https=)
JP (1) JP7363930B2 (https=)
WO (1) WO2021156954A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021156954A1 (ja) * 2020-02-04 2021-08-12 日本電信電話株式会社 オフロードサーバ、オフロード制御方法およびオフロードプログラム

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019216127A1 (ja) * 2018-05-09 2019-11-14 日本電信電話株式会社 オフロードサーバおよびオフロードプログラム

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10372497B1 (en) 2017-09-05 2019-08-06 Parallels International Gmbh Offloading GPU computations for computers and virtual machines
US11593138B2 (en) 2019-05-20 2023-02-28 Microsoft Technology Licensing, Llc Server offload card with SoC and FPGA
US11204711B2 (en) 2019-10-31 2021-12-21 EMC IP Holding Company LLC Method and system for optimizing a host computing device power down through offload capabilities
WO2021156954A1 (ja) * 2020-02-04 2021-08-12 日本電信電話株式会社 オフロードサーバ、オフロード制御方法およびオフロードプログラム

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019216127A1 (ja) * 2018-05-09 2019-11-14 日本電信電話株式会社 オフロードサーバおよびオフロードプログラム

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
#PRAGMA ACC KERNELS LOOP VERSUS #PRAGMA ACC PARALLEL LOOP - USER FORUMS [ONLINE], JPN6020010139, 28 May 2015 (2015-05-28), ISSN: 0005092844 *
山登庸次 ほか: "IoTアプリケーションのGPUオフロード時の並列処理部抽出とデータ転送回数低減手法", 電子情報通信学会技術研究報告, vol. Vol.118,KBSE2018-37,SC2018-32(2018-11), JPN6020010138, 10 November 2018 (2018-11-10), JP, pages 53 - 58, ISSN: 0005092843 *

Also Published As

Publication number Publication date
JP7363930B2 (ja) 2023-10-18
WO2021156954A1 (ja) 2021-08-12
US12033235B2 (en) 2024-07-09
US20230066594A1 (en) 2023-03-02

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