JPWO2021061547A5 - - Google Patents
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Claims (19)
第１のセグメントと第２のセグメントとを含む抵抗器ネットワークを含むデジタルアナログコンバータ（ＤＡＣ）を含み、
前記第１のセグメントが、第１の抵抗器のセットと、第１の供給電圧ノードと前記第１の抵抗器のセットとの間に結合される第１のスイッチとを含み、
前記第２のセグメントが、第２の抵抗器のセットと、前記第１の供給電圧ノードと前記第２の抵抗器のセットとの間に結合される第２のスイッチとを含み、
前記第１のセグメントが、第２の抵抗器と、前記第２の抵抗器と直列に結合される第３のスイッチとを更に含み、前記第３のスイッチと前記第２の抵抗器との直列の組み合わせが、前記第１の抵抗器のセットの少なくとも１つの抵抗器と並列に結合され、
前記第２のセグメントが、第３の抵抗器と、前記第３の抵抗器と直列に結合される第４のスイッチとを含み、前記第４のスイッチと前記第３の抵抗器との直列の組み合わせが前記第２の抵抗器のセットの少なくとも１つの抵抗器と並列に結合される、ＡＤＣ。 An analog digital converter (ADC),
a digital to analog converter (DAC) including a resistor network including a first segment and a second segment ;
the first segment includes a first set of resistors and a first switch coupled between a first supply voltage node and the first set of resistors;
the second segment includes a second set of resistors and a second switch coupled between the first supply voltage node and the second set of resistors;
The first segment further includes a second resistor and a third switch coupled in series with the second resistor, the third switch being coupled in series with the second resistor. are coupled in parallel with at least one resistor of the first set of resistors;
the second segment includes a third resistor and a fourth switch coupled in series with the third resistor; An ADC in which the combination is coupled in parallel with at least one resistor of said second set of resistors.
前記第３のスイッチと前記第２の抵抗器との直列の組み合わせが、前記第１の抵抗器のセットの少なくとも２つの抵抗器の直列の組み合わせと並列に結合され、
前記第４のスイッチと前記第３の抵抗器との直列の組み合わせが、前記第２の抵抗器のセットの少なくとも２つの抵抗器の直列の組み合わせと並列に結合される、ＡＤＣ。 The ADC according to claim 1,
a series combination of the third switch and the second resistor is coupled in parallel with a series combination of at least two resistors of the first resistor set;
The ADC, wherein the series combination of the fourth switch and the third resistor is coupled in parallel with the series combination of at least two resistors of the second set of resistors.
前記第１のセグメントがバイナリセグメントを更に含み、前記第２のセグメントがサーモメトリックセグメントを更に含み、
前記抵抗器ネットワークが前記バイナリセグメントと前記サーモメトリックセグメントとの間に結合される第３の抵抗器のセットを更に含み、前記第３の抵抗器のセットが、直列に結合される第４及び第５の抵抗器と、直列に結合される第６及び第７の抵抗器とを含み、前記第４及び第５の抵抗器の直列の組み合わせが、前記第６及び第７の抵抗器の直列の組み合わせと並列に結合される、ＡＤＣ。 The ADC according to claim 1,
the first segment further includes a binary segment, and the second segment further includes a thermometric segment;
The resistor network further includes a third set of resistors coupled between the binary segment and the thermometric segment, wherein the third set of resistors includes a fourth resistor coupled in series and a third set of resistors coupled in series. a fifth resistor and sixth and seventh resistors coupled in series, the series combination of the fourth and fifth resistors being the series combination of the sixth and seventh resistors. ADC coupled in parallel with a combination of.
前記第２の抵抗器のセットが、
前記第２のスイッチと前記ＤＡＣの出力ノードとの間に直列に結合される第４、第５、第６及び第７の抵抗器と、
直列に結合される第８、第９、第１０及び第１１の抵抗器と、
を含み、
前記第４～第７の抵抗器が、前記第８～第１１の抵抗器の直列組み合わせと並列に結合される、ＡＤＣ。 The ADC according to claim 1,
The second set of resistors is
fourth, fifth, sixth, and seventh resistors coupled in series between the second switch and an output node of the DAC;
eighth, ninth, tenth and eleventh resistors coupled in series;
including;
The ADC, wherein the fourth to seventh resistors are coupled in parallel with the series combination of the eighth to eleventh resistors.
前記第１の抵抗器のセットが、前記第２の抵抗器のセットよりも少ない抵抗器を含む、ＡＤＣ。 The ADC according to claim 4,
An ADC, wherein the first set of resistors includes fewer resistors than the second set of resistors.
前記第１の抵抗器のセットの各抵抗器が、
ｎウェル上に形成されるポリシリコン抵抗器と、
ｐドープ基板と、
前記ｎウェルより高いドーピング濃度を有するｎドープ領域と、
前記ｎドープ領域への電気的接続であって、前記第１のスイッチに結合される、前記電気的接続と、
を含む、ＡＤＣ。 The ADC according to claim 1,
Each resistor of the first set of resistors is
a polysilicon resistor formed on the n-well;
a p-doped substrate;
an n-doped region having a higher doping concentration than the n-well;
an electrical connection to the n-doped region , the electrical connection being coupled to the first switch ;
Including ADC.
前記ＤＡＣの出力ノードに結合されるコンパレータと、
前記コンパレータの出力と前記ＤＡＣの入力とに結合されるレジスタと、
を更に含む、ＡＤＣ。 The ADC according to claim 1,
a comparator coupled to an output node of the DAC;
a register coupled to the output of the comparator and the input of the DAC ;
further comprising an ADC.
複数のバイナリセグメントと複数のサーモメトリックセグメントとを含む抵抗器ネットワークを含むデジタルアナログコンバータ（ＤＡＣ）であって、前記複数のサーモメトリックセグメントが第１及び第２のサーモメトリックセグメントを含む、前記ＤＡＣを含み、
前記第１のサーモメトリックセグメントが、第１のスイッチと、前記第１のスイッチと前記ＤＡＣの出力ノードとの間に直列に結合される一対のユニット抵抗器とを含み、前記第２のサーモメトリックセグメントが、第２のスイッチと、前記第２のスイッチと前記出力ノードとの間に結合される８ユニット抵抗器とを含む、ＡＤＣ。 An analog digital converter (ADC),
A digital-to-analog converter (DAC) comprising a resistor network including a plurality of binary segments and a plurality of thermometric segments , the plurality of thermometric segments including first and second thermometric segments. including,
the first thermometric segment including a first switch and a pair of unit resistors coupled in series between the first switch and an output node of the DAC ; An ADC wherein a segment includes a second switch and an eight unit resistor coupled between the second switch and the output node.
前記８ユニット抵抗器の４つが直列に結合され、前記８ユニット抵抗器の別の４つも直列に結合され、前記２つの直列のユニット抵抗器が互いに並列に結合される、ＡＤＣ。 The ADC according to claim 8 ,
An ADC, wherein four of the eight unit resistors are coupled in series, another four of the eight unit resistors are also coupled in series, and the two series unit resistors are coupled in parallel with each other.
前記第１のサーモメトリックセグメントが、第２の抵抗器と、前記第２の抵抗器と直列に結合される第３のスイッチとを含み、前記第３のスイッチと第２の抵抗器との直列組み合わせが、前記第１のサーモメトリックセグメントの対応するユニット抵抗器の対のうちの少なくとも１つと並列に結合される、ＡＤＣ。 The ADC according to claim 8,
the first thermometric segment includes a second resistor and a third switch coupled in series with the second resistor, the third switch in series with the second resistor; An ADC, wherein the combination is coupled in parallel with at least one of the pair of corresponding unit resistors of the first thermometric segment.
前記第２のサーモメトリックセグメントが、第３の抵抗器と、前記第３の抵抗器と直列に結合される第４のスイッチとを含み、前記第４のスイッチと前記第３の抵抗器との直列組み合わせが、前記第２のサーモメトリックセグメントの前記ユニット抵抗器のうちの少なくとも１つと並列に結合される、ＡＤＣ。 The ADC according to claim 8 ,
the second thermometric segment includes a third resistor and a fourth switch coupled in series with the third resistor; An ADC, wherein a series combination is coupled in parallel with at least one of the unit resistors of the second thermometric segment.
前記複数のバイナリセグメントの第１のバイナリセグメントが、複数のユニット抵抗器と、第２の抵抗器と、前記第２の抵抗器と直列に結合される第３のスイッチとを含み、前記第３のスイッチと前記第２の抵抗器との前記直列組み合わせが、前記第１のバイナリセグメントの前記複数のユニット抵抗器の少なくとも１つのユニット抵抗器と並列に結合される、ＡＤＣ。 The ADC according to claim 8,
a first binary segment of the plurality of binary segments includes a plurality of unit resistors, a second resistor, and a third switch coupled in series with the second resistor; and the second resistor is coupled in parallel with at least one unit resistor of the plurality of unit resistors of the first binary segment.
前記第１及び第２のサーモメトリックセグメントのそれぞれのユニット抵抗器が、
ｎウェル上に形成されるポリシリコン抵抗器と、
ｐドープ基板と、
前記ｎウェルよりも高いドーピング濃度を有するｎドープ領域と、
前記ｎドープ領域への電気的接続であって、それぞれの第１又は第２のスイッチに結合される、前記電気的接続と、
を含む、ＡＤＣ。 The ADC according to claim 8,
a unit resistor for each of the first and second thermometric segments;
a polysilicon resistor formed on the n-well;
a p-doped substrate;
an n-doped region having a higher doping concentration than the n-well;
an electrical connection to the n-doped region , the electrical connection being coupled to a respective first or second switch ;
Including ADC.
複数のセグメントを含む抵抗器ネットワークを含むデジタルアナログコンバータ（ＤＡＣ）を含み、
前記複数のセグメントが、第１の抵抗器のセットと、供給電圧ノードと前記第１の抵抗器のセットとの間に結合される第１のスイッチと、第２の抵抗器と、前記第２の抵抗器と直列に結合される第２のスイッチとを含む第１のセグメントを含み、前記第２のスイッチと前記第２の抵抗器との直列の組み合わせが、前記第１の抵抗器のセットの少なくとも１つの抵抗器と並列に結合され、
前記第１のスイッチが、動作時間期間の間に前記第１の抵抗器のセットに供給電圧を印加するように制御されるときに、前記第２のスイッチが、前記動作時間期間未満の間にオンにされ、次いで、前記動作時間期間の残りの間オフにされるように構成される、ＡＤＣ。 An analog digital converter (ADC),
a digital-to-analog converter (DAC) including a resistor network including a plurality of segments ;
The plurality of segments includes a first set of resistors , a first switch coupled between a supply voltage node and the first set of resistors, a second resistor, and the second set of resistors . and a second switch coupled in series with a resistor, the series combination of the second switch and the second resistor being coupled in series with the first set of resistors. coupled in parallel with at least one resistor of
When the first switch is controlled to apply a supply voltage to the first set of resistors during an operating time period, the second switch is controlled to apply a supply voltage to the first set of resistors during less than the operating time period. An ADC configured to be turned on and then turned off for the remainder of the operating time period.
前記第２のスイッチと前記第２の抵抗器との直列の組み合わせが、前記第１の抵抗器のセットの少なくとも２つの抵抗器の直列の組み合わせと並列に結合される、ＡＤＣ。 15. The ADC according to claim 14 ,
The ADC, wherein the series combination of the second switch and the second resistor is coupled in parallel with the series combination of at least two resistors of the first set of resistors.
前記複数のセグメントが、第２の抵抗器のセットと、前記供給電圧ノードと前記第２の抵抗器のセットとの間に結合される第３のスイッチとを含む第２のセグメントを含み、
前記抵抗器ネットワークが、前記第１及第２のセグメントの間に結合される第３の抵抗器のセットを更に含み、前記第３の抵抗器のセットが、直列に結合される第４及び第５の抵抗器と、直列に結合される第６及び第７の抵抗器とを含み、前記第４及び第５の抵抗器の直列の組み合わせが、前記第６及び第７の抵抗器の直列の組み合わせと並列に結合される、ＡＤＣ。 15. The ADC according to claim 14 ,
the plurality of segments includes a second segment including a second set of resistors and a third switch coupled between the supply voltage node and the second set of resistors;
The resistor network further includes a third set of resistors coupled between the first and second segments, wherein the third set of resistors includes fourth and fourth resistors coupled in series. 5 resistors and sixth and seventh resistors coupled in series, wherein the series combination of the fourth and fifth resistors is equal to the series combination of the sixth and seventh resistors. ADC coupled in parallel with the combination.
前記第１の抵抗器のセットが前記第２の抵抗器のセットよりも多くの抵抗器を含み、前記第１の抵抗器のセットが前記第２の抵抗器のセットと同じ実効抵抗を有する、ＡＤＣ。 17. The ADC according to claim 16 ,
the first set of resistors includes more resistors than the second set of resistors, and the first set of resistors has the same effective resistance as the second set of resistors; ADC.
前記第１の抵抗器のセットが、
前記第１のスイッチと前記ＤＡＣの出力ノードとの間に直列に結合される第４、第５、第６及び第７の抵抗器と、
直列に結合される第８、第９、第１０及び第１１の抵抗器と、
を含み、
前記第４～第７の抵抗器の直列の組み合わせが、前記第８～第１１の抵抗器の直列の組み合わせと並列に結合される、ＡＤＣ。 17. The ADC according to claim 16 ,
The first set of resistors is
fourth, fifth, sixth and seventh resistors coupled in series between the first switch and an output node of the DAC;
eighth, ninth, tenth and eleventh resistors coupled in series;
including;
The ADC, wherein the series combination of the fourth to seventh resistors is coupled in parallel with the series combination of the eighth to eleventh resistors.
前記第１の抵抗器のセットの各抵抗器が、
ｎウェル上に形成されるポリシリコン抵抗器と、
ｐドープ基板と、
前記ｎウェルよりも高いドーピング濃度を有するｎドープ領域と、
ｎドープ領域への電気的接続であって、前記第１のスイッチに結合される、前記電気的接続と、
を含む、ＡＤＣ。 15. The ADC according to claim 14 ,
Each resistor of the first set of resistors is
a polysilicon resistor formed on the n-well;
a p-doped substrate;
an n-doped region having a higher doping concentration than the n-well;
an electrical connection to an n-doped region , the electrical connection coupled to the first switch ;
Including ADC.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US16/582,243 | 2019-09-25 | ||
| US16/582,243 US10892771B1 (en) | 2019-09-25 | 2019-09-25 | Segmented resistor digital-to-analog converter |
| PCT/US2020/051742 WO2021061547A1 (en) | 2019-09-25 | 2020-09-21 | Segmented resistor digital-to-analog converter |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2022550062A JP2022550062A (en) | 2022-11-30 |
| JPWO2021061547A5 true JPWO2021061547A5 (en) | 2023-09-25 |
| JP7513704B2 JP7513704B2 (en) | 2024-07-09 |
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