JPWO2021053948A1 - - Google Patents

Info

Publication number
JPWO2021053948A1
JPWO2021053948A1 JP2021546524A JP2021546524A JPWO2021053948A1 JP WO2021053948 A1 JPWO2021053948 A1 JP WO2021053948A1 JP 2021546524 A JP2021546524 A JP 2021546524A JP 2021546524 A JP2021546524 A JP 2021546524A JP WO2021053948 A1 JPWO2021053948 A1 JP WO2021053948A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2021546524A
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2021053948A1 publication Critical patent/JPWO2021053948A1/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0207—Addressing or allocation; Relocation with multidimensional access, e.g. row/column, matrix
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/771—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/772—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Image Processing (AREA)
JP2021546524A 2019-09-20 2020-07-15 Pending JPWO2021053948A1 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2019171405 2019-09-20
PCT/JP2020/027460 WO2021053948A1 (ja) 2019-09-20 2020-07-15 画像処理装置と画像処理方法およびプログラム

Publications (1)

Publication Number Publication Date
JPWO2021053948A1 true JPWO2021053948A1 (ja) 2021-03-25

Family

ID=74884164

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2021546524A Pending JPWO2021053948A1 (ja) 2019-09-20 2020-07-15

Country Status (4)

Country Link
US (1) US20220377271A1 (ja)
JP (1) JPWO2021053948A1 (ja)
TW (1) TW202129591A (ja)
WO (1) WO2021053948A1 (ja)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100459715C (zh) * 1997-07-31 2009-02-04 日本胜利株式会社 数字视频信号块间预测编码/解码装置及编码/解码方法
EP2399258B1 (en) * 2009-02-20 2016-04-06 Intel Corporation Multimode accessible storage facility
JP5533109B2 (ja) * 2010-03-24 2014-06-25 セイコーエプソン株式会社 画像表示装置、プロジェクター、および、画像表示装置におけるデータの取得方法
JP5893445B2 (ja) * 2012-03-07 2016-03-23 株式会社メガチップス 画像処理装置、および画像処理装置の動作方法
US20140071146A1 (en) * 2012-09-07 2014-03-13 Texas Instruments Incorporated Methods and systems for multimedia data processing

Also Published As

Publication number Publication date
WO2021053948A1 (ja) 2021-03-25
TW202129591A (zh) 2021-08-01
US20220377271A1 (en) 2022-11-24

Similar Documents

Publication Publication Date Title
BR112021017339A2 (ja)
BR112021018450A2 (ja)
BR112021017939A2 (ja)
BR112021017892A2 (ja)
AU2020104490A4 (ja)
BR112021017738A2 (ja)
BR112021017782A2 (ja)
BR112021018168A2 (ja)
BR112021017728A2 (ja)
BR112021018452A2 (ja)
BR112021021744A2 (ja)
BR112021017234A2 (ja)
BR112021017355A2 (ja)
BR112021017703A2 (ja)
BR112021018102A2 (ja)
BR112021017173A2 (ja)
BR112021017083A2 (ja)
BR112021017637A2 (ja)
BR112021018250A2 (ja)
BR112021018084A2 (ja)
BR112021018093A2 (ja)
BR112021018484A2 (ja)
BR112021017732A2 (ja)
BR112021015080A2 (ja)
BR112021017949A2 (ja)

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20230525

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20240514

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20240515

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20240528