JPWO2021045814A5

JPWO2021045814A5 -

Info

Publication number: JPWO2021045814A5
Application number: JP2022514238A
Authority: JP
Publication date: 2023-05-26

Claims

A non-speculative cache memory in a processor-based system, comprising:
a main data array including a plurality of cache entries each configured to store cache data associated with a memory address in a memory system of the processor-based system;
a speculative buffer memory including a plurality of buffer entries each including a data entry configured to store cache data associated with a memory address in the memory system;
is a cache controller,
receiving a data request from a requestor including a target address and an instruction identification (ID) identifying a load instruction containing the target address to be processed by a processor in the processor-based system;
searching for a cache entry in the main data array associated with the target address of the data request;
searching the speculative buffer memory for a buffer entry associated with the target address of the data request;
a data response to the data request based on cache data in the main data array associated with the target address and cache data in a buffer entry in the speculative buffer memory associated with the target address; to the requestor;
receiving a commit indicator including an instruction ID for an instruction that is non-speculative;
in response to the received instruction ID in the commit indicator indicating that the load instruction of the data request is non-speculative;
updating the cache state of a cache entry in the main data array associated with the target address of the data request;
a cache controller configured to:
Non-speculative cache memory, including

the cache controller is further configured to determine if a cache entry in the main data array is associated with the target address of the data request;
In response to a cache entry in the main data array being associated with the target address of the data request, the cache controller causes the main data array to have the target address associated with the target address of the data request. configured to send the data response to the data request to the requester, including cached data in the cache entry in a data array;
2. The non-speculative cache memory of claim 1.

The cache controller associated with the target address of the data request in response to the received instruction ID in the commit indicator indicating that the load instruction of the data request is non-speculative. 3. The non-speculative cache memory of claim 2, configured to update said cache state including cache replacement state of said cache entry in a main data array.

SAR circuitry configured to store speculative access record (SAR) entries including instruction ID entries and main data array entries;
The cache controller further:
In response to a cache entry in the main data array being associated with the target address of the data request, the cache controller further:
Allocate a SAR entry in the SAR circuit, the SAR entry comprising an instruction ID entry containing the instruction ID of the load instruction of the data request and an instruction ID entry in the main data array associated with the target address of the data request. a main data array entry containing an index to the cache entry;
in response to the received instruction ID in the commit indicator indicating that the load instruction of the data request is non-speculative;
determining if the received instruction ID is contained in an instruction ID entry in a SAR entry in the SAR circuit;
responsive to determining that the received instruction ID is included in a SAR entry in the SAR circuit corresponding to the index in the main data array entry in the SAR entry containing the received instruction ID; 4. The non-speculative cache memory of claim 3, configured to: update the cache replacement status of the cache entry in a main data array.

The cache controller is further responsive to a cache entry in the main data array not being associated with the target address of the data request;
determining if a buffer entry in the speculative buffer memory is associated with the target address of the data request;
In response to a buffer entry in said speculative buffer memory being associated with said target address of said data request, said cache controller having said target address associated with said target address of said data request. 3. The non-speculation of claim 2, configured to send to the requestor the data response to the data request, comprising cached data in the buffer entry in a speculative buffer memory. cache memory.

The cache controller is further responsive to a buffer entry in the speculative buffer memory not being associated with the target address of the data request;
sending the data request to the next higher level of memory in the processor-based system;
receiving data for said data request from said next higher level memory;
determining if a buffer entry in the speculative buffer memory is available for storing cache data;
available buffer entries in the speculative buffer memory and the target address of the data request in response to determining that a buffer entry in the speculative buffer memory is available for storing cache data; 6. The non-speculative cache memory of claim 5, configured to write the data for the data request received from the next higher level memory into an available buffer entry associated with the .

in response to the received instruction ID in the commit indicator indicating that the load instruction of the data request is non-speculative;
storing data for the data request in the buffer entry in the speculative buffer memory associated with the target address of the data request in a cache entry in the main data array associated with the target address of the data request; 7. The non-speculation of claim 6, configured to write to update the cache state of the cache entry in the main data array associated with the target address of the data request. cache memory.

The cache controller further determines which of the plurality of buffer entries in the speculative buffer memory should be evicted from the speculative buffer memory based on the speculative state in the non-speculative indicator of each buffer entry. 8. The non-speculative cache memory of claim 7, configured to select .

each buffer entry in the speculative buffer memory further includes a non-speculative indicator indicating whether the buffer entry is non-speculative;
The cache controller further:
in response to a buffer entry in the speculative buffer memory being associated with the target address of the data request;
setting a non-speculative indicator in the buffer entry in the speculative buffer memory associated with the target address of the data request to a speculative state;
in response to the received instruction ID in the commit indicator indicating that the load instruction of the data request is non-speculative;
setting the non-speculative indicator in the buffer entry in the speculative buffer memory associated with the target address of the data request to a non-speculative state;
in response to the non-speculative indicator in the buffer entry in the speculative buffer memory associated with the target address of the data request being set to a non-speculative state;
storing data for the data request in the buffer entry in the speculative buffer memory associated with the target address of the data request in a cache entry in the main data array associated with the target address of the data request; 7. The non-speculation of claim 6, configured to write to update the cache state of the cache entry in the main data array associated with the target address of the data request. cache memory.

SAR circuitry configured to store speculative access record (SAR) entries including instruction ID entries and virtual fill buffer (VFB) index entries;
a VFB circuit configured to store a VFB entry including an instruction ID entry and a VFB index entry;
further comprising
The cache controller further:
in response that no buffer entry in the speculative buffer memory is associated with the target address of the data request;
allocating a VFB entry in said VFB circuit, said VFB entry being an instruction ID entry containing said instruction ID of said load instruction of said data request and in said speculative buffer memory associated with said target address of said data request; a VFB index entry containing an index to the buffer entry of
assigning a SAR entry in said SAR circuit, said SAR entry having said instruction ID entry storing said instruction ID of said load instruction of said data request and an instruction ID entry containing said instruction ID in said VFB circuit said VFB index entry storing an index to a VFB entry;
in response to the received instruction ID in the commit indicator indicating that the load instruction of the data request is non-speculative;
The associated VFB circuit having an instruction ID entry containing the instruction ID indexed based on the index in the VFB index entry in the SAR entry in the SAR circuit having the instruction ID entry containing the received instruction ID. determine the VFB entry in
within the speculative buffer memory associated with the target address of the data request set to a non-speculative state based on the index within the VFB index entry within the determined VFB entry within the VFB circuit; determine the buffer entry;
The cache controller
configured to set the non-speculative indicator in the buffer entry in the determined buffer entry in the speculative buffer memory associated with the target address of the data request to a non-speculative state;
10. The non-speculative cache memory of claim 9, configured to:

The cache controller is further responsive to allocating the SAR entry in the SAR circuit to:
determining if another SAR entry included in the SAR circuit includes the instruction ID in its instruction ID entry and the VFB index entry in its VFB entry;
11. The non-speculative cache memory of claim 10, configured to deallocate the SAR entry within the SAR circuit in response to determining that the another SAR entry is included in the SAR circuit. .

The cache controller is further configured to evict a buffer entry in the speculative buffer memory in response to a cache entry in the main data array being evicted corresponding to a memory address corresponding to the buffer entry. 2. The non-speculative cache memory of claim 1, wherein:

A method for updating cache state in non-speculative cache memory in a processor-based system, comprising:
receiving a data request from a requestor comprising a target address and an instruction identification (ID) identifying a load instruction containing the target address to be processed by a processor in the processor-based system;
among a plurality of cache entries each configured to store cache data associated with a memory address in a memory system of the processor-based system, for a cache entry associated with the target address of the data request; searching the main data array;
a speculative buffer memory for a buffer entry associated with the target address of the data request among a plurality of buffer entries each configured to store cache data associated with a memory address in the memory system; a searching step;
a data response to the data request based on cache entries in the main data array associated with the target address and cache data in buffer entries in the speculative buffer memory associated with the target address; sending to the requestor;
receiving a commit indicator that includes an instruction ID for an instruction that is non-speculative;
a cache in the main data array associated with the target address of the data request in response to the received instruction ID in the commit indicator indicating that the load instruction of the data request is non-speculative; updating the cache state of the entry;
method including.

further comprising determining if a cache entry in the main data array is associated with the target address of the data request;
said cache entry in said main data array having said target address associated with said target address of said data request, in response to said cache entry in said main data array being associated with said target address of said data request; 14. The method of claim 13, comprising sending the data response to the data request, including cached data in a cache entry, to the requester.

in response that no cache entry in the main data array is associated with the target address of the data request;
determining if a buffer entry in the speculative buffer memory is associated with the target address of the data request;
sending to the requestor the data response to the data request including cached data in the buffer entry in the speculative buffer memory having the target address associated with the target address of the data request; ,
15. The method of claim 14, further comprising: