JPWO2021019973A1 - - Google Patents

Info

Publication number
JPWO2021019973A1
JPWO2021019973A1 JP2021536839A JP2021536839A JPWO2021019973A1 JP WO2021019973 A1 JPWO2021019973 A1 JP WO2021019973A1 JP 2021536839 A JP2021536839 A JP 2021536839A JP 2021536839 A JP2021536839 A JP 2021536839A JP WO2021019973 A1 JPWO2021019973 A1 JP WO2021019973A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2021536839A
Other versions
JP7486080B2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2021019973A1 publication Critical patent/JPWO2021019973A1/ja
Application granted granted Critical
Publication of JP7486080B2 publication Critical patent/JP7486080B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/30—Transforming light or analogous information into electric information
    • H04N5/33—Transforming infrared radiation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
    • H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
    • H04N25/65—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/771—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising storage means other than floating diffusion
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
    • H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
    • H04N25/772—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components comprising A/D, V/T, V/F, I/T or I/F converters
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H04N25/79—Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors
JP2021536839A 2019-08-01 2020-06-24 撮像装置 Active JP7486080B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2019142102 2019-08-01
JP2019142102 2019-08-01
PCT/JP2020/024749 WO2021019973A1 (ja) 2019-08-01 2020-06-24 撮像装置

Publications (2)

Publication Number Publication Date
JPWO2021019973A1 true JPWO2021019973A1 (ja) 2021-02-04
JP7486080B2 JP7486080B2 (ja) 2024-05-17

Family

ID=

Also Published As

Publication number Publication date
US20220094873A1 (en) 2022-03-24
US11696051B2 (en) 2023-07-04
CN113785561B (zh) 2023-12-19
CN113785561A (zh) 2021-12-10
WO2021019973A1 (ja) 2021-02-04

Similar Documents

Publication Publication Date Title
BR112021017339A2 (ja)
BR112021018450A2 (ja)
BR112021017939A2 (ja)
BR112021017892A2 (ja)
BR112021017738A2 (ja)
BR112021017782A2 (ja)
BR112021018168A2 (ja)
BR112021017728A2 (ja)
BR112021017234A2 (ja)
BR112021017355A2 (ja)
BR112021018102A2 (ja)
BR112021017173A2 (ja)
BR112021017083A2 (ja)
BR112021017637A2 (ja)
BR112021018452A2 (ja)
BR112021018250A2 (ja)
BR112021018093A2 (ja)
BR112021018084A2 (ja)
BR112021013944A2 (ja)
BR112021018484A2 (ja)
BR112021017732A2 (ja)
BR112021015080A2 (ja)
BR112021017949A2 (ja)
BR112021017983A2 (ja)
BR112021017703A2 (ja)

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20230404

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20240402

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20240419