JPWO2020255324A1 - Array antenna device and beam synthesis method - Google Patents

Abstract

The switching unit (6-k) sequentially switches the numerical value to be multiplied from the weighting coefficient (W), which is numerical string data of time-series numerical values, and multiplies the numerical value to be multiplied by the orthogonally detected digital signal. , The addition unit (7) adds the digital signals of each antenna element (1-k) multiplied by the numerical value to be multiplied, and the integration unit (8) adds the added digital signal to the numerical value to be multiplied. A beam synthesis signal is generated by integrating each time length that can be switched.

Description

The present invention relates to an array antenna device and a beam synthesis method.

Digital beamforming (hereinafter referred to as DBF) is a method of synthesizing signals of a plurality of antenna elements by using digital signal processing. DBF can simplify the analog power supply circuit as compared with the case of synthesizing the signals of a plurality of antenna elements by using analog signal processing, and can be expected to reduce the loss. Since a general DBF type array antenna device requires an A / D converter or a D / A converter for each antenna element, the amount of data becomes enormous and the circuit scale of digital calculation increases.

Conventional techniques for dealing with this problem are described in, for example, Patent Document 1. The receiving device described in Patent Document 1 is a DBF type array antenna device, and a weight calculation for calculating a weighting coefficient required for beam synthesis is performed by a low-speed A / D converter and a low-speed processing circuit. By performing signal processing of the signal system with an analog baseband phase shifter and a high-speed A / D converter, the circuit scale of digital arithmetic is reduced.

Japanese Unexamined Patent Publication No. 2014-192807

In order for the array antenna device to support the dynamic range as a device required by a wireless system, it is necessary to perform a product-sum calculation of weight coefficients having a resolution equivalent to that of a digital signal having a resolution of about a dozen bits in real time. Therefore, a circuit scale proportional to the number of effective bits of digital operation is required. This also applies to the receiving device described in Patent Document 1. In particular, in a large-scale array antenna having a large number of antenna elements, an increase in the circuit scale of digital arithmetic becomes apparent.

The present invention solves the above problems, and an object of the present invention is to obtain an array antenna device and a beam synthesis method capable of reducing the circuit scale of digital arithmetic.

The array antenna device according to the present invention has a plurality of antenna elements, a conversion unit that generates a digital signal corresponding to each of the plurality of antenna elements, an orthogonal detection unit that detects a digital signal orthogonally, and a digital signal that has been orthogonally detected. A beam forming unit that generates a beam synthesis signal based on the beam forming unit is provided, and the beam forming unit sequentially switches the numerical value to be multiplied from the weighting coefficient, which is the numerical string data of the numerical value in time series, to obtain the numerical value to be multiplied. A switching unit that multiplies the orthogonally detected digital signal, an adder that adds the digital signal of each antenna element that has been multiplied by the numerical value to be multiplied, and a time length that allows the added digital signal to be switched between the numerical values to be multiplied. It is equipped with an integrating unit that integrates each signal to generate a beam synthesis signal.

According to the present invention, the numerical value to be multiplied is sequentially switched from the weighting coefficient which is the numerical string data of the numerical value in time series, the numerical value to be multiplied is multiplied by the orthogonally detected digital signal, and the numerical value to be multiplied is obtained. The multiplied digital signals of each antenna element are added, and the added digital signals are integrated for each time length in which the numerical value to be multiplied is switched to generate a beam synthesis signal. By multiplying the digital signal of each antenna element by the weighting coefficient for each numerical value in time series, the number of bits of the weighting coefficient multiplied by the digital signal is reduced, so that the circuit scale of digital calculation can be reduced. ..

It is a block diagram which shows the structure of the array antenna apparatus which concerns on Embodiment 1. FIG. It is a block diagram which shows the structure of the switching part of FIG. It is a flowchart which shows the beam synthesis method which concerns on Embodiment 1. FIG. It is a figure which shows the outline of the weighting coefficient, the in-phase component and the orthogonal component in Embodiment 1. FIG. FIG. 5A is a diagram showing a time waveform of a received signal before A / D conversion in a conventional array antenna device. FIG. 5B is a diagram showing a received signal that has been A / D converted by a conventional array antenna device. FIG. 5C is a diagram showing a weighting coefficient in a conventional array antenna device. FIG. 5D is a diagram showing an output signal of a conventional array antenna device. FIG. 6A is a diagram showing a time waveform of an analog received signal before A / D conversion in the array antenna device according to the first embodiment. FIG. 6B is a diagram showing a received signal A / D converted by the array antenna device according to the first embodiment. FIG. 6C is a diagram showing a weighting coefficient in the array antenna device according to the first embodiment. FIG. 6D is a diagram showing an output signal of the array antenna device according to the first embodiment. It is a figure which shows another outline of the weighting coefficient, the in-phase component and the orthogonal component in Embodiment 1. FIG. FIG. 8A is a block diagram showing a hardware configuration that realizes the function of the DBF unit according to the first embodiment. FIG. 8B is a block diagram showing a hardware configuration for executing software that realizes the function of the DBF unit according to the first embodiment.

Embodiment 1.
FIG. 1 is a block diagram showing a configuration of an array antenna device according to a first embodiment. The array antenna device shown in FIG. 1 is, for example, a DBF antenna device for reception, and includes an antenna element 1-k, an amplification unit 2-k, a DC unit 3-k, an AD conversion unit 4-k, and a DDC unit 5-k. k, switching unit 6-k, addition unit 7, integration unit 8, synchronization unit 9, bit conversion unit 10, excitation distribution setting unit 11, numerical control oscillation unit 12, 90-degree phase shift unit 13, and local oscillation unit 14 are provided. ing. k is a positive natural number, and k = 1, 2, ..., K. Hereinafter, the numerically controlled oscillator 12 will be referred to as an NCO 12, and the local oscillator 14 will be referred to as an LO unit 14.

The antenna element 1-k is a plurality of antenna elements constituting the array antenna. The high frequency signal arriving at the array antenna is received by the antenna element 1-k. The amplification unit 2-k amplifies the signal received by the antenna element 1-k, and outputs the amplified reception signal to the DC unit 3-k.

The DC (down converter) unit 3-k uses the local oscillation signal generated by the LO unit 14 to frequency-convert the signal amplified by the amplification unit 2-k into a low frequency band or baseband band signal. .. The AD conversion unit 4-k is a conversion unit that generates a digital signal corresponding to the antenna element 1-k, and A / D-converts the analog received signal output from the DC unit 3-k into a digital signal.

The DDC (digital down converter) unit 5-k is an orthogonal detection unit that separates the digital signal generated by the AD conversion unit 4-k into an in-phase component and an orthogonal component. For example, the DDC unit 5-k includes a detector for in-phase and a detector for orthogonality. The in-phase detector uses the oscillation signal generated by the NCO 12 to separate the in-phase component (I channel, real part) from the digital signal generated by the AD conversion unit 4-k. The 90-degree phase shift unit 13 shifts the oscillation signal generated by the NCO 12 by 90 degrees. The orthogonal detector uses an oscillation signal that has been phase-shifted by 90 degrees to separate orthogonal components (Q channel, imaginary portion) from the digital signal generated by the AD conversion unit 4-k. The in-phase component Xi and the orthogonal component Xq are output from each DDC unit 5-k to the DBF unit 15.

The DBF unit 15 is a beam forming unit that corresponds to the antenna elements 1-1 to 1-K and generates a beam synthesis signal based on the digital signal orthogonally detected by the DDC unit 5-1 to 5-K. As shown in FIG. 1, the DBF unit 15 includes a switching unit 6-k, an addition unit 7, an integration unit 8, a synchronization unit 9, a bit conversion unit 10, and an excitation distribution setting unit 11. A signal processing unit provided separately from the DBF unit 15 includes a synchronization unit 9, a bit conversion unit 10, and an excitation distribution setting unit 11, and the DBF unit 15 capable of exchanging signals with this signal processing unit switches. Only the unit 6-k, the addition unit 7, and the integration unit 8 may be provided.

The switching unit 6-k sequentially switches the numerical value to be multiplied from the weighting coefficient W, and multiplies the numerical value to be multiplied by the orthogonally detected digital signal X. Here, the weighting coefficient W is obtained by converting the amplitude phase data given to the digital signal X of each antenna element 1-k into numerical string data of time-series numerical values.

Further, the weighting coefficient W is a numerical vector (complex weighting coefficient) composed of amplitude and phase, and has an in-phase component (real part) Wi and an orthogonal component (imaginary part) Wq. For example, the weighting coefficient W is numerical string data in which a numerical value is set so that the complex amplitude phase level of the beam composite signal matches the default value. The default value corresponds to the target complex amplitude phase level of the beam composite signal. Numerical values that make up the numerical string data include, for example, three values of -1, 0, and +1.

For example, the switching unit 6-k sequentially multiplies the in-phase component Wi and the orthogonal component Wq having the weighting coefficient W with respect to the in-phase component Xi and the orthogonal component Xq of the digital signal X output from the DDC unit 5-k. Switch and perform complex multiplication. The in-phase component Wi is the numerical string data [1,0, ..., 0] with a time-series numerical value, and the orthogonal component Wq is the numerical string data [0,1, ..., 1] with a time-series numerical value. In some cases, the switching unit 6-k switches the numerical value "1" at the first time of the in-phase component Wi to the numerical value to be multiplied, and switches the numerical value "0" at the first time of the orthogonal component Wq to the numerical value to be multiplied. , In-phase component Xi and orthogonal component Xq. Next, the numerical value "0" at the time next to the in-phase component Wi is switched to the numerical value to be multiplied, and the numerical value "1" at the time next to the orthogonal component Wq is switched to the numerical value to be multiplied, and the in-phase component Xi and the numerical value to be multiplied are switched. It is multiplied by the orthogonal component Xq. The same process is repeated until the numerical value "0" at the final time of the in-phase component Wi is switched to the numerical value to be multiplied and the numerical value "1" at the final time of the orthogonal component Wq is switched to the numerical value to be multiplied. The digital signal of each antenna element 1-k multiplied by the weighting coefficient W for each numerical value to be multiplied by the switching unit 6-k is output to the adding unit 7.

The addition unit 7 adds the digital signals of each antenna element 1-k multiplied by the numerical value to be multiplied by the weighting coefficient W. For example, when the in-phase component Wi is [1,0, ..., 0] and the orthogonal component Wq is [0,1, ..., 1], the addition unit 7 is the first of the in-phase component Wi. The digital signal of each antenna element 1-k multiplied by the numerical value "1" of the time of and the numerical value "0" of the first time of the orthogonal component Wq is added, and then the numerical value of the next time of the in-phase component Wi ". The digital signal of each antenna element 1-k multiplied by "0" and the numerical value "1" at the next time of the orthogonal component Wq is added. This process is repeated until the digital signal of each antenna element 1-k multiplied by the numerical value “0” of the final time of the phase component Wi and the numerical value “1” of the final time of the orthogonal component Wq is added.

The integrating unit 8 integrates the digital signal calculated by the adding unit 7 for each time length during which the numerical value to be multiplied by the weighting coefficient W is switched to generate a beam synthesis signal. For example, in the integrating unit 8, the switching unit 6-k switches the numerical value to be multiplied from the weighting coefficient W to the current numerical value for each time length from when the numerical value to be multiplied is switched to the numerical value to be multiplied. Time-integrate the added signal. As a result, the time integration is executed for the added signal a number of times equal to the number of numerical values constituting the numerical string data of the weighting coefficient W. The beam synthesis signal is output as an output signal from the integrating unit 8 to a subsequent device (not shown).

The synchronization unit 9 synchronizes each operation of the integration unit 8 and the bit conversion unit 10 with time. Since the switching unit 6-k operates by inputting the weighting coefficient W generated by the bit conversion unit 10, the switching unit 6-k operates in time synchronization with the integrating unit 8.

The bit conversion unit 10 converts the amplitude phase distribution (complex weighting coefficient) set in the excitation distribution setting unit 11 into numerical string data of time-series numerical values. The process of converting the amplitude phase distribution into the numerical string data is called "bit conversion", and the numerical value at each time of the numerical string data is a bit element. For example, a bit element is assigned a numerical value of -1, 0, or + 1.

The excitation distribution setting unit 11 sets amplitude phase data An (n = 1, 2, ..., K) indicating the excitation distribution of the antenna elements 1-1 to 1-K in order to realize the target radiation pattern. do. The excitation distribution includes an amplitude distribution and a phase distribution. For example, the amplitude distribution is an amplitude distribution set so that the sidelobe level is reduced, as represented by the Taylor distribution or the Chebyshev distribution. The phase distribution includes a beam scan or a distribution for forming a null point.

The amplitude phase data An is an aperture distribution required to realize a target radiation pattern, that is, a numerical vector (complex number) consisting of amplitude and phase. In the DBF, the amplitude phase data An is usually used as information discretized with a bit width such as 12 bits or 16 bits.

FIG. 2 is a block diagram showing a configuration of the switching unit 6-k of FIG. As shown in FIG. 2, the switching unit 6-k includes a complex multiplier 61-k and an S / P converter 62-k.
The complex multiplier 61-k is a complex multiplier using the in-phase component Wi of the weighting coefficient W output from the S / P converter 62-k and the orthogonal component Wq on the in-phase component Xi and the orthogonal component Xq of the digital signal X. To execute. As a result, the amplitude and phase of the signals of the antenna elements 1-1 to 1-K are adjusted.

The S / P converter 62-k converts the numerical string data of the weighting coefficient W output from the bit converter 10 into the in-phase component Xi and the orthogonal component Xq of the digital signal X input to the complex multiplier 61-k, respectively. The so-called serial (S) -parallel (P) conversion, which is converted into the numerical string data of the in-phase component Wi of the corresponding weighting coefficient W and the orthogonal component Wq, is executed.
For example, when the in-phase component Wi is [1,0, ..., 0] and the orthogonal component Wq is [0,1, ..., 1], the S / P converter 62-k is in-phase. The numerical value to be multiplied is switched from the component Wi [1,0, ..., 0] to the first numerical value "1", and the first numerical value "0" of the orthogonal component Wq is output to the complex multiplier 61-k. .. The complex multiplier 61-k complex-multiplies the in-phase component Xi and the orthogonal component Xq by using the numerical value “1” of the in-phase component Wi and the numerical value “0” of the orthogonal component Wq.

Next, the beam synthesis method according to the first embodiment will be described.
FIG. 3 is a flowchart showing the beam synthesis method according to the first embodiment, and shows a series of processes from the array antenna device shown in FIG. 1 to the output of the beam synthesis signal.
First, the excitation distribution setting unit 11 sets the excitation distribution related to beam synthesis (step ST1). The excitation distribution is amplitude phase data given to the signals corresponding to each of the antenna elements 1-k. For example, when K = 8, eight amplitude phase data are set for each antenna element.

The bit conversion unit 10 bit-converts the amplitude phase data set by the excitation distribution setting unit 11 (step ST2). For example, the bit conversion unit 10 converts the amplitude phase data into numerical string data of time-series numerical values. The numerical string data is, for example, time-series data of numerical values set so that the complex amplitude level of the beam composite signal matches the default value. The default value is a target value of the complex amplitude level of the beam composite signal.

FIG. 4 is a diagram showing an outline of the weighting coefficient W, the in-phase component Wi, and the orthogonal component Wq in the first embodiment. For example, the bit conversion unit 10 divides the amplitude phase data in the time axis direction and assigns 0 or 1 as an element of the bit at each time. The weighting coefficient W, the in-phase component Wi, and the orthogonal component Wq shown in FIG. 4 are generated from the amplitude phase data divided into five in the time axis direction. By the bit conversion unit 10, for example, [1,0,1,0,1] which is the numerical string data of the in-phase component Wi and [1,1,1,1,1] which is the numerical string data of the orthogonal component Wq are generated. Will be generated.

Further, the weighting coefficient W is a complex number composed of an in-phase component Wi and an orthogonal component Wq, and is represented by W = Wi + j × Wq. j is an imaginary unit. For example, when the in-phase component Wi is [1,0,1,0,1] and the orthogonal component Wq is [1,1,1,1,1], the first numerical values “1” and Wq of Wi From the first numerical value "1" of, the weighting coefficient W at this time is a complex number of W = 1 + j × 1. Subsequently, the weighting coefficient W becomes a complex number of W = 0 + j × 1 from the next numerical value “0” of Wi and the next numerical value “1” of Wq. Similarly, from the next numerical value "1" of Wi and the next numerical value "1" of Wq, the weighting coefficient W becomes a complex number of W = 1 + j × 1, and is next to the next numerical value "0" of Wi and Wq. From the numerical value "1" of, the weighting coefficient W becomes a complex number of W = 0 + j × 1, and finally, from the numerical value "1" next to Wi and the numerical value "1" next to Wq, the weighting coefficient W becomes W =. It is a complex number of 1 + j × 1. Therefore, the weighting coefficient W is W = 3 + j × 5 in the integration for each time length in which the numerical value to be multiplied is switched from Wi and Wq.

The number of integrations is equal to the number of divisions of the weighting coefficient W in the time axis direction.
In the array antenna device according to the first embodiment, the number of integrations is increased as much as possible, and the voltage resolution per bit of the numerical string data having the weighting coefficient W is reduced, so that precise beam synthesis can be performed by a simple product sum. It can be realized by calculation and integration processing.

The antenna element 1-k receives the high frequency signal arriving at the array antenna. The amplification unit 2-k amplifies the signal received by the antenna element 1-k and outputs it to the DC unit 3-k. The DC unit 3-k frequency-converts the frequency of the signal amplified by the amplification unit 2-k by using the local oscillation signal from the LO unit 14.

FIG. 5A is a diagram showing a time waveform of a received signal (analog value) before A / D conversion in the conventional array antenna device, and FIG. 6A is a diagram before A / D conversion in the array antenna device according to the first embodiment. It is a figure which shows the time waveform of the received signal (analog value) of. It is assumed that the received signals shown in FIGS. 5A and 6A are the same.

The conventional array antenna device is not provided with, for example, a switching unit 6-k and an integrating unit 8, and instead is provided with a multiplier for multiplying the weight coefficient corresponding to the signal of each antenna element for each antenna element. , Different from the array antenna device according to the first embodiment.

The AD conversion unit 4-k A / D-converts the analog input signal into a digital signal by sampling the analog input signal (received signal) output from the DC unit 3-k (step ST3).

FIG. 5B is a diagram showing a received signal A / D converted by a conventional array antenna device, and shows a digital signal sampled from the received signal of FIG. 5A. Sampling of the input signal by A / D conversion is usually several samples for a certain signal state (symbol). In the example of FIG. 5B, the conventional array antenna device samples one sample at a time from the received signal (input signal) shown in FIG. 5A at time intervals.

FIG. 6B is a diagram showing a received signal A / D converted by the array antenna device according to the first embodiment, and shows a signal sampled from the received signal of FIG. 6A. The AD conversion unit 4-k samples an input signal for the number of numerical values (number of bits of numerical string data) at the weighting coefficient W from the analog received signal. For example, as shown in FIG. 6B, the AD conversion unit 4-k samples 10 samples of signals at time intervals in which the amplitude of the received signal (input signal) shown in FIG. 6A is high. The time interval in which the signal state has a high amplitude corresponds to the time interval in which the same signal information is received.

Although 10 samples of signals are sampled even at a time interval in which the amplitude is low, since the sampling points are out of the time range shown in FIG. 6B, the description of all the sampling points is omitted in FIG. 6B. There is. Further, the time interval in which the signal state has a low amplitude corresponds to the time interval in which the same signal information is received.
Further, as described with reference to FIG. 4, when the weighting coefficient W is divided into five in the time axis direction, five samples of signals are sampled from the input signal by the AD conversion unit 4-k.

The DDC unit 5-k separates the digital signal X generated by the AD conversion unit 4-k into the in-phase component Wi and the orthogonal component Wq. For example, the DDC unit 5-k separates the in-phase component (I channel, real part) Xi and the orthogonal component (Q channel, imaginary part) Wq from the digital signal X generated by the AD conversion unit 4-k. The in-phase component Xi and the orthogonal component Xq of the digital signal X are output to the DBF unit 15.

FIG. 5C is a diagram showing a weighting coefficient W in a conventional array antenna device, and shows a weighting coefficient W corresponding to the digital signal shown in FIG. 5B. For example, a weighting coefficient corresponding to each of the two digital signals sampled from the received signal shown in FIG. 5A is set.

In the DBF 15, the switching unit 6-k sequentially switches the numerical value to be multiplied from the weighting coefficient W, and performs the multiplication process of the signal X output from the DDC unit 5-k and the numerical value to be multiplied (step ST4). FIG. 6C is a diagram showing a weighting coefficient W of the array antenna device according to the first embodiment. As shown in FIG. 6C, the numerical string data of the weighting coefficient W is composed of numerical values set at the time interval in which the input signal is sampled by the AD conversion unit 4-k. In the example of FIG. 6C, a numerical value of 0 or 1 is assigned as the weighting coefficient W.

For example, the S / P converter 62-k selects a numerical value to be multiplied from the in-phase component Wi among the weighting coefficients W input from the bit conversion unit 10, and the corresponding numerical value is multiplied from the orthogonal component Wq. It is selected as a numerical value and output to the complex multiplier 61-k. The complex multiplier 61-k complex-multiplies the in-phase component Xi and the orthogonal component Xq of the digital signal X with the numerical values to be multiplied by the in-phase component Wi and the orthogonal component Wq. Since the weighting coefficient W is a complex number (W = Wi + j × Wq) composed of the in-phase component Wi and the orthogonal component Wq, the value Y obtained by complexly multiplying the weighting coefficient W and the signal X is Y = W ^* × X = (Wi + j). × Wq) ^* × (Xi + j × Xq). * Is the complex conjugate.

Next, the addition unit 7 adds a digital signal multiplied by a weighting coefficient W corresponding to the antenna element 1-k (step ST5). For example, the addition unit 7 has a digital signal X of each antenna element 1-k in which the numerical value to be multiplied is complexly multiplied each time the numerical value to be multiplied is switched from the weighting coefficient W by the switching unit 6-1 to 6-K. Is added. The digital signal calculated by the addition unit 7 is output to the integration unit 8.

The integrating unit 8 integrates the digital signal added by the adding unit 7 for each time length in which the numerical value to be multiplied by the weighting coefficient W is switched (step ST6). For example, the integrating unit 8 integrates the added digital signals in synchronization with the time interval of the signal state in which the amplitude of the received signal shown in FIG. 6A is high, that is, the time interval in which the same signal information is received. The beam synthesis signal of the antenna element 1-k is generated by this integration process. The beam synthesis signal generated by the integrating unit 8 is output as an output signal (step ST7).

After that, the DBF unit 15 confirms whether or not the above-mentioned processing has been performed on all the input signals (received signals) (step ST8). When all the input signals have been processed (step ST8; YES), the processing of FIG. 3 ends. On the other hand, when there is an unprocessed input signal (step ST8; NO), the process returns to the process of step ST3, and the above-mentioned process is repeated.

FIG. 5D is a diagram showing an output signal of a conventional array antenna device. The DBF unit included in the conventional array antenna device multiplies the orthogonally detected digital signal by the weighting coefficient, and then adds the digital signal of each antenna element to obtain the output signal (beam synthesis signal) shown in FIG. 5D. It was generating. That is, in the conventional array antenna device, it is necessary to multiply the input signal and the weighting coefficient for each antenna element, and the bit width increases in the dimension of the number of multiplications of the weighting coefficient × the number of antenna elements. Therefore, it was not possible to avoid an increase in the circuit scale of digital arithmetic. For example, in fixed-point arithmetic, when a 16-bit input signal is multiplied by a 16-bit weighting coefficient, 32 bits, which is the total number of these bits, are required.

FIG. 6D is a diagram showing an output signal of the array antenna device according to the first embodiment. The integration unit 8 time-integrates the addition signal over the integration interval shown in FIG. 6C to generate the output signal (beam synthesis signal) shown in FIG. 6D. This output signal is the same as the output signal shown in FIG. 5D. In the array antenna device according to the first embodiment, by multiplying the digital signal of each antenna element 1-k by the weighting coefficient W for each numerical value in time series, the multiplication process of the weighting coefficient W is substantially added. Will be replaced. Therefore, even when the 16-bit input signal is multiplied by the 16-bit weighting coefficient, the multiplication process can be performed instantaneously with 16 bits. Further, in the array antenna device according to the first embodiment, it is sufficient to secure the dynamic range required for the integration of the added signal, and the circuit scale of the digital calculation can be significantly reduced.

When a numerical value that takes a value of 0 or 1 is assigned as the numerical value of the numerical string data of the weighting coefficient W, the weighting coefficient W can be expressed by the vector of the first quadrant shown in FIG. Cannot represent a vector. Therefore, in order to express the weighting coefficient W with any vector from the second quadrant to the fourth quadrant, one of the three values of -1, 0 and 1 is assigned to the numerical value of the numerical string data of the weighting coefficient W. May be good.

Further, FIG. 6B shows a case where a plurality of input signals are oversampled, that is, high-speed sampling is performed within one symbol (time interval of a certain signal state), but the result of receiving the same symbol (same signal) multiple times. May be sampled as a digital signal.

Further, a numerical value that can be expressed by 1 bit of -1 or +1 may be assigned as a numerical value constituting the numerical string data of the weighting coefficient W.
FIG. 7 is a diagram showing another outline of the weighting coefficient, the in-phase component, and the orthogonal component in the first embodiment. For example, the bit conversion unit 10 divides the amplitude phase data in the time axis direction and assigns -1 or +1 as an element of the bit at each time. As shown in FIG. 7, the weighting coefficient W, the in-phase component Wi, and the orthogonal component Wq are generated from the amplitude phase data divided into five in the time axis direction. By the bit conversion unit 10, for example, the numerical string data of the in-phase component Wi [1, -1, 1, -1, 1] and the numerical string data of the orthogonal component Wq [1, 1, -1, 1, 1] 1] and are generated instantly.

When the numerical sequence data [1, -1, 1, -1, 1] of the in-phase component Wi is time-integrated five times by the integrating unit 8, 1-1 + 1-1 + 1 = 1, and the numerical sequence data of the orthogonal component Wq [1, -1,1,-1,1] 1,1, -1,1,1] is time-integrated 5 times, and 1 + 1-1 + 1 + 1 = 3, so W = 1 + j × 3 using the in-phase component Wi and the orthogonal component Wq as the weighting coefficient W. Is realized. Since 0 is not set as a numerical value constituting the numerical string data of the weighting coefficient W, there are restrictions on the expression of the weighting coefficient W. However, since the weighting coefficient W can be expressed by two values of -1 or +1 or 1 bit, the number of bits of the weighting coefficient W multiplied by the digital signal can be reduced, and the circuit scale of digital calculation can be reduced. ..

Next, a hardware configuration that realizes the function of the DBF unit 15 of the array antenna device according to the first embodiment will be described.
The functions of the switching unit 6-k, the adding unit 7, the integrating unit 8, the synchronization unit 9, the bit conversion unit 10, and the excitation distribution setting unit 11 in the DBF unit 15 are realized by the processing circuit. That is, the DBF unit 15 includes a processing circuit for executing the processing of steps ST1 to ST8 shown in FIG. The processing circuit may be dedicated hardware, or may be a CPU (Central Processing Unit) that executes a program stored in the memory.

FIG. 8A is a block diagram showing a hardware configuration that realizes the functions of the DBF unit 15. FIG. 8B is a block diagram showing a hardware configuration for executing software that realizes the functions of the DBF unit 15. In FIGS. 8A and 8B, the input interface 100 is an interface for relaying a digital signal input from the DDC unit 5-k to the switching unit 6-k, and is a signal input port such as a USB (Unversal Serial Bus) port or a serial port. Is. The output interface 101 is an interface that relays a signal output from the integrating unit 8 to a subsequent device, and is a signal input port such as a USB port or a serial port.

When the processing circuit is the dedicated hardware shown in FIG. 8A, the processing circuit 102 may be, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), or an FPGA. (Field-Programmable Gate Array) or a combination thereof is applicable. The functions of the switching unit 6-k, the adding unit 7, the integrating unit 8, the synchronizing unit 9, the bit conversion unit 10, and the excitation distribution setting unit 11 may be realized by separate processing circuits, and these functions are summarized. It may be realized by one processing circuit.

When the processing circuit is the processor 103 shown in FIG. 8B, the functions of the switching unit 6-k, the adding unit 7, the integrating unit 8, the synchronizing unit 9, the bit conversion unit 10, and the excitation distribution setting unit 11 are software, firmware, or It is realized by the combination of software and firmware. The software or firmware is written as a program and stored in the memory 104. The processor 103 reads and executes the program stored in the memory 104 to perform the functions of the switching unit 6-k, the adding unit 7, the integrating unit 8, the synchronization unit 9, the bit conversion unit 10, and the excitation distribution setting unit 11. Realize. That is, the DBF unit 15 includes a memory 104 for storing a program in which the processes of steps ST1 to ST8 shown in FIG. 3 are executed as a result when executed by the processor 103. These programs cause a computer to execute the procedure or method of the switching unit 6-k, the addition unit 7, the integration unit 8, the synchronization unit 9, the bit conversion unit 10, and the excitation distribution setting unit 11. The memory 104 is a computer-readable storage medium in which a program for functioning the computer as a switching unit 6-k, an addition unit 7, an integration unit 8, a synchronization unit 9, a bit conversion unit 10, and an excitation distribution setting unit 11 is stored. There may be.

The memory 104 includes, for example, a non-volatile semiconductor such as a RAM (Random Access Memory), a ROM (Read Only Memory), a flash memory, an EPROM (Erasable Programmable Read Only Memory), an EEPROM (Electrically-EPROM), or the like. This includes magnetic disks, flexible disks, optical disks, compact disks, mini disks, DVDs, and the like.

Regarding the functions of the switching unit 6-k, the addition unit 7, the integration unit 8, the synchronization unit 9, the bit conversion unit 10, and the excitation distribution setting unit 11, some of the functions are realized by dedicated hardware, and some of them are software or software. It may be realized by firmware. For example, the switching unit 6-k, the adding unit 7, and the integrating unit 8 are realized by the processor 103 reading and executing the program stored in the memory 104, and the synchronization unit 9, the bit conversion unit 10, and the bit conversion unit 10 are realized. The function of the excitation distribution setting unit 11 may be realized by a processing circuit as dedicated hardware. As described above, the processing circuit can realize each of the above functions by hardware, software, firmware or a combination thereof.

As described above, in the array antenna device and the beam synthesis method according to the first embodiment, the numerical values to be multiplied are sequentially switched from the weighting coefficient W, which is the numerical string data of time-series numerical values, and the numerical values to be multiplied are orthogonal to each other. Multiply the detected digital signal, add the digital signal of each antenna element 1-k multiplied by the numerical value to be multiplied, and integrate the added digital signal for each time length when the numerical value to be multiplied is switched. Generates a beam synthesis signal. By multiplying the digital signal of each antenna element 1-k by the weighting coefficient W for each numerical value in time series, the number of bits of the weighting coefficient multiplied by the digital signal is reduced, so that the circuit scale of digital calculation is reduced. can do.

The present invention is not limited to the above-described embodiment, and within the scope of the present invention, it is possible to modify any component of the embodiment or omit any component of the embodiment.

Since the array antenna device according to the present invention can reduce the circuit scale of digital arithmetic, it can be used in various wireless systems.

1-k, 1-1-1-K antenna element, 2-k, 2-1-2-K amplification section, 3-k, 3-1 to 3-K DC section, 4-k, 4-1 to 4-K AD conversion unit, 5-k, 5-1 to 5-K DDC unit, 6-k, 6-1 to 6-K switching unit, 7 addition unit, 8 integration unit, 9 synchronization unit, 10-bit conversion Part, 11 Excitation distribution setting part, 12 Numerically controlled oscillator (NCO), 13 90 degree phase shift part, 14 Local oscillation part (LO part), 15 DBF part, 61-k complex multiplier, 62-k S / P Converter, 100 input interface, 101 output interface, 102 processing circuit, 103 processor, 104 memory.

Claims (10)

With multiple antenna elements
A converter that generates digital signals corresponding to multiple antenna elements,
An orthogonal detector that detects the digital signal orthogonally and
A beam forming unit that generates a beam synthesis signal based on the orthogonally detected digital signal, and a beam forming unit.
It is an array antenna device equipped with
The beam forming part is
A switching unit that sequentially switches the numerical value to be multiplied from the weighting coefficient, which is numerical string data of time-series numerical values, and multiplies the numerical value to be multiplied by the orthogonally detected digital signal.
An adder that adds the digital signal of each antenna element multiplied by the numerical value to be multiplied, and an adder.
An integrator that generates the beam composite signal by integrating the added digital signals for each time length during which the numerical value to be multiplied is switched, and
An array antenna device characterized by being equipped with. The array antenna device according to claim 1, wherein the weighting coefficient is numerical string data of numerical values taking any value of -1, 0, and +1. The array antenna device according to claim 1, wherein the numerical value constituting the weighting coefficient is numerical value string data of a numerical value having a value of either -1 or +1. The method according to any one of claims 1 to 3, wherein the weighting coefficient is numerical string data in which a numerical value is set so that the complex amplitude phase level of the beam composite signal matches a default value. Array antenna device. The array antenna device according to any one of claims 1 to 3, wherein the integrating unit performs integration in synchronization with a time interval in which the same signal information is received. The step of receiving signals from multiple antenna elements,
A step in which the conversion unit generates a digital signal corresponding to each of a plurality of antenna elements,
A step in which the orthogonal detection unit detects the digital signal orthogonally,
A step in which the beam forming unit generates a beam synthesis signal based on the orthogonally detected digital signal,
It is a beam synthesis method equipped with
A step in which the switching unit sequentially switches the numerical value to be multiplied from the weighting coefficient, which is numerical string data of time-series numerical values, and multiplies the numerical value to be multiplied by the orthogonally detected digital signal.
A step in which the addition unit adds the digital signal of each antenna element multiplied by the numerical value to be multiplied, and
A step in which the integrating unit integrates the added digital signal for each time length during which the numerical value to be multiplied is switched to generate the beam composite signal.
A beam synthesis method characterized by being equipped with. The beam synthesis method according to claim 6, wherein the weighting coefficient is numerical string data of numerical values taking any value of -1, 0, and +1. The beam synthesis method according to claim 6, wherein the numerical value constituting the weighting coefficient is numerical value sequence data of a numerical value having a value of either -1 or +1. 6. Beam synthesis method. The beam synthesis method according to any one of claims 6 to 8, wherein the integrating unit performs integration in synchronization with a time interval in which the same signal information is received.

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