JPWO2020243700A5 - - Google Patents

Download PDF

Info

Publication number
JPWO2020243700A5
JPWO2020243700A5 JP2021572007A JP2021572007A JPWO2020243700A5 JP WO2020243700 A5 JPWO2020243700 A5 JP WO2020243700A5 JP 2021572007 A JP2021572007 A JP 2021572007A JP 2021572007 A JP2021572007 A JP 2021572007A JP WO2020243700 A5 JPWO2020243700 A5 JP WO2020243700A5
Authority
JP
Japan
Prior art keywords
layer
piezoelectric transducers
substrate
attached
piezoelectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2021572007A
Other languages
Japanese (ja)
Other versions
JP2022531022A (en
Publication date
Application filed filed Critical
Priority claimed from PCT/US2020/035537 external-priority patent/WO2020243700A1/en
Publication of JP2022531022A publication Critical patent/JP2022531022A/en
Publication of JPWO2020243700A5 publication Critical patent/JPWO2020243700A5/ja
Pending legal-status Critical Current

Links

Claims (21)

第１の表面、及び対向する第２の表面を有する基板と、
前記基板の前記第１の表面に取り付けられた、１つ又は複数のＣＭＯＳ回路を備えるＣＭＯＳデバイスと、
前記ＣＭＯＳデバイスの外面に取り付けられた、１つ又は複数の圧電トランスデューサと、
を含む、トランシーバ装置であって、
前記１つ又は複数の圧電トランスデューサの各々は、前記基板の前記第２の表面に向かって超音波を放出するように構成されている、
電圧を最大化するためのトランシーバ装置。 a substrate having a first surface and an opposing second surface;
a CMOS device comprising one or more CMOS circuits attached to the first surface of the substrate;
one or more piezoelectric transducers attached to the outer surface of the CMOS device;
A transceiver device comprising:
each of the one or more piezoelectric transducers is configured to emit ultrasonic waves toward the second surface of the substrate;
Transceiver device for maximizing voltage. 前記超音波は、位相調整される、請求項１に記載の装置。 2. The apparatus of claim 1, wherein the ultrasound waves are phased. 前記基板が、可撓性の伸縮性材料から構成される、請求項１に記載の装置。 2. The device of claim 1, wherein the substrate is constructed from a flexible stretchable material. 前記基板は、シリコンウエハ、ＳｉＣウエハ、及びシリカウエハの少なくとも１つから構成される、請求項１に記載の装置。 2. The apparatus of claim 1, wherein said substrate comprises at least one of a silicon wafer, a SiC wafer, and a silica wafer. 前記１つ又は複数の圧電トランスデューサは、ＡｌＮ又はＡｌｘＳｃｙＮから構成される、請求項１に記載の装置。 2. The apparatus of claim 1, wherein the one or more piezoelectric transducers are composed of AlN or AlxScyN . 前記１つ又は複数の圧電トランスデューサの少なくとも１つは、前記基板の前記第２の表面に向けて固定超音波を放射するように構成される、請求項１に記載の装置。 2. The apparatus of claim 1, wherein at least one of said one or more piezoelectric transducers is configured to emit stationary ultrasonic waves toward said second surface of said substrate. 第１の表面、及び対向する第２の表面を有する基板と
前記基板の前記第１の表面に取り付けられた、１つ又は複数の圧電トランスデューサの第１の層と、
前記１つ又は複数の圧電トランスデューサの第１の層に取り付けられた、バッファ層と、
前記バッファ層が前記１つ又は複数の圧電トランスデューサの第１の層、及び第２の層の間となるよう、前記バッファ層に取り付けられた、１つ又は複数の圧電トランスデューサの第２の層と、
を含む、電圧を最大化するためのトランシーバ装置であって、
前記１つ又は複数の圧電トランスデューサの第１の層、及び前記１つ又は複数の圧電トランスデューサの第２の層は、電気コネクタを介してカスケード構成で接続される、
トランシーバ装置。 a substrate having a first surface and an opposing second surface; a first layer of one or more piezoelectric transducers attached to the first surface of the substrate;
a buffer layer attached to the first layer of the one or more piezoelectric transducers;
a second layer of one or more piezoelectric transducers attached to the buffer layer such that the buffer layer is between the first and second layers of the one or more piezoelectric transducers; ,
A transceiver device for maximizing voltage, comprising:
the first layer of the one or more piezoelectric transducers and the second layer of the one or more piezoelectric transducers are connected in a cascade configuration via an electrical connector;
transceiver device. 前記１つ又は複数の圧電層の第２の層の外面に取り付けられた、上部絶縁層と、を更に備える、請求項７に記載の装置。 8. The device of claim 7 , further comprising a top insulating layer attached to the outer surface of the second layer of the one or more piezoelectric layers. １つ又は複数のＣＭＯＳ回路を含むＣＭＯＳデバイスと、を更に含み、
前記ＣＭＯＳデバイスは、前記１つ又は複数の圧電トランスデューサの第１の層と前記基板との間に接続される、
請求項７に記載の装置。 a CMOS device comprising one or more CMOS circuits;
the CMOS device is connected between a first layer of the one or more piezoelectric transducers and the substrate;
8. Apparatus according to claim 7 . 前記ＣＭＯＳデバイスは、ＢＥＯＬ層及びＦＥＯＬ層を含み、
前記ＢＥＯＬ層は、メタライゼーション層であり、前記ＦＥＯＬ層は、前記ＢＥＯＬ層と前記基板との間に接続されたトランジスタ層である、
請求項９に記載の装置。 the CMOS device includes a BEOL layer and a FEOL layer;
wherein the BEOL layer is a metallization layer and the FEOL layer is a transistor layer connected between the BEOL layer and the substrate;
10. Apparatus according to claim 9 . 前記１つ又は複数の圧電トランスデューサの第１の層と前記ＣＭＯＳデバイスとの間に接続された絶縁層と、を更に備える、請求項９に記載の装置。 10. The apparatus of claim 9 , further comprising an insulating layer connected between the first layer of said one or more piezoelectric transducers and said CMOS device. 前記電気コネクタと前記ＣＭＯＳデバイスとを接続する金属ビアと、を更に備える、請求項９に記載の装置。 10. The apparatus of claim 9 , further comprising metal vias connecting said electrical connector and said CMOS device. 前記電気コネクタに接続され、前記１つ又は複数の圧電トランスデューサの第１の層、又は前記１つ又は複数の圧電トランスデューサの第２の層の少なくとも外面まで延在する電気パッドと、を更に備える、請求項７に記載の装置。 an electrical pad connected to the electrical connector and extending to at least an outer surface of the first layer of the one or more piezoelectric transducers or the second layer of the one or more piezoelectric transducers; 8. Apparatus according to claim 7 . 前記基板は、パターンを有する裏面を有する、請求項７に記載の装置。 8. The device of claim 7 , wherein the substrate has a patterned back surface. 前記１つ又は複数の圧電トランスデューサの第２の層は、前記１つ又は複数の圧電トランスデューサのうちの２つの間に、少なくとも１つの空間を備える、請求項７に記載の装置。 8. The apparatus of claim 7 , wherein a second layer of said one or more piezoelectric transducers comprises at least one space between two of said one or more piezoelectric transducers. 前記１つ又は複数の圧電トランスデューサの第１の層、及び前記１つ又は複数の圧電トランスデューサの第２の層の少なくとも１つは、１つの大型トランスデューサである、請求項７に記載の装置。 8. The apparatus of claim 7 , wherein at least one of the first layer of one or more piezoelectric transducers and the second layer of one or more piezoelectric transducers is one large transducer. 前記１つ又は複数の圧電トランスデューサの第１の層、及び前記１つ又は複数の圧電トランスデューサの第２の層の少なくとも１つにおいて、前記圧電トランスデューサは、直列に接続される、請求項７に記載の装置。 8. The method of claim 7 , wherein in at least one of the first layer of the one or more piezoelectric transducers and the second layer of the one or more piezoelectric transducers the piezoelectric transducers are connected in series. device. 前記１つ又は複数の圧電トランスデューサの第１の層、及び前記１つ又は複数の圧電トランスデューサの第２の層の少なくとも１つにおいて、前記圧電トランスデューサは、並列に接続される、請求項７に記載の装置。 8. The method of claim 7 , wherein in at least one of the first layer of the one or more piezoelectric transducers and the second layer of the one or more piezoelectric transducers, the piezoelectric transducers are connected in parallel. device. 前記１つ又は複数の圧電トランスデューサの第１の層、又は前記１つ又は複数の圧電トランスデューサの第２の層うちの少なくとも１つは、前記基板に向かって超音波を放射し、
前記１つ又は複数の圧電トランスデューサの少なくとも１つは、異方性波集中によって決定される波の焦点に基づいて位置決めされる、
請求項７に記載の装置。 at least one of the first layer of the one or more piezoelectric transducers or the second layer of the one or more piezoelectric transducers radiates ultrasonic waves toward the substrate;
at least one of the one or more piezoelectric transducers is positioned based on a wave focus determined by an anisotropic wave concentration;
8. Apparatus according to claim 7 . 第１の表面、及び対向する第２の表面を有する基板と、
前記基板の前記第１の表面に取り付けられた、１つ又は複数の圧電トランスデューサの第１の層と、
前記１つ又は複数の圧電トランスデューサの第１の層に取り付けられた、バッファ層と、
前記バッファ層が前記１つ又は複数の圧電トランスデューサの第１の層、及び第２の層の間となるよう、前記バッファ層に取り付けられた、１つ又は複数の圧電トランスデューサの第２の層と、
を含む、電圧を最大化するためのトランシーバ装置であって
前記１つ又は複数の圧電トランスデューサの第１の層、及び前記１つ又は複数の圧電トランスデューサの第２の層は、第１の構成と第２の構成との間を再構成可能性に達成できるようオン又はオフ可能な１つ又は複数のトランジスタスイッチを有する回路内で接続されている、
トランシーバ装置。 a substrate having a first surface and an opposing second surface;
a first layer of one or more piezoelectric transducers attached to the first surface of the substrate;
a buffer layer attached to the first layer of the one or more piezoelectric transducers;
a second layer of one or more piezoelectric transducers attached to the buffer layer such that the buffer layer is between the first and second layers of the one or more piezoelectric transducers; ,
wherein the first layer of the one or more piezoelectric transducers and the second layer of the one or more piezoelectric transducers have a first configuration and connected in a circuit having one or more transistor switches that can be turned on or off to achieve reconfigurability between a second configuration;
transceiver device. 前記第１の構成において、前記第１の層、及び前記第２の層の少なくとも１つの前記１つ又は複数の圧電トランスデューサは、並列に送信し、
前記第２の構成において、前記第１の層、及び前記第２の層の少なくとも１つの前記１つ又は複数の圧電トランスデューサは、直列に送信する、
請求項２０に記載の装置。
In the first configuration, the one or more piezoelectric transducers of at least one of the first layer and the second layer transmit in parallel;
In the second configuration, the one or more piezoelectric transducers of the first layer and at least one of the second layer transmit in series.
21. Apparatus according to claim 20 .
JP2021572007A 2019-05-30 2020-06-01 How to increase ultrasound signal reception Pending JP2022531022A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201962854933P 2019-05-30 2019-05-30
US62/854,933 2019-05-30
PCT/US2020/035537 WO2020243700A1 (en) 2019-05-30 2020-06-01 Methods of increasing ultrasonic signal reception

Publications (2)

Publication Number Publication Date
JP2022531022A JP2022531022A (en) 2022-07-05
JPWO2020243700A5 true JPWO2020243700A5 (en) 2023-04-25

Family

ID=73553310

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2021572007A Pending JP2022531022A (en) 2019-05-30 2020-06-01 How to increase ultrasound signal reception

Country Status (5)

Country Link
US (1) US20220219197A1 (en)
EP (1) EP3977756A4 (en)
JP (1) JP2022531022A (en)
KR (1) KR20220019722A (en)
WO (1) WO2020243700A1 (en)

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6443900B2 (en) * 2000-03-15 2002-09-03 Olympus Optical Co., Ltd. Ultrasonic wave transducer system and ultrasonic wave transducer
WO2014014968A1 (en) * 2012-07-16 2014-01-23 Cornell University Integrated circuits having integrated acoustic communication links
US10217045B2 (en) 2012-07-16 2019-02-26 Cornell University Computation devices and artificial neurons based on nanoelectromechanical systems
US9475093B2 (en) * 2013-10-03 2016-10-25 Fujifilm Dimatix, Inc. Piezoelectric ultrasonic transducer array with switched operational modes
US9761324B2 (en) 2014-02-03 2017-09-12 Cornell University Piezoelectric and logic integrated delay line memory
US10497748B2 (en) 2015-10-14 2019-12-03 Qualcomm Incorporated Integrated piezoelectric micromechanical ultrasonic transducer pixel and array
US10721568B2 (en) * 2016-07-01 2020-07-21 Intel Corporation Piezoelectric package-integrated acoustic transducer devices

Similar Documents

Publication Publication Date Title
US6784600B2 (en) Ultrasonic membrane transducer for an ultrasonic diagnostic probe
JP4524719B2 (en) Array type ultrasonic transducer
JP2995076B2 (en) Semiconductor device
JP4660087B2 (en) Backing material for ultra-fine processed ultrasonic transducer device
JP6205704B2 (en) Ultrasonic measuring device, head unit, probe and diagnostic device
US10310061B2 (en) Ultrasound transducer and method of manufacturing
JP6186696B2 (en) Ultrasonic measuring device, head unit, probe and diagnostic device
JP6003466B2 (en) Integrated circuit device, ultrasonic measurement device, ultrasonic probe, and ultrasonic diagnostic device
US10721568B2 (en) Piezoelectric package-integrated acoustic transducer devices
JP2013501405A (en) Ultrasonic imaging transducer acoustic stack with integrated electrical connections
US20230034707A1 (en) Packaging structures and packaging methods for ultrasound-on-chip devices
KR101613413B1 (en) Ultrasonic diagnostic instrument and manufacturing method thereof
KR100916029B1 (en) Ultrasonic probe and its method of manufacturing
JP2007513563A (en) Apparatus and method for mounting an IC mounted sensor with a high attenuation backing
JP2015023994A (en) Ultrasonic measurement device, ultrasonic head unit, ultrasonic probe, and ultrasonic imaging device
JP2014083283A (en) Ultrasonic measuring device, head unit, probe, and diagnostic system
JPWO2020243700A5 (en)
US20220094337A1 (en) Integration Method and Integration Structure for Control Circuit and Acoustic Wave Filter
Kuo et al. Towards ultrasonic through-silicon vias (UTSV)
CN110785839B (en) Electronic component device
CN114864806A (en) Ultrasonic transducer with short waveguide structure, manufacturing method and ultrasonic detection device
Suzuki et al. Monolithic Integration of P (VDF-TrFE) Thin Film on CMOS for Wide-band Ultrasonic Transducer Arrays
JP5349141B2 (en) Ultrasonic probe
US20210265233A1 (en) Electronic component and electronic component module including the same
JP2021007117A (en) Piezoelectric transducer and piezoelectric module