JPWO2020200758A5

JPWO2020200758A5 -

Info

Publication number: JPWO2020200758A5
Application number: JP2021549421A
Authority: JP
Publication date: 2022-08-12
Anticipated expiration: 2040-03-17

Claims

is a method,
performing a calibration operation on a set of qubits, said calibration operation determining an initial state of a quantum processor;
estimating a period of execution time of a quantum circuit design corresponding to a quantum algorithm, in response to determining an initial state of the quantum processor, such that the quantum processor executes the quantum circuit design; said estimating, comprising:
calculating error scenarios for the quantum circuit design;
selecting a quantum error correction method for the quantum circuit design using the error scenario and the initial state of the quantum processor;
transforming the quantum algorithm into the quantum circuit design, wherein the quantum circuit design comprises a set of quantum logic gates.

2. The method of claim 1, wherein a subset of the set of quantum logic gates corresponds to the selected quantum error correction method.

3. The method of claim 1 or 2, wherein the initial state of the quantum processor comprises a total number of qubits of the quantum processor.

4. The method of claim 1, 2, or 3, further comprising determining the depth of the quantum circuit design.

5. The method of any of claims 1-4, further comprising assigning a set of weights to the set of quantum logic gates.

6. The method of any of claims 1-5, further comprising comparing the quantum circuit design to a set of previously performed quantum circuit designs.

determining a first computational cost of the selected quantum error correction method;
and determining a second computational cost of the probabilistic quantum error correction method.

comparing the quantum circuit design to a previously performed set of quantum circuit designs;
selecting a quantum error correction method for a first quantum circuit design of the set of previously executed quantum circuit designs;
converting the quantum algorithm to a new quantum circuit design, wherein the new quantum circuit design includes a set of quantum logic gates corresponding to the first quantum circuit design; 8. A method according to any one of claims 1-7.

A program for causing a computer to execute the method according to any one of claims 1 to 8.

A computer system comprising a processor, a computer readable memory, and a computer readable storage device, and program instructions stored in the storage device for execution by the processor through the memory, wherein the stored A program instruction that
program instructions for performing a calibration operation on a set of qubits, said calibration operation determining an initial state of a quantum processor;
Program instructions for estimating a period of execution time of a quantum circuit design corresponding to a quantum algorithm in response to determining an initial state of the quantum processor, the quantum processor executing the quantum circuit design. said program instructions configured to
program instructions for calculating error scenarios for the quantum circuit design;
program instructions for selecting a quantum error correction method for the quantum circuit design using the error scenario and the initial state of the quantum processor;
program instructions for transforming the quantum algorithm into the quantum circuit design, wherein the quantum circuit design comprises a set of quantum logic gates.