JPWO2020182498A5 - - Google Patents

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JPWO2020182498A5
JPWO2020182498A5 JP2021552193A JP2021552193A JPWO2020182498A5 JP WO2020182498 A5 JPWO2020182498 A5 JP WO2020182498A5 JP 2021552193 A JP2021552193 A JP 2021552193A JP 2021552193 A JP2021552193 A JP 2021552193A JP WO2020182498 A5 JPWO2020182498 A5 JP WO2020182498A5
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secure
interrupt
entity
interface control
guest
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JP2021552193A
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JP7398472B2 (en
JP2022522374A (en
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Priority claimed from US16/296,452 external-priority patent/US11308215B2/en
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Claims (13)

割り込みをイネーブルする命令に対する部分的な命令解釈を提供するコンピュータのセキュア・インターフェース制御によって、セキュア・ゲスト・ストレージからプログラム状況ワードまたは制御レジスタ値をフェッチすることと、
前記セキュア・インターフェース制御によって、信頼されないエンティティにゲスト割り込みマスク更新を通知することであって、前記信頼されないエンティティは、前記信頼されないエンティティにおいて実行されるセキュア・エンティティの動作をサポートするために、前記セキュア・インターフェース制御を介して前記コンピュータのハードウェアにおいて実行され、それと通信する、前記通知することと、
前記セキュア・インターフェース制御によって、前記ゲスト割り込みマスク更新を前記通知することに応答して、最高優先順位のイネーブルされたゲスト割り込みを提供する要求を前記信頼されないエンティティから受信することと、
前記セキュア・インターフェース制御によって、ゲスト・プレフィックス・ページに割り込み情報を移動し、前記割り込みの挿入が有効と判定されたときに前記セキュア・エンティティに前記割り込みを挿入することと
を含む、方法。
Fetching a program status word or control register value from secure guest storage by the computer's secure interface control, which provides partial instruction interpretation for the instruction that enables interrupts,
The secure interface control is to notify the untrusted entity of a guest interrupt mask update, the untrusted entity said to support the operation of the secure entity performed on the untrusted entity. The notification, which is executed and communicates with the hardware of the computer via the interface control.
Receiving from the untrusted entity a request to provide the highest priority enabled guest interrupt in response to the notification of the guest interrupt mask update by said secure interface control.
A method comprising moving interrupt information to a guest prefix page by said secure interface control and inserting the interrupt into the secure entity when the insertion of the interrupt is determined to be valid.
前記セキュア・エンティティによって、前記信頼されないエンティティによってモニタされるロード・プログラム状況ワードまたはロード制御を発行することをさらに含む、請求項1に記載の方法。 The method of claim 1, further comprising issuing a load program status word or load control monitored by said untrusted entity by said secure entity. 前記フェッチすることに応答して、前記セキュア・インターフェース制御によって、前記プログラム状況ワードまたは制御レジスタをロードすることをさらに含む、請求項1または2に記載の方法。 The method of claim 1 or 2, further comprising loading the program status word or control register by said secure interface control in response to said fetch. 前記信頼されないエンティティによって、保留およびイネーブルされた割り込みの優先順位付けをして、前記最高優先順位のイネーブルされたゲスト割り込みを決定することをさらに含む、請求項1ないし3のいずれか一項に記載の方法。 13. the method of. 前記信頼されないエンティティによって、前記最高優先順位のイネーブルされたゲスト割り込みに対する割り込み情報を非セキュア・ストレージに記憶することをさらに含む、請求項1ないし4のいずれか一項に記載の方法。 The method of any one of claims 1 to 4, further comprising storing interrupt information for the highest priority enabled guest interrupt in non-secure storage by said untrusted entity. 前記信頼されないエンティティは、状態記述に前記割り込み情報を提供する、請求項5に記載の方法。 The method of claim 5, wherein the untrusted entity provides the interrupt information in the state description. 前記信頼されないエンティティは前記セキュア・インターフェース制御に前記割り込み情報を提供するための命令を発行し、前記割り込み情報は前記命令に対するパラメータとして渡される、請求項5に記載の方法。 The method of claim 5, wherein the untrusted entity issues an instruction to provide the interrupt information to the secure interface control, and the interrupt information is passed as a parameter to the instruction. 前記割り込みの前記挿入が無効と判定されたときに、前記セキュア・インターフェース制御によって、前記信頼されないエンティティに例外を発行することをさらに含む、請求項1ないし7のいずれか一項に記載の方法。 The method of any one of claims 1-7, further comprising issuing an exception to the untrusted entity by said secure interface control when the insertion of the interrupt is determined to be invalid. 前記挿入された割り込みを受信したことに応答して、前記セキュア・エンティティによって割り込みハンドラを実行することをさらに含む、請求項1ないし8のいずれか一項に記載の方法。 The method of any one of claims 1-8, further comprising executing an interrupt handler by the secure entity in response to receiving the inserted interrupt. 前記セキュア・エンティティはセキュア・ゲストを含み、前記信頼されないエンティティはハイパーバイザを含む、請求項9に記載の方法。 9. The method of claim 9, wherein the secure entity comprises a secure guest and the untrusted entity comprises a hypervisor. コンピュータのセキュア・インターフェース制御を含むシステムであって、
前記システムは、割り込みをイネーブルする命令に対する部分的な命令解釈を提供するよう、請求項1ないし10のいずれか1項に記載の方法を行うように構成される、システム。
A system that includes secure interface control of a computer
The system is configured to perform the method of any one of claims 1-10 to provide a partial instruction interpretation for an instruction that enables interrupts.
コンピュータに、請求項1ないし10のいずれか1項に記載の方法を実行させるためのコンピュータ・プログラム。 A computer program for causing a computer to perform the method according to any one of claims 1 to 10. 請求項12に記載のコンピュータ・プログラムを記録したプログラム製品。 A program product recording the computer program according to claim 12.
JP2021552193A 2019-03-08 2020-02-28 Secure interface control high-level instruction intercept for interrupt enable Active JP7398472B2 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/296,452 US11308215B2 (en) 2019-03-08 2019-03-08 Secure interface control high-level instruction interception for interruption enablement
US16/296,452 2019-03-08
PCT/EP2020/055317 WO2020182498A1 (en) 2019-03-08 2020-02-28 Secure interface control high-level instruction interception for interruption enablement

Publications (3)

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JP2022522374A JP2022522374A (en) 2022-04-18
JPWO2020182498A5 true JPWO2020182498A5 (en) 2022-06-07
JP7398472B2 JP7398472B2 (en) 2023-12-14

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US (1) US11308215B2 (en)
EP (1) EP3935532A1 (en)
JP (1) JP7398472B2 (en)
CN (1) CN113544664B (en)
AU (1) AU2020237597B2 (en)
CA (1) CA3132752A1 (en)
IL (1) IL284822B2 (en)
WO (1) WO2020182498A1 (en)

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