JPWO2020156796A5 - - Google Patents
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- JPWO2020156796A5 JPWO2020156796A5 JP2021532167A JP2021532167A JPWO2020156796A5 JP WO2020156796 A5 JPWO2020156796 A5 JP WO2020156796A5 JP 2021532167 A JP2021532167 A JP 2021532167A JP 2021532167 A JP2021532167 A JP 2021532167A JP WO2020156796 A5 JPWO2020156796 A5 JP WO2020156796A5
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- 238000000034 method Methods 0.000 claims 11
- 230000006870 function Effects 0.000 claims 6
- 230000002776 aggregation Effects 0.000 claims 4
- 238000004220 aggregation Methods 0.000 claims 4
- 230000005540 biological transmission Effects 0.000 claims 3
- 238000004590 computer program Methods 0.000 claims 2
- 238000011084 recovery Methods 0.000 claims 2
- 230000011664 signaling Effects 0.000 claims 2
- 230000007547 defect Effects 0.000 claims 1
Claims (22)
コア(12)、システム・ファームウェア(10)、および非同期コア・ネスト・インターフェース(14)を備えるデータ処理ユニット(216)を少なくともさらに備え、
前記データ処理ユニット(216)が、集約バッファ(16)を介して前記システム・ネスト(18)に通信連結され、
前記システム・ネスト(18)が、前記入出力バス(22)に通信連結された少なくとも1つの外部デバイス(214)からデータを非同期的にロードすること、または前記少なくとも1つの外部デバイス(214)にデータを非同期的にストアすること、あるいはその両方を行うように構成され、
(i)前記データ処理システム(210)上で動くオペレーティング・システムが、アドレスを通じたオフセットを伴う入出力機能、移送されることになるデータ、または移送されることになるデータへのポインタ、あるいはその両方、およびデータの長さを少なくとも指定する前記入出力ストア命令(30)を発行すること、
(ii)前記データ処理ユニット(216)が、前記入出力ストア命令(30)で指定された前記アドレスによって前記入出力機能を識別するように構成されること、
(iii)前記データ処理ユニット(216)が、アドレス空間およびゲスト・インスタンス・レベルで前記入出力機能へのアクセスが許可されるかどうかを検証するように構成され、前記ゲストが前記データ処理システム(210)上で動くこと、
(iv)前記データ処理ユニット(216)が、前記システム・ネスト(18)における前記入出力ストア命令(30)の実行が完了する前に、前記入出力ストア命令(30)を完了させるように構成されること、
(v)前記システム・ファームウェア(10)が、前記入出力ストア命令(30)の非同期実行中に前記データ処理ユニット(216)によってエラーが検出された場合、失敗した前記非同期実行の前記データを伝送することを、割込みを通じて前記オペレーティング・システムに通知するように構成されること
を含む、データ処理システム(210)。 A data processing system (210) for handling input / output store instructions (30), which is a system nest (18) communication-connected to at least one input / output bus (22) by an input / output bus controller (20). )
At least an additional data processing unit (216) with core (12), system firmware (10), and asynchronous core nested interface (14).
The data processing unit (216) is communication-connected to the system nest (18) via the aggregation buffer (16).
The system nest (18) asynchronously loads data from at least one external device (214) communication-connected to the input / output bus (22), or to the at least one external device (214). Configured to store data asynchronously, or both,
(I) The operating system running on the data processing system (210) has an input / output function with an offset through the address, data to be transferred, or a pointer to the data to be transferred, or a pointer thereof. Issuing the I / O store instruction (30), which specifies at least both, and the length of the data.
(Ii) The data processing unit (216) is configured to identify the input / output function by the address specified by the input / output store instruction (30).
(Iii) The data processing unit (216) is configured to verify whether access to the input / output function is granted at the address space and guest instance level, and the guest is the data processing system (1). 210) Moving on,
(Iv) The data processing unit (216) is configured to complete the I / O store instruction (30) before the execution of the I / O store instruction (30) in the system nest (18) is complete. To be done,
(V) If the system firmware (10) detects an error by the data processing unit (216) during the asynchronous execution of the input / output store instruction (30), the data of the failed asynchronous execution is transmitted. It is configured to notify the operating system of what to do through an interrupt.
Data processing system (210) , including .
- 階層型物理ターゲット・アドレス、
- SMTスレッドまたは集約バッファ識別子の発生源を確認すること、
- データの長さ、
- 入出力バス・アドレス、
- 回復アルゴリズムのためのシーケンス番号
のうちの1つを含む、請求項1ないし10のいずれか一項に記載のデータ処理システム。 The system message is
-Hierarchical physical target address,
-Identify the source of the SMT thread or aggregate buffer identifier,
-Data length,
-I / O bus address,
-The data processing system of any one of claims 1-10, comprising one of the sequence numbers for the recovery algorithm.
入出力バス・コントローラ(20)によって少なくとも1つの入出力バス(22)に通信連結されたシステム・ネスト(18)を備え、
コア(12)、システム・ファームウェア(10)、および非同期コア・ネスト・インターフェース(14)を備えるデータ処理ユニット(216)を少なくともさらに備え、
前記データ処理ユニット(216)が、集約バッファ(16)を介して前記システム・ネスト(18)に通信連結され、
前記外部デバイス(214)が、前記入出力バス(22)に通信連結され、
前記方法が、
(i)前記データ処理システム(210)上で動くオペレーティング・システムが、アドレスを通じたオフセットを伴う入出力機能、移送されることになるデータ、または移送されることになるデータへのポインタ、あるいはその両方、およびデータの長さを少なくとも指定する前記入出力ストア命令(30)を発行すること、
(ii)前記データ処理ユニット(216)が、前記入出力ストア命令(30)で指定された前記アドレスによって前記入出力機能を識別するように構成されること、
(iii)前記データ処理ユニット(216)が、アドレス空間およびゲスト・インスタンス・レベルで前記入出力機能へのアクセスが許可されるかどうかを検証するように構成され、前記ゲストが前記データ処理システム(210)上で動くこと、
(iv)前記データ処理ユニット(216)が、前記システム・ネスト(18)における前記入出力ストア命令(30)の実行が完了する前に、前記入出力ストア命令(30)を完了させるように構成されること、
(v)前記システム・ファームウェア(10)が、前記入出力ストア命令(30)の非同期実行中に前記データ処理ユニット(216)によってエラーが検出された場合、失敗した前記非同期実行の前記データを伝送することを、割込みを通じて前記オペレーティング・システムに通知するように構成されること
を含む、方法。 A method for handling an input / output store instruction (30) to at least one external device (214) of the data processing system (210), wherein the data processing system (210) is capable of handling the input / output store instruction (30).
A system nest (18) communication-connected to at least one I / O bus (22) by an I / O bus controller (20).
At least an additional data processing unit (216) with core (12), system firmware (10), and asynchronous core nested interface (14).
The data processing unit (216) is communication-connected to the system nest (18) via the aggregation buffer (16).
The external device (214) is communication-connected to the input / output bus (22).
The above method
(I) The operating system running on the data processing system (210) has an input / output function with an offset through the address, data to be transferred, or a pointer to the data to be transferred, or a pointer thereof. Issuing the I / O store instruction (30), which specifies at least both, and the length of the data.
(Ii) The data processing unit (216) is configured to identify the input / output function by the address specified by the input / output store instruction (30).
(Iii) The data processing unit (216) is configured to verify whether access to the input / output function is granted at the address space and guest instance level, and the guest is the data processing system (1). 210) Moving on,
(Iv) The data processing unit (216) is configured to complete the I / O store instruction (30) before the execution of the I / O store instruction (30) in the system nest (18) is complete. To be done,
(V) If the system firmware (10) detects an error by the data processing unit (216) during the asynchronous execution of the input / output store instruction (30), the data of the failed asynchronous execution is transmitted. A method comprising configuring to notify the operating system of what to do through an interrupt.
(ii)前記データの前記長さに応じて、前記データの長さが8バイトを超える場合、システム・メッセージによって前記データが送信されるまで前記システム・ファームウェア(10)が待つ間、ストア・ブロックの全てのデータが前記集約バッファ(16)に転送されるまで前記集約バッファ(16)にデータ・パケットを送信するために、前記システム・ファームウェア(10)が前記システム・メッセージを繰り返し発行し、そうでなければ、
前記集約バッファ(16)に前記データを送信するために、前記システム・ファームウェア(10)がシステム・メッセージを発行すること、
(iii)前記集約バッファ(16)が完了メッセージを送信するのを待つ間、単一のネスト・メッセージとして前記データを非同期的に前記入出力バス・コントローラ(20)に転送するために、前記システム・ファームウェア(10)が、前記集約バッファ(16)へのシステム・メッセージを発行すること、
(iv)前記集約バッファ(16)が、前記システム・ネスト(18)に前記ネスト・メッセージを投入することであって、前記集約バッファ(16)が、送信動作の直後、再使用のための空きがある、投入すること、前記システム・ファームウェア(10)にシグナリングを返すこと、次に、前記集約バッファ(16)が、再使用のための空きがあるというメッセージを送信すること、
(v)前記システム・ネスト(18)が、ターゲット位置に前記メッセージを転送すること、
(vi)前記入出力バス・コントローラ(20)が、前記メッセージを受信し、データ・フレーム内のデータを前記入出力バスに転送すること、
(vii)前記入出力バス・コントローラ(20)が、前記システム・ネスト(18)に完了メッセージを送信すること、
(viii)前記システム・ネスト(18)が、発信元の集約バッファ(16)に前記完了メッセージを転送すること、
(ix)前記集約バッファ(16)が、前記非同期コア・ネスト・インターフェース(14)に完了を転送すること、
(x)前記非同期コア・ネスト・インターフェース(14)が、前記システム・ファームウェア(10)に動作の完了をシグナリングすること、
(xi)エラーの場合、前記システム・ファームウェア(10)が、前記オペレーティング・システムに欠陥を非同期的にシグナリングすること
をさらに含む、請求項12に記載の方法。 (I) The operating system issues the I / O store instruction (30).
(Ii) Depending on the length of the data, if the length of the data exceeds 8 bytes, the store block while the system firmware (10) waits for the data to be transmitted by a system message. The system firmware (10) repeatedly issues the system message in order to send a data packet to the aggregate buffer (16) until all the data in the data is transferred to the aggregate buffer (16). If not,
The system firmware (10) issues a system message to send the data to the aggregate buffer (16).
(Iii) The system to asynchronously transfer the data to the I / O bus controller (20) as a single nested message while waiting for the aggregate buffer (16) to send a completion message. The firmware (10) issues a system message to the aggregation buffer (16).
(Iv) The aggregate buffer (16) inputs the nested message to the system nest (18), and the aggregate buffer (16) is free for reuse immediately after the transmission operation . Is, is populated, returns signaling to the system firmware (10), and then sends a message that the aggregate buffer (16) is free for reuse.
(V) The system nest (18) transfers the message to the target location.
(Vi) The input / output bus controller (20) receives the message and transfers the data in the data frame to the input / output bus.
(Vii) The input / output bus controller (20) sends a completion message to the system nest (18).
(Viii) The system nest (18) transfers the completion message to the source aggregate buffer (16).
(Ix) The aggregation buffer (16) transfers completion to the asynchronous core nested interface (14).
(X) The asynchronous core nested interface (14) signals the completion of operation to the system firmware (10).
(Xi) The method of claim 12, further comprising signaling the system firmware (10) asynchronously a defect to the operating system in the case of an error.
- 階層型物理ターゲット・アドレス、
- SMTスレッドまたは集約バッファ識別子の発生源を確認すること、
- データの長さ、
- 入出力バス・アドレス、
- 回復アルゴリズムのためのシーケンス番号
のうちの1つを含む、請求項12ないし19のいずれか一項に記載の方法。 The system message is
-Hierarchical physical target address,
-Identify the source of the SMT thread or aggregate buffer identifier,
-Data length,
-I / O bus address,
-The method of any one of claims 12-19, comprising one of the sequence numbers for the recovery algorithm.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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EP19154733.0 | 2019-01-31 | ||
EP19154733 | 2019-01-31 | ||
PCT/EP2020/050755 WO2020156796A1 (en) | 2019-01-31 | 2020-01-14 | Handling an input/output store instruction |
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JP2022518340A JP2022518340A (en) | 2022-03-15 |
JPWO2020156796A5 true JPWO2020156796A5 (en) | 2022-06-22 |
JP7461693B2 JP7461693B2 (en) | 2024-04-04 |
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US (2) | US11163566B2 (en) |
EP (1) | EP3918466A1 (en) |
JP (1) | JP7461693B2 (en) |
CN (1) | CN113366433A (en) |
AU (1) | AU2020214661B2 (en) |
CA (1) | CA3127852A1 (en) |
IL (1) | IL284334B2 (en) |
TW (1) | TWI773959B (en) |
WO (1) | WO2020156796A1 (en) |
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KR20210108973A (en) | 2019-01-31 | 2021-09-03 | 인터내셔널 비지네스 머신즈 코포레이션 | Handling of input/output storage commands |
US11748101B2 (en) * | 2021-07-13 | 2023-09-05 | Arm Limited | Handling of single-copy-atomic load/store instruction with a memory access request shared by micro-operations |
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2020
- 2020-01-13 TW TW109101028A patent/TWI773959B/en active
- 2020-01-14 WO PCT/EP2020/050755 patent/WO2020156796A1/en unknown
- 2020-01-14 IL IL284334A patent/IL284334B2/en unknown
- 2020-01-14 CN CN202080011206.8A patent/CN113366433A/en active Pending
- 2020-01-14 AU AU2020214661A patent/AU2020214661B2/en active Active
- 2020-01-14 CA CA3127852A patent/CA3127852A1/en active Pending
- 2020-01-14 JP JP2021532167A patent/JP7461693B2/en active Active
- 2020-01-14 EP EP20700223.9A patent/EP3918466A1/en active Pending
- 2020-01-29 US US16/775,663 patent/US11163566B2/en active Active
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2021
- 2021-09-21 US US17/480,337 patent/US11762659B2/en active Active
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