JPWO2020090025A1 - Arithmetic processing unit and control method of arithmetic processing unit - Google Patents

Abstract

When the number of calculation repetitions by the calculation circuits 107 and 114 that perform exponential calculation or logarithmic calculation and the calculation repetition by the calculation circuits 107 and 114 is less than the threshold value, the number of bits required by the calculation circuits 107 and 114 per cycle is set to the first number. It is provided with setting units 106, 108, 109 for setting the number of bits required by the arithmetic circuits 107, 114 per cycle to a second number, which is larger than the first number, when the number of arithmetic repetitions is larger than the threshold value. Therefore, it is possible to converge on a solution in exponential operation or logarithmic operation without increasing the circuit scale.

Description

The present invention relates to an arithmetic processing unit and a control method for the arithmetic processing unit.

FIG. 8 is a diagram showing a configuration of a conventional arithmetic processing circuit 500.
The arithmetic processing circuit 500 shown in FIG. 8 includes registers 501 to 504, a determination circuit 505, a CSA (Carry-Save Adder) 506, 507, a Log Table circuit 508, and a right shift circuit (RSFT) 509. It includes 510 and arithmetic circuits 511 to 514.

The arithmetic processing circuit 500 is an arithmetic circuit that performs exponential (EXP) arithmetic and logarithmic (LOG) arithmetic. For example, the STL (Sequential Table Lookup) method of radix-4, which obtains a quotient of 2 bits in one operation, is used.

The arithmetic processing circuit 500 takes x as an input and obtains exp (x) in the exponential arithmetic.
L is a space variable of powers and E is a space variable of exponents. Also, i is the number of times the operation is repeated.

The L _i calculated in (L _i calculation), using the following equation (1).
L _{i + 1} = L _i --log (1 + n × 2 ^ -2i) ・ ・ ・ (1)

Further, the calculation of E _i (E _i calculation), using the following equation (2).
E _{i + 1} = E _i × (1 + n × 2 ^ -2i)
= E _i + E _i × n × 2 ^ -2i ・ ・ ・ (2)

However, n = -2, -1, 0, +1, +2, determine the magnitude relationship and difference between _{L i and 0, and select n so that L i} is closest to 0.

The values (register values) stored in the registers 501, 502, 503, 504 may be referred to as LS, LC, ES, and EC, respectively. Further, the registers 501, 502, 503, 504 may be referred to as registers LS, LC, ES, and EC, respectively.

In the arithmetic processing circuit 500, the registers 501 to 504 are initialized so that _{the initial values are L 1} = x and E _{1 = exp (0) = 1.}

Note that LS + LC = L ₁ , for example, x is set in either LS or LC, and 0 is set in the other. Similarly, ES + EC = E ₁ , set 1 for either ES or EC and 0 for the other.

In the arithmetic processing circuit 500, while satisfying _{x = log (E i) +} L i, that closer to 0 gradually the L _i by repeating an operation, E _i approaches _{exp (x) (L i =} x → 0, E _i = exp (0) → exp (x)).

That is, until it reaches the maximum value i in the exponent computation to be processed is defined in advance (imax), repeated E _i and calculation for calculating the L _i operations and E _i to calculate the L _i is performed.

The arithmetic processing circuit 500 takes x as an input and obtains log (x) in logarithmic arithmetic.
L is a variable in logarithmic space and E is a variable in antilogarithm space. Also, i is the number of repetitive operations.

By setting the initial value to L ₁ = log (1) = 0 and E ₁ = x and satisfying x = E _i × exp (L _i ) and repeating the operation _{to gradually bring E i} closer to 1, L _i Approaches log (x) (E _i = x → 1, L _i = log (1) → log (x)).

The calculation methods _{of L i} and E _i in logarithmic calculation _{(L i} calculation, E _i calculation) are almost the same as those of exponential calculation, but the selection method of n is different. That is, the magnitude relationship and difference between _{E i} and 1 are judged, and n is selected so that _{E i is closest to 1.}

In the arithmetic processing circuit 500, Log Table circuits 508 and CSA506 is, to achieve a L _i operations in exponentiation or logarithmic operation. Further, the right shift circuits 509, 510, arithmetic circuits 511 to 514 and CSA507 realize _{E i arithmetic in exponential calculation or logarithmic calculation.}

When performing the exponentiation, the decision circuit 505, based on the L _i, selects n. The determination circuit 505 determines the magnitude relationship and difference between _{L i} and 0, and selects the value of n where _{L i is closest to 0.} On the other hand, when performing logarithmic calculation, the determination circuit 505 selects n based on _{E i.} The determination circuit 505 determines the magnitude relationship and difference between _{E i} and 1, and selects the value of n where _{E i is closest to 1.} The selected n is output to the Log Table circuit 508.

In the Log Table circuit 508, the value of log (1 + n * 2 ^ -2i) corresponding to the variables i and n is set in advance, and the log (1 + n * 2 ^ -2i) corresponding to i and n input from the determination circuit 505 is set. The value of 1 + n * 2 ^ -2i) is output to CSA506.

CSA506 is an adder directly outputs without propagate Ketajo performs L _i calculates (see) by using the equation (1). A string of partial sum bits in the output (calculation result) of CSA506 is input to register 501. On the other hand, a string of carry bits in the output (calculation result) of CSA506 is input to the register 502.

Further, the right shift circuits 509, 510, arithmetic circuits 511 to 514 and CSA507 _{realize E i} arithmetic (see the above equation (2)) in exponential arithmetic.

The right shift circuits 509 and 510 realize 2 ^ -2i multiplication by performing a 2i bit right shift operation on the values ES and EC read from the registers 503 and 504. As a result, the operation of 2 ^ -2i in the above equation (2) is realized. After that, the calculation of E _i × n × 2 ^ -2i is realized by the calculation circuits 511 to 514.

The arithmetic circuits 511 and 512 perform 1x (x1) arithmetic or 2x (x2) arithmetic on the values output from the right shift circuits 509 and 510. For example, when n determined in the determination circuit 505 is +2 or -2, the arithmetic circuits 511 and 512 perform x2 arithmetic. On the other hand, when n determined in the determination circuit 505 is +1 or -1, the arithmetic circuits 511 and 512 perform × 1 arithmetic.

The arithmetic circuits 513 and 514 output the values output from the arithmetic circuits 511 and 512 as through (+) or sign inversion (-). For example, when n determined in the determination circuit 505 is any of +2, +1, and 0, the arithmetic circuits 513 and 514 output through. On the other hand, when n determined in the determination circuit 505 is -2 or -1, the arithmetic circuits 513 and 514 are code-inverted and output.

The CSA507 is an adder that outputs as it is without propagating the digits, and performs _{an E i operation using the above equation (2).} A string of partial sum bits in the output (calculation result) of CSA507 is input to register 503. On the other hand, in the output (calculation result) of CSA507, the carry bit string is input to the register 504.

_{The arithmetic processing circuit 500 outputs the value E i} of the registers 503 and 504 as a result of the exponential operation, _{and outputs the value L i of the} registers 501 and 502 as the result of the logarithmic operation.

However, in such a conventional arithmetic processing circuit 500, when performing an exponential operation, when L _i is far from 0, E _i does not sufficiently approach exp (x) in one operation, and as a result, the operation is performed. _{E i} may not converge to exp (x) even if is repeated. Similarly, when performing logarithmic operations, when E _i is far from 1, Li _i does not approach log (x) sufficiently in one operation, and as a result, even if the operation is repeated, L _i is log (x). May not converge to. This _{is because it is assumed that E i} or L _i is in a range close to the solution to some extent, but when the number of repetitions (i) is small, it may be out of that range.

That is, even if the operation is repeated, E _{i of the} exponential operation or L _{i of the} logarithmic operation may not converge to the solution.

FIG. 9 is a diagram showing a configuration of a conventional arithmetic processing circuit 600 for solving the problem caused by the arithmetic processing circuit 500 as described above.

The arithmetic processing circuit 600 shown in FIG. 9 includes a determination circuit 601, 1st_n table circuit 602 and a selector 603 in place of the determination circuit 505 of the arithmetic processing circuit 500 shown in FIG. Further, the arithmetic circuits 604 and 605 are provided in place of the arithmetic circuits 511 and 512 of the arithmetic processing circuit 500, and the Log Table circuit 606 is provided in place of the Log Table circuit 508. Other parts are configured in the same manner as the arithmetic processing circuit 500 of FIG.

In the figure, the same reference numerals as those described above indicate the same parts, and thus the description thereof will be omitted.

In the arithmetic processing circuit 600 shown in FIG. 9, the selection logic of n is changed only for the first arithmetic (i = 1).

Each output of the 1st_n table circuit 602 and the determination circuit 601 is input to the selector 603.

The 1st_n table circuit 602 is a lookup table that is referred to only in the first operation (i = 1). Only in the first operation (i = 1), the _{1st_n table circuit 602 is referred to with L 1} or E ₁ (that is, the input x) as an index, and the selector 603 selects and outputs the output of the 1st_n table circuit 602.

From the second calculation onward, the selector 603 selects and outputs the output of the determination circuit 601. Further, in the determination circuit 601, ± 3 is added to the options of n as compared with the determination circuit 505 shown in FIG. That is, the determination circuit 601 has -3, -2, -1, 0, +1, +2, +3 as options n.

The output of the selector 603 is input to the arithmetic circuits 513, 514, 604, 605 and the Log Table circuit 606.

Compared to the Log Table circuit 508, the Log Table circuit 606 is provided with additional values corresponding to n = -3 and +3 to the entry.

The arithmetic circuits 604 and 605 are × 1 or × 2 or × 3 circuits, respectively, and are through (× 1), left shift (× 2), or × 3 multiplication according to n output from the determination circuit 601. Do one of the above.

Japanese Unexamined Patent Publication No. 8-123785 Japanese Unexamined Patent Publication No. 2-170285

However, in the conventional arithmetic processing circuit 600 shown in FIG. 9, the circuit scale is increased by providing the 1st_n table circuit 602 and the selectors 603 and the arithmetic circuits 604 and 605. As a result, there is a problem that the number of logical stages of the critical path increases and the delay increases.

The present invention has been devised in view of such a problem, and an object of the present invention is to enable convergence to a solution in exponential or logarithmic operations without increasing the circuit scale.

In order to achieve the above object, this arithmetic processing apparatus includes an arithmetic circuit that performs exponential calculation or logarithmic calculation, and bits obtained by the arithmetic circuit per cycle when the number of arithmetic repetitions by the arithmetic circuit is equal to or less than a threshold value. A setting unit that sets the number to the first number and sets the number of bits required by the calculation circuit per cycle to the second number, which is larger than the first number, when the number of repetitions of the calculation is larger than the threshold value. And.

It can converge to a solution in exponential or logarithmic operations without increasing the circuit scale.

It is a figure which illustrates the structure of the arithmetic processing circuit as an example of an embodiment. It is a figure which illustrates the relationship between the index and the entry of the Log Table circuit in the arithmetic processing circuit as an example of an embodiment. It is a figure which illustrates the circuit structure of the right shift circuit in the arithmetic processing circuit as an example of an embodiment. It is a figure which illustrates the switching rule of the selector of the right shift circuit illustrated in FIG. It is a flowchart for demonstrating the outline of processing of the arithmetic processing circuit as an example of Embodiment. It is a flowchart for demonstrating the arithmetic processing in the arithmetic processing circuit as an example of Embodiment. It is a figure which shows the configuration example which implements the arithmetic processing circuit as an example of Embodiment in a processor. It is a figure which shows the structure of the conventional arithmetic processing circuit. It is a figure which shows the structure of the conventional arithmetic processing circuit.

Hereinafter, embodiments relating to the present arithmetic processing unit and the control method of the arithmetic processing unit will be described with reference to the drawings. However, the embodiments shown below are merely examples, and there is no intention of excluding the application of various modifications and techniques not specified in the embodiments. That is, the present embodiment can be variously modified and implemented within a range that does not deviate from the purpose. Further, each figure does not mean that it includes only the components shown in the figure, but may include other functions and the like.

FIG. 1 is a diagram illustrating a configuration of an arithmetic processing circuit 1 as an example of an embodiment.

The arithmetic processing circuit (arithmetic unit) 1 is provided in, for example, a processor (arithmetic processing unit) of an information processing device to realize arithmetic operations. The arithmetic processing circuit 1 shown in FIG. 1 is an arithmetic processing circuit that realizes two types of operations, an exponential (EXP) operation and a logarithmic (LOG) operation. That is, the arithmetic processing circuit 1 selectively realizes either exponential arithmetic or logarithmic arithmetic.

[Exponential calculation]
In the exponential calculation, for example, the STL (Sequential Table Lookup) method of radix4 for obtaining the quotient 2 bits in one calculation may be used.
For example, take x as an input and find exp (x).
L is a space variable of powers and E is a space variable of exponents. Also, i is the number of times the operation is repeated.

By setting the initial values to L ₁ = x and E ₁ = exp (0) = 1, and satisfying x = log (E _i ) + L _i , repeating the calculation _{to gradually bring L i} closer to 0, E _i Approaches exp (x) (L _i = x → 0, Ei = exp (0) → exp (x)).

[Logarithmic calculation]
The STL method may be used for logarithmic calculation.
For example, take x as an input and find log (x).

L is a variable in logarithmic space and E is a variable in antilogarithm space. Also, i is the number of repetitive operations.

By setting the initial value to L ₁ = log (1) = 0 and E ₁ = x and satisfying x = E _i × exp (L _i ) and repeating the operation _{to gradually bring E i} closer to 1, L _i Approaches log (x) (E _i = x → 1, L _i = log (1) → log (x)).

The calculation methods _{of L i} and E _i in logarithmic calculation _{(L i} calculation, E _i calculation) are almost the same as those of exponential calculation, but the selection method of n is different. That is, the magnitude relationship and difference between _{E i} and 1 are judged, and n is selected so that _{E i is closest to 1.}

(A) Configuration The arithmetic processing circuit 1 shown in FIG. 1 includes registers 101-104, determination circuits 105, CSA107, 114, Log Table circuit 106, right shift circuits (RSFT2) 108, 109, and arithmetic circuits 110-113.

Hereinafter, the register 101 may be referred to as a register LS. Similarly, the register 102 may be referred to as a register LC, the register 103 may be referred to as a register ES, and the register 104 may be referred to as a register EC.

The register 101 is connected to the determination circuit 105 and the CSA 107, respectively. The register 101 stores the result (sum) of the Li operation by CSA107, which will be described later. That is, the register 101 stores the calculation intermediate value generated by the CSA 107 in the process of calculation processing.

The register value L _i read from the register 101 is inputted into the decision circuit 105 and CSA107.

The register 102 is connected to the determination circuit 105 and the CSA 107, respectively. Register 102 to the L _i calculation by CSA107 result (carry) is stored. That is, the register 102 stores the calculation intermediate value generated by the CSA 107 in the process of calculation processing.

Register value L _i read from the register 102 are input to the respective decision circuits 105 and CSA107.

Log Table circuits 106 and CSA107 is, to achieve a L _i operations in exponentiation or logarithmic operation. The right shift circuits 108, 109, arithmetic circuits 110-113 and CSA 114 realize _{E i arithmetic in exponential or logarithmic arithmetic.}

Here, in the present arithmetic processing circuit 1, when the number of repetitions (i) is small, that is, when i is equal to or less than the threshold value k, the number of bits (first number) obtained per cycle is reduced (for example, once). .. Then, after the number of repetitions (i) becomes larger than the threshold value k, the number of bits (second number) obtained per cycle is increased (for example, twice or more). The second number is larger than the first number.

Specifically, for example, the calculation of L _i (L _i calculation) and the calculation of E _i (E _i calculation), using the following equation (3).

Note that n = -2, -1, 0, +1, +2.
In the present embodiment, the number of bits (first number) obtained per cycle is 1 when i ≦ k, and the number of bits (second number) obtained per cycle is 2 when i> k.

When performing the exponentiation, the decision circuit 105, based on the L _i, selects n. The determination circuit 105 determines the magnitude relationship and difference between _{L i} and 0, and selects the value of n where _{L i is closest to 0.} When performing logarithmic calculation, the determination circuit 105 selects n based on _{E i.} The determination circuit 105 determines the magnitude relationship and difference between _{E i} and 1, and selects the value of n where _{E i is closest to 1.}

The value of n determined by the determination circuit 105 is input to the arithmetic circuits 110 to 113 and the Log Table circuit 106.

The Log Table circuit 106 outputs the value of log (1 + n * 2 ^ -A). Here, A = i when i ≤ k, and A = 2i-k when i> k.

The value of log (1 + n * 2 ^ -A) corresponding to the variables i and n is preset in the Log Table circuit 106, and corresponds to i and n input from the determination circuit 105. Output the value of log (1 + n * 2 ^ -A).

That is, the Log Table circuit 106 has i and n as indexes, and each value of log (1 + n × 2 ^ -i) or log (1 + n × 2 ^-(2i-k)) as an entry. Have.

FIG. 2 is a diagram illustrating the relationship between the index and the entry of the Log Table circuit 106 in the arithmetic processing circuit 1 as an example of the embodiment.

In FIG. 2, 1 ≦ i ≦ 9 and an example of k = 3 is shown. Further, in FIG. 2, for convenience, each entry is shown in the form of a logarithm with a log, but in reality, each entry holds a numerical value obtained by calculating the logarithm. In addition, the portion indicated by "don't care" in FIG. 2 is not selected.

The Log Table circuit 106 outputs the value of the entry corresponding to the input i and n to the CSA 107.

The Log Table circuit 106 stores information in which an index and an entry are associated with each other as illustrated in FIG. 2 in a storage device (not shown), and when i and n are input, this information is input. You may refer to i and n as indexes to get the value of the corresponding entry and output it.

Further, the Log Table circuit 106 may acquire information as illustrated in FIG. 2 from the control unit 10 or the like.

The CSA 107 is a 3-input-2 output (3 in − 2 out) carry-save adder, and each output is input from the registers 101 and 102 and the Log Table circuit 106. Further, in the output (calculation result) of the CSA 107, a string of partial sum bits is input to the register 101. On the other hand, in the output (calculation result) of CSA107, the carry bit string is input to the register 102.

The CSA 107 performs an operation of _{L i + 1 (L i} operation). CSA107, using the value of Log output from Table circuit 106 the log (1 + n * 2 ^ -A), and calculates the L _i based on the equation (3).

The register 103 is connected to the determination circuit 105, the right shift circuit 108, and the CSA 114, respectively, and the result (sum) of the _{E i operation by the CSA 114, which will be described later, is stored in the register 103.} That is, the register 103 stores the calculation intermediate value generated by the CSA 114 in the process of calculation processing.

_{The register value E i} read from the register 103 is input to the determination circuit 105, the right shift circuit 108, and the CSA 114, respectively.

The register 104 is connected to the determination circuit 105, the right shift circuit 109, and the CSA 114, respectively. The result (carry) of the _{E i} operation by the CSA 114 is stored in this register 104. That is, the register 104 stores the calculation intermediate value generated by the CSA 114 in the process of calculation processing.

_{The register value E i} read from the register 104 is input to each of the determination circuit 105, the right shift circuit 109, and the CSA 114.

The CSA 114 is a 4-input-2 output (4 in − 2 out) carry-save adder, and each output from the registers 103 and 104 and the arithmetic circuits 112 and 113 is input.

CSA114 is used for exponential or logarithmic operations. The CSA 114 performs an E _{i + 1} operation. The CSA 114 calculates _{E i} based on the above equation (3) using the values output from the registers 103 and 104 and the arithmetic circuits 112 and 113, respectively.

A string of partial sum bits in the output (calculation result) of the CSA 114 is input to the register 103. On the other hand, a string of carry bits in the output (calculation result) of CSA 114 is input to the register 104.

The right shift circuits 108 and 109 perform a right shift on the bit string of the processing target data, and perform a number of bit shifts on the processing target data according to the number of operation repetitions i. The right shift circuit 108 performs a right shift operation on the register output ES of the register 103, and the right shift circuit 109 performs a right shift operation on the register output EC of the register 104, so that E _i × 2 ^ -i Or E _i × 2 ^-(2i-k).

The right shift circuits 108 and 109 _{perform an operation of E i} × 2 ^ -i when i ≦ k, and perform an operation of E _i × 2 ^-(2i-k) when i> k.

Right shift circuit 108 and 109, i only achieves calculation of E _i × 2 ^ -i by right shifting the E _i, 2i-k only E by right shifting the E _{i i} × 2 ^ - ( 2 Realize the operation of i-k). The right shift circuits 108 and 109 have the same configuration as each other.

FIG. 3 is a diagram illustrating the circuit configuration of the right shift circuits 108 and 109 in the arithmetic processing circuit 1 as an example of the embodiment, and FIG. 4 is an example of a switching rule of the selector 1081 of the right shift circuits 108 and 109 illustrated in FIG. It is a figure to do.

_{The right shift circuits 108 and 109 output the calculation result of E i} × 2 ^ -i when i ≦ k by performing selection output by each selector 1081 according to the switching rule illustrated in FIG. 4, and i> k. In the case of, _{the output of the operation result of E i} × 2 ^-(2i-k) is realized.

In FIGS. 3 and 4, right shift circuits 108 and 109 having a data width of 16 bits are illustrated, and the case where k = 3 is shown.

D [15: 0] indicates the data to be shifted, and R [15: 0] indicates the data after the shift. Note that [15] is a sign bit. Also, i is the number of repetitive operations.

The right shift circuits 108 and 109 include selectors 1081 for inputting D for each bit of R (R [0] to R [15]). The selector 1081 selects and outputs according to i with reference to the switching rule illustrated in FIG. The number of inputs of the selector 1801 is the number that i can take (9 in the example shown in FIG. 4).

In the switching rule illustrated in FIG. 4, for example, in R [0], data having a shift amount of i is selected as output data when i ≦ 3, and when i ≧ 4, the shift amount is 2i-k. The data is selected as output data. That is, in the right shift circuits 108 and 109, the shift amount is changed at the threshold value k (k = 3 in the example shown in FIG. 4), and when i ≦ 3, the shift is performed by the operation of _{E i × 2 ^ -i.} Quantity = i bits, and when i> k, the shift amount = 2i-k bits by the operation of _{E i × 2 ^-(2i-k).}

In this way, the right shift circuits 108 and 109 perform a number of bit shifts on the data to be processed according to the number of operation repetitions i. The input D [15: 0] shifted to the right by the i bit becomes R [15: 0].

The arithmetic circuits 110 and 111 perform a 1-fold (x1) operation or a 2-fold (x2) operation on the input value. The arithmetic circuits 110 and 111 realize a 1x (x1) operation by passing through the input value, and a 2x (x2) operation by shifting the input register value to the left by 1 bit.

For example, when n determined in the determination circuit 105 is +2 or -2, the arithmetic circuits 110 and 111 perform × 2 arithmetic. On the other hand, when n determined by the determination circuit 105 is +1 or -1, the arithmetic circuits 110 and 111 perform × 1 arithmetic.

The calculation result by the calculation circuit 110 is input to the calculation circuit 112, and the calculation result by the calculation circuit 111 is input to the calculation circuit 113.

The arithmetic circuits 112 and 113 output the input value through (+) or sign inversion (-). The output from the determination circuit 105 is input to the arithmetic circuits 112 and 113. The arithmetic circuits 112 and 113 select and set a code corresponding to the code of n determined in the determination circuit 105.

The control unit 10 controls the arithmetic processing in the arithmetic processing circuit 1. The control unit 10 operates according to an instruction from the program.

The control unit 10 has a function as an instruction decoder, decodes the contents of an instruction read in an instruction register (not shown), and controls the arithmetic processing circuit 1.

The memory 11 is, for example, a RAM (Random Access Memory). The memory 11 stores, for example, the initial values of the registers 101 to 104. Initial values are provided according to the type of arithmetic processing (exponential arithmetic and logarithmic arithmetic).

The control unit 10 initializes the registers 101 to 104 at the start of the arithmetic processing in the arithmetic processing circuit 1. The control unit 10 may perform initialization by reading an initial value corresponding to the operation type executed in the operation processing circuit 1 from the memory 11 and storing it in each of the registers 101 to 104.

Further, the control unit 10 reads the calculation result from the registers 101 to 104 that store the result of the calculation process and outputs the result.

The control unit 10 may store the information (see FIG. 2) in which the index and the entry referred to by the Log Table circuit 106 are associated with each other in the memory 11 and appropriately provide the information to the Log Table circuit 106.

Further, the control unit 10 may store the switching rule (see FIG. 4) of the selector 1081 referred to by the right shift circuits 108 and 109 in the memory 11 and provide the right shift circuits 108 and 109 as appropriate.

Further, the control unit 10 may give an instruction to start arithmetic processing in the arithmetic processing circuit 1.

The control unit 10 may manage i indicating the number of repetitions (loops) of the calculation in the calculation processing circuit 1. The control unit 10 may count i and compare the value of i with a preset threshold value (imax) to determine that the loop has ended.

(B) Operation An outline of the processing of the arithmetic processing circuit 1 as an example of the embodiment configured as described above will be described with reference to the flowcharts (steps A1 to A15) shown in FIG.

In step A1, the control unit 10 confirms the calculation type. If the operation type is exponential operation (see the EXP route in step A1), the process proceeds to step A2.

In step A2, for example, the right shift circuits 108 and 109 confirm whether the number of repetitions i of the operation is equal to or less than a predetermined threshold value k (for example, k = 3).

As a result of the confirmation, if the number of times the operation is repeated i is equal to or less than the threshold value k (see the YES route in step A2), the process proceeds to step A3. In step A3, the arithmetic processing circuit 1 sets a specified first number (first number of bits: for example, 1 bit) as the number of bits to be obtained per cycle.

On the other hand, when the number of repetitions i of the operation is larger than the threshold value k (see the NO route in step A2), the process proceeds to step A4. In step A4, the arithmetic processing circuit 1 sets a second number (second number of bits: for example, 2 bits) that is larger than the first number as the number of bits to be obtained per cycle. The right shift circuits 108 and 109 execute the right shift operation according to the set number of shifts.

In step A5, the decision circuit 105 selects the n based on L _i.

In step A6, the exponential calculation is executed with the number of bits corresponding to the first number or the second number set in step A3 or step A4.

In step A7, the control unit 10 confirms whether the exponential calculation is completed. As a result of this confirmation, if the exponential calculation is not completed (see the NO route in step A7), the value of i is incremented (i ++) in step A8, and then the process returns to step A2.

If, as a result of the confirmation in step A7, the exponential calculation is completed (see the YES route in step A7), the process proceeds to step A15.

In step A15, the values of registers 103 and 104 are output as the result of the _{E i operation.}

On the other hand, as a result of the confirmation in step A1, if the operation type is logarithmic operation (see the LOG route in step A1), the process proceeds to step A9.

In step S9, the control unit 10 confirms whether the number of times the operation is repeated i is equal to or less than a predetermined threshold value k (for example, k = 3).

As a result of the confirmation, if the number of times the operation is repeated i is equal to or less than the threshold value k (see the YES route in step A9), the process proceeds to step A10. In step A10, the arithmetic processing circuit 1 sets a specified first number (first number of bits: for example, 1 bit) as the number of bits to be obtained per cycle.

On the other hand, when the number of repetitions i of the operation is larger than the threshold value k (see the NO route in step A9), the process proceeds to step A11. In step A11, the arithmetic processing circuit 1 sets a second number (second number of bits: for example, 2 bits) that is larger than the first number as the number of bits to be obtained per cycle. The right shift circuits 108 and 109 execute the right shift operation according to the set number of shifts.

In step A12, the determination circuit 105 selects n based on _{E i.}

Then, in step A6, the logarithmic operation is executed with the number of bits corresponding to the first number or the second number set in step A10 or step A11.

In step A13, the control unit 10 confirms whether the logarithmic calculation is completed. As a result of this confirmation, if the logarithmic calculation is not completed (see the NO route in step A13), the value of i is incremented (i ++) in step A14, and then the process returns to step A9.

If, as a result of the confirmation in step A13, the logarithmic calculation is completed (see the YES route in step A13), the process proceeds to step A15.

In step A15, the values of registers 101 and 102 are output as the result of the _{Li operation.}

Next, the arithmetic processing in the arithmetic processing circuit 1 as an example of the embodiment will be described according to the flowcharts (steps B1 to B23) shown in FIG.

At the start of the arithmetic processing, x is input. In step B1, the control unit 10 confirms the calculation type. If the operation type is exponential operation (see the EXP route in step B1), the process proceeds to step B2.

In step B2, registers 101 to 104 are initialized. The initialization of the register is performed by, for example, the control unit 10. For example, the registers 101 to 104 are initialized so that _{L 1} = x and E _{1 = 1.} Note that LS + LC = L ₁ , for example, x is set in either LS or LC, and 0 is set in the other. Similarly, ES + EC = E ₁ , set 1 for either ES or EC and 0 for the other.

In step B3, a loop process is started in which the control up to step B11 is repeatedly executed until i reaches a predetermined maximum value (imax) in the exponential calculation to be processed.

In step B4, for example, the right shift circuits 108 and 109 confirm whether the number of repetitions i of the operation is equal to or less than a predetermined threshold value k (for example, k = 3).

As a result of the confirmation, when the number of repetitions i of the operation is equal to or less than the threshold value k (see the YES route in step B4), A = i is set in step B5. On the other hand, when the number of repetitions i of the operation is larger than the threshold value k (see the NO route in step B4), A = 2i-k is set in step B6.

After that, in step B7, the determination circuit 105 determines the magnitude relationship and difference between _{L i} and 0, and selects the value of n where _{L i is closest to 0.}

In step B8, the Log Table circuit 106 outputs the value of log (1 + n * 2 ^ -A) corresponding to i and n selected by the determination circuit 105.

In step B9, CSA107, using the Log Table circuit 106 obtained from the log (1 + n * 2 ^ -A), performs L _i calculated based on the equation (3). That is, CSA107 calculates L _{i + 1} = L _i --log (1 + n × 2 ^ -A).

Further, in step B10, the right shift circuits 108 and 109, the arithmetic circuits 110 to 113 and the CSA 114 _{realize the E i} arithmetic in the exponential arithmetic (see the above equation (3)). That is, CSA114 and the like _{calculate E i + 1} = E _i + E _i × n × 2 ^ -A.

After that, the control proceeds to step B11. In step B11, the loop end processing corresponding to step B3 is performed. Here, when i reaches imax (i = imax), the process proceeds to step B12.

In step B12, E _i is output to a processing unit (for example, another arithmetic circuit or the like) in the subsequent stage, and processing ends.

As a result of checking the operation type in step B1, if the operation type is a logarithmic operation (see the LOG route in step B1), the process proceeds to step B13.

In step B13, registers 101 to 104 are initialized. The initialization of the register is performed by, for example, the control unit 10. For example, the registers 101 to 104 are initialized so that _{L 1} = 0 and E _{1 = x.} Note that LS + LC = L ₁ , for example, set 0 for each of LS and LC. Similarly, ES + EC = E ₁ , and one of ES and EC is set to x and the other is set to 0.

In step B14, a loop process is started in which the control up to step B22 is repeatedly executed until i reaches a predetermined maximum value (imax) in the exponential calculation to be processed.

In step B15, for example, the right shift circuits 108 and 109 confirm whether the number of repetitions i of the operation is equal to or less than a predetermined threshold value k (for example, k = 3).

As a result of the confirmation, when the number of repetitions i of the operation is equal to or less than the threshold value k (see the YES route in step B15), A = i is set in step B16. On the other hand, when the number of repetitions i of the operation is larger than the threshold value k (see the NO route in step B15), A = 2i-k is set in step B17.

After that, in step B18, the determination circuit 105 determines the magnitude relationship and difference between _{E i} and 1, and selects the value of n where _{E i is closest to 0.}

In step B19, the Log Table circuit 106 outputs the value of log (1 + n * 2 ^ -A) corresponding to i and n selected by the determination circuit 105.

In step B20, CSA107, using the Log Table circuit 106 obtained from the log (1 + n * 2 ^ -A), performs L _i calculated based on the equation (3). That is, CSA107 calculates L _{i + 1} = L _i --log (1 + n × 2 ^ -A).

Further, in step B21, the right shift circuits 108 and 109, the arithmetic circuits 110 to 113 and the CSA 114 _{realize the E i} arithmetic (see the above equation (3)) in the exponential arithmetic. That is, CSA114 and the like _{calculate E i + 1} = E _i + E _i × n × 2 ^ -A.

After that, the control proceeds to step B22. In step B22, the loop end processing corresponding to step B14 is performed. Here, when i reaches imax (i = imax), the process proceeds to step B23.

In step B23, L _i is output to the subsequent processing unit (for example, other arithmetic circuits, etc.), the process ends.

(C) Effect As described above, according to the arithmetic processing circuit 1 as an example of the embodiment, when the number of repetitions i of the arithmetic i is equal to or less than the threshold value k, the number of bits required per cycle is reduced and the arithmetic is repeated. When the number of times i is larger than the threshold value k, the number of bits to be obtained per cycle is increased. As a result, the exponential operation E _i can be converged to exp (x), and the logarithmic operation L _i can be converged to log (x).

Further, as compared with the conventional arithmetic processing circuit shown in FIG. 9, it is not necessary to provide a 1st_n table circuit or the like, and the circuit scale can be reduced. As a result, the number of logical stages of the critical path can be reduced and the delay can be reduced.

That is, it is possible to converge on a solution in exponential or logarithmic operations without increasing the circuit scale.

(D) Others FIG. 7 is a diagram showing a configuration example in which the arithmetic processing circuit 1 as an example of the above-described embodiment is mounted on a processor for, for example, deep learning.

As illustrated in FIG. 7, a processor for deep learning or the like is provided with a plurality of arithmetic units and performs parallel arithmetic.

Each arithmetic unit includes an EXP / LOG arithmetic unit that performs exponential calculation and logarithmic calculation, and as shown in FIG. 7, the arithmetic processing circuit 1 may be used as the EXP / LOG arithmetic unit provided in the processor.

The processor illustrated in FIG. 7 includes an instruction unit, a plurality of register files # 1 to # m, and a plurality of execution units # 1 to # m.

Each execution unit includes a plurality of (n) arithmetic units # 1 to # n, and these arithmetic units are provided with an arithmetic processing circuit 1.

The processor system illustrated in FIG. 7 has a large occupancy rate of the arithmetic unit with respect to the whole. By applying the arithmetic processing circuit 1 to each such arithmetic unit, the effect of reducing the circuit scale of the arithmetic unit is obtained. Can be played.

The present invention is not limited to the above-described embodiment, and can be modified in various ways without departing from the spirit of the present invention.

Further, according to the above-mentioned disclosure, it is possible for a person skilled in the art to carry out and manufacture the present embodiment.

1 Arithmetic processing circuit 10 Control unit 11 Memory 12 Processor 101-104 Register 105 Judgment circuit 107, 114 CSA
106 Log Table circuit 108, 109 Right shift circuit 110-113 Arithmetic circuit 1081 Selector

Claims (8)

An arithmetic circuit that performs exponential or logarithmic operations,
When the number of arithmetic repetitions by the arithmetic circuit is equal to or less than the threshold value, the number of bits required by the arithmetic circuit per cycle is set to the first number, and when the number of arithmetic repetitions is greater than the threshold value, per cycle. An arithmetic processing apparatus including a setting unit for setting the number of bits required by the arithmetic circuit to a second number larger than the first number. The setting unit is a right shift circuit that shifts the bit string of the data to be processed to the right.
The arithmetic processing unit according to claim 1, wherein the right shift circuit performs a number of bit shifts on the data to be processed according to the number of times the arithmetic is repeated. The calculation circuit is an exponential calculation circuit that performs exponential calculation.
When the number of operation repetitions (i) is less than or equal to the threshold value, L _{i + 1} = L _i --log (1 + n × 2 ^ -i) is calculated.
_{A claim, characterized in that L i + 1} = L _i --log (1 + n × 2 ^-(2i-k)) is calculated when the number of repetitions (i) of the calculation is larger than the threshold value. The arithmetic processing unit according to 1 or 2. The arithmetic circuit is an exponential arithmetic circuit that performs logarithmic arithmetic.
When the number of operation repetitions (i) is less than or equal to the threshold value, E _{i + 1} = E _i + E _i × n × 2 ^ -i is calculated.
_{Claims 1 to 3, characterized in that E i + 1} = E _i + Ei × n × 2 ^-(2i-k) is calculated when the number of repetitions (i) of the calculation is larger than the threshold value. The arithmetic processing unit according to any one of the above items. In an arithmetic processing unit including an arithmetic circuit that performs exponential calculation or logarithmic calculation,
The process of confirming the number of arithmetic repetitions by the arithmetic circuit and
When the number of arithmetic repetitions by the arithmetic circuit is equal to or less than the threshold value, the number of bits required by the arithmetic circuit per cycle is set to the first number, and when the number of arithmetic repetitions is greater than the threshold value, the number of bits per cycle is set. A method for controlling an arithmetic processing apparatus, which comprises a process of setting the number of bits required by the arithmetic circuit to a second number larger than the first number. The fifth aspect of claim 5, wherein the right shift circuit that shifts the bit string of the data to be processed to the right performs a number of bit shifts to the data to be processed according to the number of repetitions of the calculation. A control method for arithmetic processing units. The calculation circuit is an exponential calculation circuit that performs exponential calculation.
When the number of operation repetitions (i) is less than or equal to the threshold value, L _{i + 1} = L _i --log (1 + n × 2 ^ -i) is calculated.
_{A claim, characterized in that L i + 1} = L _i --log (1 + n × 2 ^-(2i-k)) is calculated when the number of repetitions (i) of the calculation is larger than the threshold value. 5. The method for controlling an arithmetic processing unit according to 5 or 6. The arithmetic circuit is an exponential arithmetic circuit that performs logarithmic arithmetic.
When the number of operation repetitions (i) is less than or equal to the threshold value, E _{i + 1} = E _i + E _i × n × 2 ^ -i is calculated.
In the case of the calculation repetition count (i) is greater than the _{threshold, E i + 1 = E i} + Ei × n × 2 ^ - characterized by calculating the (2i-k), according to claim 5 7. The method for controlling an arithmetic processing unit according to any one of 7.

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