JPWO2020051388A5 - - Google Patents
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- JPWO2020051388A5 JPWO2020051388A5 JP2021512671A JP2021512671A JPWO2020051388A5 JP WO2020051388 A5 JPWO2020051388 A5 JP WO2020051388A5 JP 2021512671 A JP2021512671 A JP 2021512671A JP 2021512671 A JP2021512671 A JP 2021512671A JP WO2020051388 A5 JPWO2020051388 A5 JP WO2020051388A5
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- 235000012431 wafers Nutrition 0.000 claims 77
- 230000004907 flux Effects 0.000 claims 53
- 238000005259 measurement Methods 0.000 claims 43
- 238000000034 method Methods 0.000 claims 29
- 238000009529 body temperature measurement Methods 0.000 claims 27
- 230000008569 process Effects 0.000 claims 23
- 239000010410 layer Substances 0.000 claims 10
- 239000012790 adhesive layer Substances 0.000 claims 4
- 230000006870 function Effects 0.000 claims 3
- 238000013507 mapping Methods 0.000 claims 3
- 230000008859 change Effects 0.000 claims 2
- 230000008878 coupling Effects 0.000 claims 2
- 238000010168 coupling process Methods 0.000 claims 2
- 238000005859 coupling reaction Methods 0.000 claims 2
- 239000011229 interlayer Substances 0.000 claims 2
- 239000012528 membrane Substances 0.000 claims 2
- 229910052751 metal Inorganic materials 0.000 claims 2
- 239000002184 metal Substances 0.000 claims 2
- 239000004065 semiconductor Substances 0.000 claims 2
- 229910052710 silicon Inorganic materials 0.000 claims 2
- 239000010703 silicon Substances 0.000 claims 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims 1
- 229910052581 Si3N4 Inorganic materials 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- 238000004891 communication Methods 0.000 claims 1
- 238000009713 electroplating Methods 0.000 claims 1
- 229910052733 gallium Inorganic materials 0.000 claims 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims 1
- 229910052738 indium Inorganic materials 0.000 claims 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims 1
- 229910010272 inorganic material Inorganic materials 0.000 claims 1
- 239000011147 inorganic material Substances 0.000 claims 1
- 239000007791 liquid phase Substances 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
- 239000002245 particle Substances 0.000 claims 1
- 230000005855 radiation Effects 0.000 claims 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims 1
- 229910010271 silicon carbide Inorganic materials 0.000 claims 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims 1
- 230000007480 spreading Effects 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
- 238000012546 transfer Methods 0.000 claims 1
- 230000001052 transient effect Effects 0.000 claims 1
Claims (44)
下ウェハと、
上ウェハと、
１個又は複数個の印刷回路要素上に配置され且つ上ウェハ・下ウェハ間に間挿された１個又は複数個の電子部品と、
前記１個又は複数個の電子部品と前記上ウェア、前記１個又は複数個の電子部品と前記下ウェア、前記下ウェハと前記上ウェハ、のそれぞれの間に配置された１個又は複数個の遮蔽層であり、前記１個又は複数個の電子部品と前記上ウェハとの間に介在する、遮蔽層と、
前記１個又は複数個の遮蔽層は導電性であり、前記上ウェハと前記下ウェハの表面との間に電気的接触を形成し、前記電気的接触は、電圧電位を拡散し、プロセス条件計測ウェハアセンブリの温度上昇により引き起こされる前記１個又は複数個の電子部品の取得計測パラメタの相違を低減するように構成され、
前記１個又は複数個の遮蔽層は、前記１個又は複数個の電子部品を電磁的に遮蔽するように構成され、
前記上ウェハの表面または前記下ウェハの表面の少なくとも一方に形成された複数個の導電構造であって、前記上ウェハの少なくとも一部分を前記下ウェハの少なくとも一部分に電気的に結合する、複数個の導電構造と、
を備えるアセンブリ。 A process condition metrology wafer assembly comprising:
a lower wafer ;
an upper wafer ;
one or more electronic components disposed on one or more printed circuit elements and interposed between the upper and lower wafers ;
one or more electronic components and the upper wafer, the one or more electronic components and the lower wafer, or the lower wafer and the upper wafer, respectively. a shielding layer interposed between the one or more electronic components and the top wafer;
The one or more shield layers are electrically conductive and form electrical contact between the top wafer and the bottom wafer surface, the electrical contact spreading voltage potentials and process condition measurements. configured to reduce differences in acquired metrology parameters of the one or more electronic components caused by temperature rise of the wafer assembly;
wherein the one or more shielding layers are configured to electromagnetically shield the one or more electronic components;
A plurality of conductive structures formed on at least one of the surface of the top wafer or the surface of the bottom wafer, the plurality of conductive structures electrically coupling at least a portion of the top wafer to at least a portion of the bottom wafer. a conductive structure;
assembly.
前記下ウェハの表面上及び前記上ウェハの表面上のうち少なくとも一方に配置された１個又は複数個の膜を備え、当該１個又は複数個の膜が導電性であり且つ不透明なアセンブリ。 2. The assembly of Claim 1, wherein the one or more shielding layers comprise:
An assembly comprising one or more membranes disposed on at least one of the bottom wafer surface and the top wafer surface, the one or more membranes being conductive and opaque.
接着層と、
前記接着層内に滞留する複数個の導電粒子であり、前記上ウェハの一部分と前記下ウェハの一部分との間に電気的接触を確立するよう構成されている複数個の導電粒子と、
を備えるアセンブリ。 2. The assembly of Claim 1, wherein the one or more shielding layers comprise:
an adhesive layer;
a plurality of conductive particles residing within the adhesive layer and configured to establish electrical contact between a portion of the top wafer and a portion of the bottom wafer ;
assembly.
接着層
を備え、前記接着層が前記複数個の導電構造の周囲に形成されているアセンブリ。 2. The assembly of Claim 1, wherein the one or more shielding layers comprise:
adhesive layer
and wherein said adhesive layer is formed around said plurality of conductive structures.
過渡液相接合プロセスにより上表面上及び下表面上のうち少なくとも一方に堆積された１個又は複数個の膜を含むアセンブリ。 2. The assembly of Claim 1, wherein the one or more shielding layers comprise:
An assembly including one or more films deposited on at least one of a top surface and a bottom surface by a transient liquid phase bonding process.
前記上ウェハ上及び前記下ウェハ上のうち少なくとも一方に形成された１個又は複数個の柱状構造を備え、当該１個又は複数個の柱状構造が、前記１個又は複数個の印刷回路要素の一部分又は複数部分を通る熱伝達路を確立するよう構成されているアセンブリ。 2. The assembly of claim 1, further comprising:
one or more columnar structures formed on at least one of the upper wafer and the lower wafer , wherein the one or more columnar structures are aligned with the one or more printed circuit elements; An assembly configured to establish a heat transfer path through a portion or portions.
シリコンウェハ、シリコンカーバイドウェハ、窒化シリコンウェハ、窒化ガリウムウェハ、砒化ガリウムウェハ、ゲルマニウムウェハ、並びにガリウム及びインジウム製のウェハのうち、少なくとも一つを備えるアセンブリ。 18. The assembly of claim 17, wherein at least one of said top wafer and said bottom wafer :
An assembly comprising at least one of a silicon wafer , a silicon carbide wafer , a silicon nitride wafer , a gallium nitride wafer , a gallium arsenide wafer , a germanium wafer , and a gallium and indium wafer .
１個又は複数個の温度センサ、１個又は複数個の圧力センサ、１個又は複数個の化学物質センサ、並びに１個又は複数個の輻射センサのうち、少なくとも一つを含むアセンブリ。 2. The assembly of claim 1, wherein the one or more electronic components are
An assembly including at least one of one or more temperature sensors, one or more pressure sensors, one or more chemical sensors, and one or more radiation sensors.
１個又は複数個のプロセッサと、
通信回路と、
メモリと、
電源と、
を含むアセンブリ。 21. The assembly of claim 20 , wherein the one or more electronic components are
one or more processors;
a communication circuit;
memory;
a power supply;
Assembly containing .
前記１個又は複数個の電子部品に可通信結合されたリモートデータシステムを備え、獲得した１個又は複数個の計測パラメタをそのリモートデータシステムに送信するよう当該１個又は複数個の電子部品が構成されており、獲得した１個又は複数個の計測パラメタから値を計算するようそのリモートデータシステムが構成されているアセンブリ。 2. The assembly of claim 1, further comprising:
a remote data system communicatively coupled to the one or more electronic components, the one or more electronic components to transmit one or more acquired measurement parameters to the remote data system; An assembly configured and whose remote data system is configured to calculate a value from one or more acquired measurement parameters.
上ウェハと、
１個又は複数個の印刷回路要素上に配置され且つ前記上ウェハ・前記下ウェハ間に間挿された１個又は複数個の電子部品と、
を備え、前記下ウェハ及び前記上ウェハのうち少なくとも一方が、前記１個又は複数個の電子部品を電磁的に遮蔽し、前記下ウェハおよび前記上ウェハにわたって電圧電位を拡散させるように構成され、前記１個又は複数個の電子部品を電磁的に遮蔽し、前記下ウェハおよび前記上ウェハにわたって前記電圧電位を拡散させるように構成された前記下ウェハまたは前記上ウェハのうちの少なくとも１つはまた、プロセス条件測定ウェハアセンブリの温度上昇によって引き起こされる前記１個または複数個の電子部品の取得計測パラメタの相違を低減するように構成され、
前記上ウェハの表面または前記下ウェハの表面の少なくとも一方に形成された複数個の導電構造であって、前記上ウェハの少なくとも一部分と前記下ウェハの少なくとも一部分とを電気的に結合する複数個の導電構造と、
を備えるプロセス条件計測ウェハアセンブリ。 a lower wafer ;
an upper wafer ;
one or more electronic components disposed on one or more printed circuit elements and interposed between the upper and lower wafers ;
at least one of the bottom wafer and the top wafer configured to electromagnetically shield the one or more electronic components and spread a voltage potential across the bottom wafer and the top wafer; at least one of the bottom wafer or the top wafer configured to electromagnetically shield the one or more electronic components and spread the voltage potential across the bottom wafer and the top wafer; configured to reduce differences in acquired metrology parameters of the one or more electronic components caused by temperature increases in the process condition measurement wafer assembly;
a plurality of conductive structures formed on at least one of the top wafer surface and the bottom wafer surface electrically coupling at least a portion of the top wafer and at least a portion of the bottom wafer; a conductive structure;
a process condition metrology wafer assembly.
恒温条件下で、一組の温度センサから一組の温度測定値を取得し、一組の熱流束センサから一組の熱流束測定値を取得するステップと、obtaining a set of temperature measurements from a set of temperature sensors and a set of heat flux measurements from a set of heat flux sensors under isothermal conditions;
恒温条件下で取得された前記一組の温度測定値および前記一組の熱流束測定値を較正するステップと、calibrating the set of temperature measurements and the set of heat flux measurements taken under isothermal conditions;
プロセス条件計測ウェハに既知の熱流束を適用するステップと、applying a known heat flux to the process condition metrology wafer;
前記既知の熱流束の適用中に、前記一組の温度センサから一組の付加的温度測定値を取得し、前記一組の熱流束センサから一組の付加的熱流束測定値を取得するステップと、obtaining a set of additional temperature measurements from the set of temperature sensors and a set of additional heat flux measurements from the set of heat flux sensors during application of the known heat flux; When,
既知の熱流束の適用中に前記一組の温度センサにわたって観察される温度変動を識別するステップと、identifying temperature variations observed across the set of temperature sensors during application of a known heat flux;
既知の熱流束を前記一組の温度センサの識別された温度変化と相関させることによって熱流束－温度変化関係を識別するステップと、identifying a heat flux-temperature change relationship by correlating the known heat flux with the identified temperature change of the set of temperature sensors;
未知の熱流束条件下で、前記一組の温度センサから一組の試験的温度測定値を取得し、前記一組の熱流束センサから一組の試験的熱流束測定値を取得するステップと、obtaining a set of trial temperature measurements from the set of temperature sensors and a set of trial heat flux measurements from the set of heat flux sensors under unknown heat flux conditions;
前記一組の試験的熱流束測定値および識別された熱流束－温度変動関係に基づいて、前記一組の試験的温度測定値を調整するステップと、adjusting the set of tentative temperature measurements based on the set of tentative heat flux measurements and the identified heat flux-temperature variation relationship;
を備える方法。How to prepare.
をさらに含む請求項２７に記載の方法。28. The method of claim 27, further comprising:
をさらに含む請求項２７に記載の方法。28. The method of claim 27, further comprising:
前記恒温条件下で取得された前記一組の温度測定値および前記一組の熱流束測定値をベースラインとして設定するステップsetting the set of temperature measurements and the set of heat flux measurements taken under the isothermal conditions as a baseline;
を含む請求項２７に記載の方法。28. The method of claim 27, comprising:
熱源に前記既知の熱流束をプロセス条件計測ウェハに印加させるステップcausing a heat source to apply the known heat flux to the process condition measurement wafer;
を含む請求項２７に記載の方法。28. The method of claim 27, comprising:
プロセス条件計測ウェハの一組の温度センサおよび一組の熱流束センサに通信可能に結合可能な１個又は複数個のプロセッサであって、前記１個または複数個のプロセッサは、One or more processors communicatively coupled to a set of temperature sensors and a set of heat flux sensors of a process condition metrology wafer, said one or more processors comprising:
恒温条件下で、前記一組の温度センサから一組の温度測定値を取得し、前記一組の熱流束センサから一組の熱流束測定値を取得し、obtaining a set of temperature measurements from the set of temperature sensors and a set of heat flux measurements from the set of heat flux sensors under isothermal conditions;
恒温条件下で取得された前記一組の温度測定値および前記一組の熱流束測定値を較正し、calibrating the set of temperature measurements and the set of heat flux measurements taken under isothermal conditions;
既知の熱流束の適用中に、前記一組の温度センサから一組の付加的温度測定値を取得し、前記一組の熱流束センサから一組の付加的熱流束測定値を取得し、obtaining a set of additional temperature measurements from the set of temperature sensors and obtaining a set of additional heat flux measurements from the set of heat flux sensors during application of a known heat flux;
既知の熱流束の適用中に前記一組の温度センサにわたる温度変動を識別し、identifying temperature variations across the set of temperature sensors during application of a known heat flux;
既知の熱流束を前記一組の温度センサの識別された温度変動と相関させることによって、熱流束－温度変動関係を識別し、identifying a heat flux-temperature variation relationship by correlating the known heat flux with the identified temperature variation of the set of temperature sensors;
未知の熱流束条件下で、前記一組の温度センサから一組の試験的温度測定値を取得し、前記一組の熱流束センサから一組の試験的熱流束測定値を取得し、obtaining a set of trial temperature measurements from the set of temperature sensors and taking a set of trial heat flux measurements from the set of heat flux sensors under unknown heat flux conditions;
前記一組の試験的熱流束測定値および識別された熱流束－温度変動関係に基づいて、前記一組の試験的温度測定値を調整するadjusting the set of tentative temperature measurements based on the set of tentative heat flux measurements and the identified heat flux-temperature variation relationship;
ように構成されたプログラム命令の組を実行するように構成される、システム。A system configured to execute a set of program instructions configured to:
調整された前記一組の試験的温度測定値を前記プロセス条件計測ウェハの１つまたは複数の測定位置にマッピングするmapping the set of adjusted trial temperature measurements to one or more measurement locations of the process condition measurement wafer;
ように構成される請求項３３に記載のシステム。34. The system of claim 33, configured to:
調整された前記一組の試験的温度測定値および１つまたは複数の補間関数に基づいて、１つまたは複数の測定位置間の位置における一組の温度値を補間するinterpolating a set of temperature values at locations between one or more measurement locations based on the set of adjusted trial temperature measurements and one or more interpolation functions;
ように構成される請求項３３に記載のシステム。34. The system of claim 33, configured to:
恒温条件下で取得された前記一組の温度測定値および前記一組の熱流束測定値をベースラインとして設定するステップsetting the set of temperature measurements and the set of heat flux measurements taken under isothermal conditions as a baseline;
を含む請求項３３に記載のシステム。34. The system of claim 33, comprising:
をさらに含む請求項３３に記載のシステム。34. The system of claim 33, further comprising:
一組の温度センサおよび一組の熱流束センサを含むプロセス条件計測ウェハと、a process condition metrology wafer including a set of temperature sensors and a set of heat flux sensors;
前記一組の温度センサおよび前記一組の熱流束センサに通信可能に結合された１個または複数個のプロセッサであって、one or more processors communicatively coupled to the set of temperature sensors and the set of heat flux sensors, comprising:
恒温条件下で、前記一組の温度センサから一組の温度測定値を取得し、前記一組の熱流束センサから一組の熱流束測定値を取得し、obtaining a set of temperature measurements from the set of temperature sensors and a set of heat flux measurements from the set of heat flux sensors under isothermal conditions;
恒温条件下で取得された前記一組の温度測定値および前記一組の熱流束測定値を較正し、calibrating the set of temperature measurements and the set of heat flux measurements taken under isothermal conditions;
既知の熱流束の適用中に、前記一組の温度センサから一組の付加的温度測定値を取得し、前記一組の熱流束センサから一組の付加的熱流束測定値を取得し、obtaining a set of additional temperature measurements from the set of temperature sensors and obtaining a set of additional heat flux measurements from the set of heat flux sensors during application of a known heat flux;
既知の熱流束の適用中に前記一組の温度センサにわたる温度変動を識別し、identifying temperature variations across the set of temperature sensors during application of a known heat flux;
既知の熱流束を前記一組の温度センサの識別された温度変動と相関させることによって、熱流束－温度変動関係を識別し、identifying a heat flux-temperature variation relationship by correlating the known heat flux with the identified temperature variation of the set of temperature sensors;
未知の熱流束条件下で、前記一組の温度センサから一組の試験的温度測定値を取得し、前記一組の熱流束センサから一組の試験的熱流束測定値を取得し、obtaining a set of trial temperature measurements from the set of temperature sensors and taking a set of trial heat flux measurements from the set of heat flux sensors under unknown heat flux conditions;
前記一組の試験的熱流束測定値および識別された前記熱流束－温度変動関係に基づいて、前記一組の試験的温度測定値を調整する、adjusting the set of tentative temperature measurements based on the set of tentative heat flux measurements and the identified heat flux-temperature variation relationship;
ように構成されたプログラム命令の組を実行するように構成される１個または複数個のプロセッサと、one or more processors configured to execute a set of program instructions configured to
を含むシステム。system including.
調整された前記一組の試験的温度測定値を前記プロセス条件計測ウェハの１つまたは複数の測定位置にマッピングするmapping the set of adjusted trial temperature measurements to one or more measurement locations of the process condition measurement wafer;
請求項３９に記載のシステム。 40. A system according to claim 39.
調整された前記一組の試験的温度測定値および１つまたは複数の補間関数に基づいて、１つまたは複数の測定位置間の位置における一組の温度値を補間するinterpolating a set of temperature values at locations between one or more measurement locations based on the set of adjusted trial temperature measurements and one or more interpolation functions;
請求項３９に記載のシステム。40. A system according to claim 39.
恒温条件下で取得された前記一組の温度測定値および前記一組の熱流束測定値をベースラインとして設定するステップsetting the set of temperature measurements and the set of heat flux measurements taken under isothermal conditions as a baseline;
を含む請求項３９に記載のシステム。40. The system of claim 39, comprising:
をさらに含む請求項３９に記載のシステム。40. The system of Claim 39, further comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2023200810A JP2024019227A (en) | 2018-09-06 | 2023-11-28 | Systems and methods for process condition measurement wafer assembly |
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201862727633P | 2018-09-06 | 2018-09-06 | |
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| PCT/US2019/049833 WO2020051388A1 (en) | 2018-09-06 | 2019-09-06 | Process temperature measurement device fabrication techniques and methods of calibration and data interpolation of the same |
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| KR102505963B1 (en) * | 2020-10-30 | 2023-03-03 | 이트론 주식회사 | Plasma Sensor Mounted Wafer And Manufacturing Method Thereof |
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| JP3905330B2 (en) | 2001-05-30 | 2007-04-18 | 株式会社神戸製鋼所 | Temperature measuring device and temperature measuring method using the same |
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| JP5476114B2 (en) | 2009-12-18 | 2014-04-23 | 東京エレクトロン株式会社 | Temperature measuring device |
| US9134186B2 (en) * | 2011-02-03 | 2015-09-15 | Kla-Tencor Corporation | Process condition measuring device (PCMD) and method for measuring process conditions in a workpiece processing tool configured to process production workpieces |
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| KR102059716B1 (en) * | 2013-05-30 | 2019-12-26 | 케이엘에이 코포레이션 | Method and system for measuring heat flux |
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| US9823121B2 (en) * | 2014-10-14 | 2017-11-21 | Kla-Tencor Corporation | Method and system for measuring radiation and temperature exposure of wafers along a fabrication process line |
| US10444103B2 (en) | 2014-11-11 | 2019-10-15 | Ams International Ag | Method and apparatus for calibrating pressure sensor integrated circuit devices |
| US9673150B2 (en) * | 2014-12-16 | 2017-06-06 | Nxp Usa, Inc. | EMI/RFI shielding for semiconductor device packages |
| US9659985B2 (en) * | 2015-02-17 | 2017-05-23 | Taiwan Semiconductor Manufacturing Company Ltd. | Integrated circuit and image sensing device having metal shielding layer and related fabricating method |
| KR20180093966A (en) | 2015-12-10 | 2018-08-22 | 아이오니어 엘엘씨 | Apparatus and method for determining parameters of a process operation |
| US11150140B2 (en) | 2016-02-02 | 2021-10-19 | Kla Corporation | Instrumented substrate apparatus for acquiring measurement parameters in high temperature process applications |
| CN107507823B (en) * | 2016-06-14 | 2022-12-20 | 三星电子株式会社 | Semiconductor package and method for manufacturing semiconductor package |
| US10460966B2 (en) | 2016-06-15 | 2019-10-29 | Kla-Tencor Corporation | Encapsulated instrumented substrate apparatus for acquiring measurement parameters in high temperature process applications |
| KR101820675B1 (en) | 2017-04-06 | 2018-01-24 | 한국표준과학연구원 | Multi-layered resistive type multi-point temperature measuring wafer sensor and method for fabricating the same |
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