JPWO2020046495A5 - - Google Patents

Claims (49)

An analog neuromorphic memory system comprising :
a vector matrix multiplication array comprising an array of memory cells;
a temperature compensation block for continuously modifying the slope of the current-voltage characteristic curve of the memory cells of the array of memory cells as the operating temperature of the memory cells of the array of memory cells changes; The temperature compensation block is
a temperature sensor for producing an output indicative of said operating temperature;
a controller for generating one or more control signals in response to the output of the temperature sensor;
and one or more adjustable devices for generating temperature compensated voltages in response to the one or more control signals. 2. The system of claim 1, wherein weights in said vector-matrix multiplication array are implemented by said memory cells. 2. The system of claim 1, wherein weights in said vector-matrix multiplication array are implemented by differential cells. 2. The system of claim 1, wherein weights in said vector matrix multiplication array are implemented by a pair of blended memory cells. each of the memory cells of the array of memory cells is a flash memory cell, the one or more adjustable devices comprise one or more adjustable current sources, and the one or more adjustable Each of the current sources is regulated by one of the one or more control signals and coupled to a resistor, and the temperature compensated voltage is controlled by the one or more adjustable current sources and the resistor. 2. The system of claim 1, wherein a is generated at a node between and applied to said flash memory cell to modify the slope of said current-voltage characteristic curve of said flash memory cell. 6. The system of claim 5, wherein said temperature compensated voltage is applied to a control gate terminal of said flash memory cell. 6. The system of claim 5, wherein said temperature compensated voltage is applied to an erase gate terminal of said flash memory cell. 6. The system of claim 5, wherein said temperature compensated voltage is applied to a source line terminal of said flash memory cell. 6. The system of claim 5, wherein said temperature compensated voltage is applied to a bitline terminal of said flash memory cell. 6. The system of claim 5, wherein said flash memory cells are split gate flash memory cells. 6. The system of claim 5, wherein said flash memory cells are stacked gate flash memory cells. a leakage reduction block for modifying bias voltages applied to terminals of the memory cells of the array of memory cells to reduce leakage as the operating temperature of the memory cells of the array of memory cells changes; 2. The system of claim 1, further comprising: An analog neuromorphic memory system comprising :
a vector matrix multiplication system comprising an array of memory cells;
a temperature compensation block for discontinuously modifying the current-voltage characteristic curve of the memory cells of the array of memory cells as the level of operating temperature of the memory cells of the array of memory cells changes. , an analog neuromorphic memory system. 14. The system of claim 13, wherein weights in said vector-matrix multiplication system are implemented by said memory cells. 14. The system of claim 13, wherein weights in said vector-matrix multiplication system are implemented by differential cells. 14. The system of claim 13, wherein weights in said vector matrix multiplication system are implemented by blend memory cells. each of the memory cells of the array of memory cells being a flash memory cell, the temperature compensation block comprising:
a temperature sensor for producing an output indicative of said operating temperature;
a controller for generating one or more control bits in response to the output of the temperature sensor;
a plurality of current sources, each current source selectively coupled to the resistor via a switch, each switch controlled by one of the control bits. ,
14. The system of claim 13, wherein the voltage generated at one end of said resistor is applied to said flash memory cell to modify the slope of said current-voltage characteristic curve of said flash memory cell. 14. The system of claim 13, wherein modifying comprises modifying a slope of a current-voltage characteristic curve of a flash memory cell. 14. The system of claim 13, wherein said memory cells are split gate flash memory cells. 14. The system of claim 13, wherein the memory cells are stacked gate flash memory cells. The temperature compensation block is
a temperature sensor for producing an output indicative of said operating temperature;
a controller for generating one or more control bits in response to the output of the temperature sensor;
An amplifier circuit comprising a plurality of registers, each resistor selectively coupled to said amplifier via a switch, each switch controlled by one of said control bits. a circuit;
14. The system of claim 13, wherein the voltage produced at the output of said amplifier is applied to said memory cell to modify the slope of said current-voltage characteristic curve of said memory cell. 22. The system of claim 21, wherein modifying comprises modifying the slope of the current-voltage characteristic curve of the memory cell. 22. The system of claim 21, wherein said memory cells are split gate flash memory cells. 22. The system of claim 21, wherein said memory cells are stacked gate flash memory cells. a leakage reduction block for modifying bias voltages applied to terminals of the memory cells of the array of memory cells to reduce leakage as the operating temperature of the memory cells of the array of memory cells changes; 14. The system of claim 13, further comprising: A method of performing temperature compensation in an analog neuromorphic memory system comprising a plurality of vector matrix multiplying arrays, each vector matrix multiplying array comprising an array of memory cells, the method comprising:
continuously modifying, by a temperature compensation block, the slope of the current-voltage characteristic curve of the memory cells of the array of memory cells as the operating temperature of the memory cells of the array of memory cells changes, comprising: The temperature compensation block includes a temperature sensor for producing an output indicative of operating temperature, a controller for producing one or more control signals in response to the output of the temperature sensor, and the one or more controls. and one or more adjustable devices for generating a temperature compensated voltage in response to the signal. 27. The method of claim 26, wherein weights in said vector-matrix multiplication array are implemented by memory cells. 27. The method of claim 26, wherein weights in said vector matrix multiplication array are implemented by differential cells. 27. The method of claim 26, wherein weights in said vector-matrix multiplication array are implemented by a pair of blended memory cells. each of the memory cells of the array of memory cells is a flash memory cell, the one or more adjustable devices comprise one or more adjustable current sources, and the one or more adjustable each of the current sources being regulated by one of the one or more control signals and coupled to a resistor, the temperature compensated voltage being between the one or more adjustable current sources and the resistor; and applied to said flash memory cell to modify the slope of said current-voltage characteristic curve of said flash memory cell. 31. The method of claim 30, wherein said temperature compensated voltage is applied to a control gate terminal of said flash memory cell. 31. The method of claim 30, wherein said temperature compensated voltage is applied to an erase gate terminal of said flash memory cell. 31. The method of claim 30, wherein said temperature compensated voltage is applied to a source line terminal of said flash memory cell. 31. The method of claim 30, wherein said temperature compensated voltage is applied to a bitline terminal of said flash memory cell. 31. The method of claim 30, wherein said flash memory cells are split gate flash memory cells. 31. The method of claim 30, wherein said flash memory cells are stacked gate flash memory cells. further comprising modifying bias voltages applied to terminals of the memory cells of the array of memory cells to reduce leakage as the operating temperature of the memory cells of the array of memory cells changes. 27. The method of claim 26. A method of performing temperature compensation in an analog neuromorphic memory system comprising a plurality of vector matrix multiplication systems, each vector matrix multiplication system comprising an array of memory cells, the method comprising:
modifying discontinuously by a temperature compensation block for a current-voltage characteristic curve of the memory cells of the array of memory cells as the level of operating temperature of the memory cells of the array of memory cells changes. ,Method. 39. The method of claim 38, wherein weights in said vector-matrix multiplication system are implemented by said memory cells. 39. The method of claim 38, wherein weights in the vector-matrix multiplication system are implemented by differential cells. 39. The method of claim 38, wherein weights in said vector matrix multiplication system are implemented by blend memory cells. Each of the memory cells of the array of memory cells is a flash memory cell, the temperature compensation block includes a temperature sensor for producing an output indicative of the operating temperature, and responsive to the output of the temperature sensor. a controller for generating one or more control bits; and a plurality of current sources, each current source selectively coupled to the register via a switch, each switch for controlling one of said control bits. and a plurality of current sources controlled by one, wherein the voltage generated at one end of the resistor is applied to the flash memory cell to modify the slope of the current-voltage characteristic curve of the flash memory cell. 39. The method of claim 38. 39. The system of claim 38, wherein modifying comprises modifying a slope of a current-voltage characteristic curve of a flash memory cell. 39. The method of claim 38, wherein said memory cells are split gate flash memory cells. 39. The method of claim 38, wherein said memory cells are stacked gate flash memory cells. The temperature compensation block comprises a temperature sensor for producing an output indicative of the operating temperature, a controller for producing one or more control bits in response to the output of the temperature sensor, and a plurality of registers. an amplifier circuit, each register selectively coupled to the amplifier via a switch, each switch controlled by one of the control bits; 39. The method of claim 38, wherein the voltage produced at the output of an amplifier is applied to the memory cell to modify the slope of the current-voltage characteristic curve of the memory cell. 47. The method of claim 46, wherein said memory cells are split gate flash memory cells. 47. The method of claim 46, wherein said memory cells are stacked gate flash memory cells. a leakage reduction block for modifying bias voltages applied to terminals of the memory cells of the array of memory cells to reduce leakage as the operating temperature of the memory cells of the array of memory cells changes;
39. The method of claim 38, further comprising: