JPWO2019186750A1 - Solid-state image sensor - Google Patents

Abstract

The solid-state image sensor (100) has a plurality of pixel regions (1 to 4) arranged in an array on the substrate (7), and each of the plurality of pixel regions (1 to 4) photoelectrically receives received light. The first pixel to be converted and the plurality of pixel regions (1 to 4) includes a first photoelectric conversion layer (15a) that photoelectrically converts light in the first wavelength region and multiplys the charge by avalanche multiplication. A second pixel comprising a region (1) and a second photoelectric conversion layer (15b) that photoelectrically converts light in a second wavelength region different from the first wavelength region and multiplys the charge by avalanche multiplication. A plurality of pixel regions (1 to 4) including a region (2) are separated by an element separation region (5).

Description

The present disclosure relates to a solid-state image sensor.

As a solid-state image sensor having high spectral sensitivity characteristics for near-infrared light (hereinafter referred to as IR light), a solid-state image sensor using a compound semiconductor is known (see, for example, Patent Document 1).

The solid-state image sensor described in Patent Document 1 is formed on a semiconductor substrate (InP substrate), and has a first light receiving layer made of a single-layer compound semiconductor InGaAsN and light having a longer wavelength side than the first light receiving layer. It includes a second light receiving layer made of a quantum well structure (InP / InAsP) having high absorption efficiency.

Japanese Unexamined Patent Publication No. 2008-153311

One of the problems with solid-state image sensors using such compound semiconductors is the high wafer cost. In addition, the process cost for manufacturing the solid-state image sensor is also high. Therefore, a solid-state image sensor has been proposed in which a silicon substrate with low wafer cost and process cost is used and a depletion layer is designed to be thick in order to secure the detection efficiency of IR light.

However, the solid-state image sensor having such a structure is premised on high-voltage drive, and while suppressing power consumption, both IR light and visible light (particularly blue light having a short wavelength) can be detected efficiently. It becomes difficult to improve.

An object of the present disclosure is to provide a solid-state image sensor that improves the detection efficiency of different wavelengths.

The solid-state image sensor according to the present disclosure has a plurality of pixel regions arranged in an array on a substrate, each of the plurality of pixel regions photomultipliers the received light, and the plurality of pixel regions are the first. A first pixel region including a first photoelectric conversion layer that photomultipliers light in one wavelength region and multipliers the charge by avalanche multiplication, and a second wavelength region different from the first wavelength region. A second pixel region including a second photoelectric conversion layer that photomultipliers light and multipliers the charge by avalanche multiplication is included, and the plurality of pixel regions are separated by an element separation region.

According to the solid-state image sensor according to one aspect of the present disclosure, it is possible to improve the detection efficiency of different wavelengths.

FIG. 1 is a top view showing the structure of the solid-state image sensor according to the embodiment of the present disclosure. FIG. 2 is a cross-sectional view showing a cross section of the solid-state image sensor according to the embodiment of the present disclosure in line II-II of FIG. FIG. 3 is a cross-sectional view showing a cross section of the solid-state image sensor according to the embodiment of the present disclosure in lines III-III of FIG. FIG. 4 is a cross-sectional view showing a cross section of the solid-state image sensor according to the embodiment of the present disclosure in the IV-IV line of FIG. FIG. 5A is a cross-sectional view for explaining a first example of the method for manufacturing a solid-state image sensor according to the embodiment of the present disclosure in line II-II of FIG. FIG. 5B is a cross-sectional view for explaining a first example of the method for manufacturing a solid-state image sensor according to the embodiment of the present disclosure in lines III-III of FIG. FIG. 5C is a cross-sectional view for explaining a first example of the method for manufacturing a solid-state image sensor according to the embodiment of the present disclosure in the IV-IV line of FIG. FIG. 6A is a cross-sectional view for explaining a second example of the method for manufacturing a solid-state image sensor according to the embodiment of the present disclosure in line II-II of FIG. FIG. 6B is a cross-sectional view for explaining a second example of the method for manufacturing a solid-state image sensor according to the embodiment of the present disclosure according to lines III-III of FIG. FIG. 6C is a cross-sectional view for explaining a second example of the method for manufacturing a solid-state image sensor according to the embodiment of the present disclosure in the IV-IV line of FIG. FIG. 7 is a diagram illustrating a trench separation structure which is a first example of an element separation region included in the solid-state image sensor according to the embodiment of the present disclosure. FIG. 8 is a diagram illustrating an injection separation structure which is a second example of an element separation region included in the solid-state image sensor according to the embodiment of the present disclosure.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. It should be noted that all of the embodiments described below show a specific example of the present disclosure. The numerical values, shapes, materials, components, arrangement positions and connection forms of the components, steps, the order of steps, etc. shown in the following embodiments are examples, and are not intended to limit the present disclosure. This disclosure is limited only by the scope of claims. Therefore, among the components in the following embodiments, the components not described in the independent claims indicating the highest level concept of the present disclosure will be described.

It should be noted that each figure is a schematic view and is not necessarily exactly shown. In addition, duplicate explanations for substantially the same configuration may be omitted.

Further, in the present specification, the terms "upper" and "lower" do not refer to the upward direction (vertically upward) and the downward direction (vertically downward) in absolute spatial recognition. Also, the terms "upper" and "lower" are used not only when the two components are spaced apart from each other and another component exists between the two components, but also when the two components It also applies when the two components are placed in close contact with each other and touch each other.

Further, in the present specification, the “top surface” refers to the light receiving side of the solid-state image sensor.

Further, the “planar view” refers to a case where the solid-state image sensor is viewed from the light receiving surface side.

Further, in the present specification, the "depth" or "thickness" indicates the length of the main surface of the substrate in the normal direction.

(Embodiment)
[Constitution]
First, the configuration of the solid-state image sensor according to the present embodiment will be described.

FIG. 1 is a top view showing the structure of the solid-state image sensor 100 according to the embodiment of the present disclosure.

The solid-state image sensor 100 is an APD (Avalanche Photodiode) having a structure in which an electric charge is multiplied by an avalanche multiplier. Specifically, the solid-state image sensor 100 has a plurality of pixel regions arranged in an array on a substrate. In addition, each of the plurality of pixel regions photoelectrically converts the received light. The plurality of pixel regions are different from the first wavelength region and the first pixel region including the first photomultiplier layer that photomultipliers the light in the first wavelength region and multiplys the charge by avalanche multiplication. Includes a second pixel region that includes a second photomultiplier layer that photomultipliers light in the second wavelength region and multiplys the charge by avalanche multiplication. For example, a color filter (not shown) that transmits light of a specific wavelength is arranged on the light receiving surface side of the solid-state image sensor 100.

Further, the plurality of pixel regions are separated by the element separation region 5. For example, the first wavelength region is a region on the longer wavelength side than the second wavelength region. Specifically, the light in the first wavelength region is near-infrared light, and the light in the second wavelength region is visible light.

Further, in a plan view, the area of the first pixel region is smaller than that of the second pixel region.

In the present embodiment, the solid-state image sensor 100 is composed of four avalanche multiplication regions. Specifically, the solid-state image sensor 100 includes a pixel region (first pixel region) 1 which is an avalanche magnification region for near-infrared light (IR light) and red light (R light) of visible light. The pixel area (second pixel area) 2 which is the avalanche magnification area for the visible light, and the pixel area (third pixel area) 3 which is the avalanche magnification area for the green (G light) of the visible light. It has a pixel region (fourth pixel region) 4, which is an avalanche multiplication region for blue light (B light) of visible light.

Each of the pixel regions 1 to 4 is electrically separated by the element separation region 5.

The element separation region 5 is a separation portion that electrically separates each pixel region formed by the trench separation method or the injection separation method. As the element separation region 5 formed by the trench separation method, for example, a DTI (Deep Trench Isolation) structure is adopted.

Further, the element separation region 5 around the pixel region 1 has a thicker separation width (that is, a width in a plan view) as a measure against color mixing, as compared with those around the other pixel regions 2 to 4.

Details of the manufacturing method of the element separation region 5 will be described later.

Further, the transistor 6 is arranged in the region inside the element separation region 5 existing between the pixel region 1 and the pixel region 2. Specifically, the transistor 6 is provided between the plurality of pixel regions 1 to 4 in a plan view. Further, the transistor 6 is surrounded by an element separation region in a plan view.

The transistor 6 is a transistor for reading out the electric charge generated by photoelectric conversion in at least one of the plurality of pixel regions 1 to 4. The transistor 6 is, for example, a transistor such as a read transistor, a reset transistor, or an amplification transistor.

In FIG. 1, nine transistors 6 are formed for the four pixel regions 1 to 4, but the number of transistors 6 for the pixel region is such that at least one transistor is formed for one pixel region. It suffices, and is not particularly limited.

FIG. 2 is a cross-sectional view showing a cross section of the solid-state image sensor 100 in line II-II of FIG.

The solid-state image sensor 100 includes a Psub substrate (board) 7, a P- layer 8, a P + layer 9, an N + layer 10a and 10b, and a control circuit 17.

The Psub substrate 7 is a second conductive type semiconductor substrate. The Psub substrate 7 is, for example, a P-type silicon substrate.

The P-layer 8 epitaxially grown on the main surface 7a of the Psub substrate 7 is an APD multiplying region in each of the pixel regions 1 to 4, and is a second conductive type semiconductor layer.

The P + layer 9 is a second conductive type semiconductor layer having a higher impurity concentration than the P− layer 8, and is, for example, a P type layer.

The N + layers 10a and 10b are first conductive type semiconductor layers, for example, N type layers.

In the following, the first conductive type will be described as N type, and the second conductive type will be described as P type. The solid-state image sensor 100 may have a structure in which the P-type and the N-type described below are all inverted. That is, the first conductive type may be P type, and the second conductive type may be N type.

The light received by the N + layers 10a and 10b, the P-layer 8 and the P + layer 9 is photoelectrically converted, and the photoelectrically converted charges are read out to the transistor 6.

Here, "+ (plus)" and "-(minus)" indicate a relative difference in the concentration of impurities. The impurity concentration of each layer, P + layer 9 is 1E17 cm ^-3 or more, P- layer 8 is 1E15 cm ^-3, N + layer 10a, 10b is 1E17 cm ^-3 is exemplified. The impurity concentration of each layer is not particularly limited. The N + layer 10c (see FIG. 3) and the N + layer 10d (see FIG. 4) described below are also N-type semiconductor layers, and the impurity concentration is also exemplified as ^1E17cm-3.

Each layer of the P-layer 8, the P + layer 9, and the N + layers 10a and 10b is made of the same material as the Psub substrate 7, and silicon is exemplified.

The pixel region 1 is, for example, a region that receives near-infrared light (that is, IR light, for example, light having a wavelength of 700 nm or more and 1100 nm or less) and performs photoelectric conversion. It is composed of a second semiconductor region) 8a and an N + layer (first semiconductor region) 10a.

The P-layer 8a epitaxially grown on the Psub substrate 7 is a part of the P-layer 8 and is an avalanche multiplication region in the pixel region 1.

The P + layer 9a is a part of the P + layer 9 and is a P-type layer having a higher impurity concentration than the P- layer 8a.

The N + layer 10a is an N-type layer.

That is, the P-layer 8a and the P-layer 8 and the P + layer 9a and the Psub substrate 7 are the same constituent elements (that is, the same material), but whether or not they are the constituent elements of the pixel region 1. The notation is changed due to the difference in.

The photoelectric conversion layer (first photoelectric conversion layer) 15a is a layer that photoelectrically converts the received light by the N + layer 10a and the P− layer 8a. The electric charge generated by photoelectric conversion by the photoelectric conversion layer 15a is read out by one of the plurality of transistors 6.

The pixel region 2 is, for example, a region that receives red light (that is, R light, for example, light having a wavelength of 600 nm or more and less than 700 nm) and performs photoelectric conversion, and is a P + layer 9b and a P- layer (fourth layer). (Semiconductor region) 8b and N + layer (third semiconductor region) 10b.

The P-layer 8b epitaxially grown on the Psub substrate 7 is a part of the P-layer 8 and is an avalanche multiplication region in the pixel region 2.

The P + layer 9b is a part of the P + layer 9 and is a P-type layer having a higher impurity concentration than the P- layer 8b.

The N + layer 10b is an N-type layer.

That is, the P-layer 8b and the P-layer 8 and the P + layer 9b and the Psub substrate 7 are the same constituent elements (that is, the same material), but whether or not they are the constituent elements of the pixel region 2. The notation is changed due to the difference in.

The photoelectric conversion layer (second photoelectric conversion layer) 15b is a layer that photoelectrically converts the received light by the N + layer 10b and the P- layer 8b. The electric charge generated by photoelectric conversion by the photoelectric conversion layer 15b is read out by one of the plurality of transistors 6.

Here, the thickness of the P-layer 8a and the thickness of the P-layer 8b are different. Specifically, the thickness (depth) of the P-layer 8a is formed thicker (deeper) than the thickness (depth) of the P-layer 8b. That is, the P-layer 8a that photoelectrically converts the light on the longer wavelength region side is thicker than the P-layer 8b.

The thickness of the P-layer 8a is, for example, 10 μm, and the thickness of the P-layer 8b is, for example, 5 μm. The thickness of each layer is not limited to these thicknesses. The pixel region 1 is a diffusion layer (that is, a P-layer) which is an avalanche multiplication region so that the depletion layer width formed between the N + layer 10a and the P-layer 8a becomes thicker in order to ensure detection efficiency. It is important to form 8a) thickly.

Further, in a plan view, the width of the element separation region 5 between the pixel region 1 and the pixel region 2 is set in order to prevent color mixing between the pixel region 1 and the pixel region 2 and to secure an region for arranging the transistor 6. It is formed wider than the width of the element separation region 5 between the pixel regions 2 to 4.

The control circuit 17 is a circuit for applying a variable voltage to the Psub board 7. In other words, the control circuit 17 has a configuration in which different voltages can be applied to the Psub substrate 7. Specifically, the control circuit 17 is realized by a power supply circuit including a converter and the like. For example, the control circuit 17 generates a predetermined voltage based on the electric power received from an external power source such as a commercial power source, and applies the generated voltage to the Psub substrate 7. The voltage applied by the control circuit 17 determines whether or not avalanche multiplication occurs in each of the pixel regions 1 to 4.

In each drawing other than FIG. 2, the control circuit 17 is not shown. Further, in FIGS. 3 to 8 described later, the description of the transistor 6 is omitted.

FIG. 3 is a cross-sectional view showing a cross section of the solid-state image sensor 100 in lines III-III of FIG.

The pixel region 3 is, for example, a region that receives green light (that is, G light, for example, light having a wavelength of 500 nm or more and less than 600 nm) and performs photoelectric conversion, and is a P + layer 9c and a P- layer (eighth). (Semiconductor region) 8c and N + layer (seventh semiconductor region) 10c.

The P-layer 8c epitaxially grown on the Psub substrate 7 is a part of the P-layer 8 and is an avalanche multiplication region in the pixel region 3.

The P + layer 9c is a part of the P + layer 9 and is a P-type layer having a higher impurity concentration than the P- layer 8c.

The N + layer 10c is an N-type layer.

That is, the P-layer 8c and the P-layer 8 and the P + layer 9c and the Psub substrate 7 are the same constituent elements (that is, the same material), but whether or not they are the constituent elements of the pixel region 3. The notation is changed due to the difference in.

Further, the thickness of the P-layer 8a is formed to be thicker than that of the P-layer 8c. That is, the P-layer 8a that photoelectrically converts the light on the longer wavelength region side is thicker than the P-layer 8c.

The thickness of the P-layer 8c is exemplified by 3 μm, but the thickness is not limited to this.

The photoelectric conversion layer (third photoelectric conversion layer) 15c is a layer that photoelectrically converts the received light by the N + layer 10c and the P− layer 8c. The electric charge generated by photoelectric conversion by the photoelectric conversion layer 15c is read out by one of the plurality of transistors 6.

FIG. 4 is a cross-sectional view showing a cross section of the solid-state image sensor 100 in line IV-IV of FIG.

The pixel region 4 is, for example, a region that receives blue light (that is, B light, for example, light having a wavelength of 400 nm or more and less than 500 nm) and performs photoelectric conversion, and is a P + layer 9d and a P− layer (10th layer). (Semiconductor region) 8d and N + layer (9th semiconductor region) 10d.

The P-layer 8d epitaxially grown on the Psub substrate 7 is a part of the P-layer 8 and is an avalanche multiplication region in the pixel region 4.

The P + layer 9d is a part of the P + layer 9 and is a P-type layer having a higher impurity concentration than the P- layer 8d.

The N + layer 10d is an N-type layer.

That is, the P-layer 8d and the P-layer 8 and the P + layer 9d and the Psub substrate 7 are the same constituent elements (that is, the same material), but whether or not they are the constituent elements of the pixel region 3. The notation is changed due to the difference in.

Further, the thickness of the P-layer 8a is formed to be thicker than that of the P-layer 8d. That is, the P-layer 8a that photoelectrically converts the light on the longer wavelength region side is thicker than the P-layer 8d.

The thickness of the P-layer 8d is exemplified by 1 μm, but the thickness is not limited to this.

The photoelectric conversion layer (fourth photoelectric conversion layer) 15d is a layer that photoelectrically converts the received light by the N + layer 10d and the P− layer 8d. The electric charge generated by photoelectric conversion by the photoelectric conversion layer 15d is read out by one of the plurality of transistors 6.

Further, as the width of the element separation region 5 arranged between the pixel regions 1 to 4 in the plan view, for example, the width of the element separation region 5 in the region between the pixel region 1 and the pixel region 2 is 2 μm. The width of the element separation region 5 in the region between the pixel region 1 and the pixel region 3 and the width of the element separation region 5 in the region between the pixel region 1 and the pixel region 4 are 1.0 μm. The width of the element separation region 5 in the region between the pixel region 2 and the pixel region 3 and the width of the element separation region 5 in the region between the pixel region 2 and the pixel region 4 are 0.5 μm. .. The width of the element separation region 5 in a plan view is not limited to these widths.

Further, the width of the element separation region 5 in the plan view is a value to be set according to the color mixing resistance of each pixel region 1 to 4 and the target value of the detection efficiency. As the width of the element separation region 5 in the plan view increases, the color mixing resistance increases, but the areas of the pixel regions 1 to 4 are relatively reduced, resulting in a decrease in detection efficiency.

[Production method]
Subsequently, a method for manufacturing the solid-state image sensor 100 will be described.

<First example>
First, a first example of a method for manufacturing the solid-state image sensor 100 will be described in detail with reference to FIGS. 5A to 5C.

FIG. 5A is a cross-sectional view for explaining a first example of a method for manufacturing the solid-state image sensor 100 in line II-II of FIG. FIG. 5B is a cross-sectional view for explaining a first example of a method of manufacturing the solid-state image sensor 100 in lines III-III of FIG. FIG. 5C is a cross-sectional view for explaining a first example of a method of manufacturing the solid-state image sensor 100 in the IV-IV line of FIG.

In addition, (a) to (e) of FIGS. 5A to 5C will be described as being common steps in FIGS. 5A to 5C, that is, the same steps in the manufacturing process.

First, as shown in (a) of FIGS. 5A to 5C, an element separation region 5 is formed on the Psub substrate 7 in which the P-layer 8 is epitaxially grown on the Psub substrate 7.

Next, as shown in (b) of FIGS. 5A to 5C, the avalanche multiplication region for R light, the APD multiplication region for G light, and the avalanche multiplication region for B light should be formed. Only selectively B (boron) ultra-high energy injection is performed to form a P + layer 9 on the Psub substrate 7. For example, the P + layer 9 is formed by performing multi-stage injection of 5MeV to 8MeV (in 1MeV increments), 5E12cm- ^2.

Next, as shown in (c) of FIGS. 5A to 5C, the ultra-high boron is selectively formed only in the region where the avalanche multiplication region for G light and the avalanche multiplication region for B light should be formed. By injecting energy, the P + layer 91 is formed on the P + layer 9. For example, the P + layer 91 is formed by performing multi-stage injection of 3MeV to 4MeV (in 1MeV increments), 5E12cm- ^2.

Next, as shown in (d) of FIGS. 5A to 5C, the P + layer is selectively injected with ultra-high energy of boron only in the region where the avalanche multiplication region for B light should be formed. A P + layer 92 is formed on the 91. For example, the P + layer 92 is formed by performing multi-stage injection of ^{1 MeV to 2} MeV (in 1 MeV increments), 5E12 cm-2.

Finally, as shown in (e) of FIGS. 5A-5C, as (arsenic) injection is selectively performed only in the region where each avalanche multiplying region should be formed. For example, by injecting 150 keV, 2E 12 cm- ² , N + layers 10a to 10d are formed on the surface of the P-layer 8. For each avalanche multiplication region, the region sandwiched between the N + layer and the P + layer is the P- layer.

The impurity concentration of the P-layer is defined by the concentration of the atmosphere at the time of epitaxial growth, but if it is desired to adjust the impurity concentration individually, the amount of boron injected may be changed individually.

According to this manufacturing method, the P-layer 8a of the pixel region 1 for IR light can be formed to be the thickest, and the P-layer 8a for R light, the P-layer 8b for G light, and B light can be formed. The P-layer 8 can be formed thin (shallow) in the order of the P-layer 8c. Specifically, the thicknesses of the P-layer 8a, the P-layer 8b, the P-layer 8c, and the P-layer 8d can be formed to be about 10 μm, 5 μm, 3 μm, and 1 μm, respectively.

According to the first example of the manufacturing method of the solid-state image sensor 100, it is possible to secure and improve the detection efficiency for each of IR light and visible light (specifically, R light, G light, and B light). It becomes. For example, at the time of high voltage drive in which a high voltage is applied to the Psub substrate 7 by the control circuit 17 (see FIG. 2), the depletion layer can be formed thicker with respect to IR light, so that the detection efficiency can be improved.

Further, for visible light (particularly B light), the detection efficiency can be expected to be improved by the avalanche multiplication region. Further, in a situation where the detection efficiency of IR light is not required, the voltage applied to the Psub substrate 7 is lowered (during low voltage drive) to suppress power consumption and for visible light including B light. However, the detection efficiency can be improved.

<Second example>
Subsequently, a manufacturing method having a form different from the solid-state imaging device 100 manufacturing method described in the first example will be described in detail with reference to FIGS. 6A to 6C. FIG. 6A is a cross-sectional view for explaining a second example of a method of manufacturing the solid-state image sensor 100 in line II-II of FIG. FIG. 6B is a cross-sectional view for explaining a second example of the method of manufacturing the solid-state image sensor 100 in lines III-III of FIG. FIG. 6C is a cross-sectional view for explaining a second example of a method of manufacturing the solid-state image sensor 100 in the IV-IV line of FIG.

It should be noted that (a) to (e) of FIGS. 6A to 6C are described as being common steps in FIGS. 6A to 6C, that is, the same steps in the manufacturing process.

First, as shown in (a) of FIGS. 6A to 6C, the avalanche multiplication region for R light and the avalanche multiplication region for G light are used for the Psub board 7 in which the P-layer 8 is epigrown on the Psub board 7. The P + layer 9 is formed on the Psub substrate 7 by selectively injecting ultra-high energy of boron only in the avalanche multiplication region and the region where the avalanche multiplication region for B light should be formed. For example, the P + layer 9 is formed by performing multi-stage injection of 1 MeV to 4 MeV (in 1 MeV increments) 5E12 cm- ^2.

Next, as shown in (b) of FIGS. 6A to 6C, the P-layer 10 is formed by additionally performing epitaxial growth so as to increase the thickness by, for example, 5 μm.

Next, as shown in (c) of FIGS. 6A to 6C, after the element separation region 5 is formed, the avalanche multiplication region for G light and the avalanche multiplication region for B light should be formed. Only, by selectively further injecting boron with ultra-high energy, a P + layer 91 is formed on the P + layer 9. For example, the P + layer 91 is formed by performing multi-stage injection of 3MeV to 4MeV (in 1MeV increments), 5E12cm- ^2.

Next, as shown in (d) of FIGS. 6A to 6C, P + is further selectively injected with ultra-high energy of boron only in the region where the avalanche multiplication region for B light should be formed. A P + layer 92 is formed on the layer 91. For example, the P + layer 92 is formed by performing multi-stage injection of ^{1 MeV to 2} MeV (in 1 MeV increments), 5E12 cm-2.

Finally, as shown in (e) of FIGS. 6A to 6C, as injection is selectively performed only in the region where each avalanche multiplication region should be formed. For example, by injecting 150 keV and 2E 12 cm- ² , N + layers 10a to 10d are applied to the surface of the Psub substrate 7 (specifically, the surface of the P-layer 8 on the main surface 7a (see FIG. 2) side). Form. For each avalanche multiplication region, the region sandwiched between the N + layer and the P + layer is the P- layer.

The impurity concentration of the P + layer 9 is defined by the concentration of the atmosphere at the time of epitaxial growth, but if it is desired to adjust the concentration individually, the injection of impurities may be changed individually.

According to the second example of the method for manufacturing the solid-state image sensor 100, the following effects can be expected in addition to the effects described in the first example.

Ultra-high energy injection is currently difficult to carry out above 8 MeV. Therefore, the difference between the thickness of the P-layer (specifically, the P-layer 8a and the P-layer 8d shown in FIG. 4) between the IR light region and the B light region described in the first example of the manufacturing method. Cannot be 9 μm or more. That is, the P-layer 8a cannot be formed deeper and the P-layer 8d cannot be formed at the same time.

On the other hand, as in the second example of the manufacturing method, by combining the additional epitaxial growth and the ultra-high energy injection, the P-layer 8a is formed thickly (that is, depletion) in order to further improve the detection efficiency of IR light. The P-layer 8d can be formed at the same time (while expanding the layer width). As a result, it is possible to increase the detection efficiency of IR light and also the detection efficiency of visible light such as B light.

Further, even if there is no injector capable of injecting up to 8 MeV, the solid-state image sensor 100 can be formed by repeating ultra-high energy injection with an existing injector and additional epitaxial growth, which increases the process cost. It is possible to suppress it to the minimum.

[Element separation area]
Subsequently, the details of the structure of the element separation region 5 and the method of forming the element separation region 5 will be described.

In the description of the method of forming the element separation region 5 in FIGS. 7 and 8, for example, in the solid-state imaging device 100 shown in FIG. 2, a structure other than the element separation region 5 is already formed.

<Trench separation>
FIG. 7 is a diagram illustrating a trench separation structure which is a first example of the element separation region 5 included in the solid-state image sensor 100 according to the embodiment of the present disclosure. Note that FIG. 7 is a cross-sectional view corresponding to the cross section taken along the line II-II of FIG.

First, the solid-state image sensor 100 already has a structure other than the element separation region 5 shown in FIG. 2, for example. At this time, the element separation region 5 has the same conductive type as the P-layer 8a and the P-layer 8b, and has the same impurity concentration.

Next, by etching the region between the N + layer 10a and the N + layer 10b, the solid-state image sensor 100 has a trench (groove 16) that is a space recessed in the direction orthogonal to the main surface 7a of the Psub substrate 7. ) Is provided.

Next, the element separation region 5 is formed by filling the groove portion 16 with the insulating member 14 that fills the groove portion 16.

The insulating member 14 is a member for forming electrical insulation between adjacent photoelectric conversion layers (in FIG. 7, the photoelectric conversion layer 15a and the photoelectric conversion layer 15b). The insulating member 14 is, for example, SiO ₂ . Note that FIG. 7 illustrates a state in which the groove portion 16 is filled with the insulating member 14.

Further, a P + layer (fifth semiconductor region) 12 which is a P + type layer is formed in the region near the groove portion 16. Specifically, the P + layer 12 is formed in the region around the groove 16 (the region in which the insulating member 14 is formed in FIG. 7) in the element separation region 5.

By forming the P + layer 12, the N + layers 10a and 10b and the P-layers 8a and 8b are formed in a region around the groove portion 16 which is a region where damage due to etching when forming the groove portion 16 remains. The effect of suppressing the depletion layer from extending to the element separation region 5 can be expected.

As the conditions for forming the P + layer 12, for example, boron injection is performed as the side wall injection at the stage immediately after the groove 16 is formed by etching.

As a specific condition, for example, 20 keV, 5E 13 cm- ² is assumed, but the condition is not limited to this condition. Further, for the purpose of suppressing breakdown between PN junctions, it is important to form the P + layers 9a and 9b and the N + layers 10a and 10b apart.

<Injection separation>
FIG. 8 is a diagram illustrating an injection separation structure which is a second example of the element separation region 5 included in the solid-state imaging device 100 according to the embodiment of the present disclosure. Note that FIG. 8 is a cross-sectional view corresponding to the cross section taken along the line II-II of FIG.

First, the solid-state image sensor 100 already has a structure other than the element separation region 5 shown in FIG. 2, for example. At this time, the element separation region 5 shown in FIG. 2 is of the same conductive type as the P-layer 8a and the P-layer 8b, and has the same impurity concentration.

Next, an injection separation region (element separation region 13), which is a P layer, is formed by boron injection. As a result, a P-type layer having a higher impurity concentration than the P-layer 8a and the P-layer 8b is formed as the element separation region 13. For example, the element separation region 13 is a P + layer.

As the boron injection conditions, for example, multi-stage injection of 50 keV to 250 keV (in 100 keV increments) and 2E12 cm- ² is assumed, but the conditions are not limited to these conditions.

As described above, as described with reference to FIGS. 7 and 8, the element separation regions 5 and 13 are formed.

In FIGS. 7 and 8, a part of the P- layer located between the pixel region 1 and the pixel region 2 is formed as the element separation region 5 or the element separation region 13, but the pixel region 1 and The entire P-layer located between the pixel regions 2 may be formed as the element separation region 5 or the element separation region 13. For example, the element separation region 5 or the element separation region 13 may be in contact with the main surface 7a of the Psub substrate 7.

Further, in order to form the transistor 6, a plurality of element separation regions 5 or element separation regions 13 extending in a direction orthogonal to the main surface 7a of the Psub substrate 7 are formed between the pixel region 1 and the pixel region 2. You may be. For example, the transistor 6 may be arranged between the three in the plurality of element separation regions. In this case, the P- layer may be located on the Psub substrate 7 side of the transistor 6 instead of the element separation region 5.

[Effects, etc.]
As described above, the solid-state image sensor 100 according to the present embodiment has a plurality of pixel regions arranged in an array on the Psub substrate 7. Each of the plurality of pixel regions photoelectrically converts the received light. The plurality of pixel regions include a pixel region 1 including a photomultiplier layer 15a that photomultipliers light in the first wavelength region and multipliers the charge by avalanche multiplication, and a second wavelength different from the first wavelength region. It includes a pixel region 2 including a photomultiplier layer 15b, which photomultipliers the light in the region and multiplys the charge by avalanche multiplication. The plurality of pixel regions are separated by the element separation region 5.

According to such a configuration, the solid-state image sensor 100 can detect light in a plurality of wavelength regions by avalanche multiplication. Therefore, according to the solid-state image sensor 100, the detection efficiencies of different wavelengths can be improved.

For example, the photoelectric conversion layer 15a includes a first conductive type N + layer 10a and a second conductive type P-layer 8a different from the first conductive type. Further, for example, the photoelectric conversion layer 15b includes a first conductive type N + layer 10b and a second conductive type P- layer 8b. For example, the P-layer 8a and the P-layer 8b have different thicknesses.

According to such a configuration, the amount of charge to be multiplied by the avalanche can be changed depending on the wavelength region of the light to be detected. Therefore, according to such a configuration, the amount of charge suitable for detecting each of the plurality of wavelength regions can be multiplied by the avalanche multiplication.

Further, for example, the first wavelength region is a longer wavelength region than the second wavelength region, and the thickness of the P-layer 8a is thicker than that of the P-layer 8b.

The detection efficiency of the solid-state image sensor 100 decreases as the wavelength of light increases. Therefore, by increasing the thickness of the P-layer 8a that detects light in the long wavelength region, the charge can be multiplied more by the avalanche multiplication.

Further, for example, the first conductive type is an N type, and the second conductive type is a P type.

According to such a configuration, the first conductive type is a P type, and the second conductive type can be easily manufactured as compared with the case where the second conductive type is an N type.

Further, for example, in a plan view, the pixel area 1 has a smaller area than the pixel area 2. In other words, the width of the element separation region 5 between the pixel region 1 and the pixel region 2 is formed wider than the width of the element separation region 5 between the pixel regions 2 to 4.

For example, IR light is more likely to cause color mixing than visible light. Therefore, according to such a configuration, it is possible to suppress color mixing between the pixel region 1 and the pixel region 2.

Further, for example, the element separation region 5 is provided with a groove portion 16 recessed in a direction orthogonal to the main surface 7a of the Psub substrate 7. In this case, for example, the solid-state image sensor 100 further has an insulating member 14 filled in the groove 16.

According to such a configuration, the electrical insulation between the pixel region 1 and the pixel region 2 can be further improved.

Further, for example, a P + layer 12, which is a P + type layer, is formed in a region near the groove portion 16.

According to such a configuration, the N + layers 10a and 10b and P- are formed in the region around the groove portion 16 which is a region where the damage due to etching when forming the groove portion 16 remains due to the formation of the P + layer 12. It is possible to prevent the depletion layer formed by the layers 8a and 8b from extending into the element separation region 5.

Further, for example, the element separation region 5 is a P-type layer having a higher impurity concentration than the P-layer 8a and the P-layer 8b.

According to such a configuration, the element separation region 13 can be formed in a smaller number of steps as compared with the case where the groove portion 16 is formed.

Further, for example, the solid-state image sensor 100 is further provided between a plurality of pixel regions (for example, a pixel region 1 and a pixel region 2) in a plan view, and is photoelectric in at least one of the plurality of pixel regions. It has a transistor 6 for reading out the charge generated by the conversion. In this case, the transistor 6 is surrounded by the element separation region 5 in a plan view.

According to such a configuration, the solid-state image sensor 100 does not need to separately provide a region for arranging the transistor 6. Therefore, according to such a configuration, the solid-state image sensor 100 can be miniaturized.

Further, for example, the solid-state image sensor 100 further includes a control circuit 17 that applies a variable voltage to the Psub substrate 7.

According to such a configuration, for example, at the time of high voltage drive in which a high voltage is applied to the Psub substrate 7 by the control circuit 17, a depletion layer can be formed thickly with respect to IR light, so that the detection efficiency can be improved. .. Further, for visible light (particularly B light), the detection efficiency can be improved by the avalanche multiplication region. Further, in a situation where the detection efficiency of IR light is not required, the voltage applied to the Psub substrate 7 is lowered (during low voltage drive) to suppress power consumption and for visible light including B light. However, the detection efficiency can be improved.

Further, the light in the first wavelength region is IR light, and the light in the second wavelength region is visible light.

That is, the solid-state image sensor 100 can particularly improve the detection efficiency of both IR light and visible light. In other words, the solid-state image sensor 100 can improve both the detection efficiency of IR light and visible light (particularly, blue light having a short wavelength).

(Other embodiments)
Although the solid-state image sensor according to the embodiment of the present disclosure has been described above based on the embodiment, the present disclosure is not limited to this embodiment. As long as the gist of the present disclosure is not deviated, various modifications that can be conceived by those skilled in the art are applied to the present embodiment, or a form constructed by combining components in different embodiments is also within the scope of one or more embodiments. May be included within.

For example, the wavelength regions of light received by each pixel region of the solid-state image sensor may partially overlap each other.

Further, in the above embodiment, as an example of the pixel regions 1 to 4 of the solid-state image sensor 100, an example of receiving IR light, R light, G light, and B light and performing photoelectric conversion has been described. However, the solid-state image sensor may have, for example, only a pixel region that receives IR light and R light and performs photoelectric conversion, or receives IR light, R light, and G light and performs photoelectric conversion. It may have only the pixel region to be converted, and the combination of the pixel regions included in the solid-state image sensor is not particularly limited.

The solid-state image sensor of the present disclosure can be used for a CMOS (Complementary Metal Oxide Sensor) image sensor or the like that is effective in an environment with only weak light, such as a night-vision in-vehicle camera or a security (night vision and / or surveillance) camera.

1 pixel area (first pixel area)
2 pixel area (second pixel area)
3 pixel area (third pixel area)
4 pixel area (4th pixel area)
5, 13 Element separation area 6 Transistor 7 Psub board (board)
7a Main surface 8, 10 P-layer 8a P-layer (second semiconductor region)
8b P-layer (fourth semiconductor region)
8c P-layer (8th semiconductor region)
8d P-layer (10th semiconductor region)
9, 9a, 9b, 9c, 9d, 91, 92 P + layer 10a N + layer (first semiconductor region)
10b N + layer (third semiconductor region)
10c N + layer (7th semiconductor region)
10d N + layer (9th semiconductor region)
12 P + layer (fifth semiconductor region)
14 Insulating member 15a Photoelectric conversion layer (first photoelectric conversion layer)
15b Photoelectric conversion layer (second photoelectric conversion layer)
15c photoelectric conversion layer (third photoelectric conversion layer)
15d photoelectric conversion layer (fourth photoelectric conversion layer)
16 Groove 17 Control circuit 100 Solid-state image sensor

Claims (11)

It has a plurality of pixel regions arranged in an array on a substrate, and has a plurality of pixel regions.
Each of the plurality of pixel regions photoelectrically converts the received light into light.
The plurality of pixel areas are
A first pixel region containing a first photomultiplier layer that photomultipliers light in the first wavelength region and multipliers the charge by avalanche multiplication.
A second pixel region including a second photoelectric conversion layer that photomultipliers light in a second wavelength region different from the first wavelength region and multiplies the charge by avalanche multiplication is included.
A solid-state image sensor in which the plurality of pixel regions are separated by an element separation region. The first photoelectric conversion layer includes a first semiconductor region of the first conductive type and a second semiconductor region of the second conductive type different from the first conductive type.
The second photoelectric conversion layer includes a third semiconductor region of the first conductive type and a fourth semiconductor region of the second conductive type.
The solid-state image sensor according to claim 1, wherein the second semiconductor region and the fourth semiconductor region have different thicknesses. The first wavelength region is a longer wavelength region than the second wavelength region.
The solid-state image sensor according to claim 2, wherein the thickness of the second semiconductor region is thicker than the thickness of the fourth semiconductor region. The first conductive type is an N type.
The solid-state image sensor according to claim 2 or 3, wherein the second conductive type is a P type. The solid-state image sensor according to any one of claims 1 to 4, wherein the first pixel region has a smaller area than the second pixel region in a plan view. The element separation region is provided with a groove portion recessed in a direction orthogonal to the main surface of the substrate.
The solid-state image sensor according to any one of claims 1 to 5, further comprising an insulating member filled in the groove. The solid-state image sensor according to claim 6, wherein a P + type layer is formed in a region near the groove. The solid-state imaging device according to any one of claims 1 to 5, wherein the element separation region is a P-type layer having a higher impurity concentration than the second semiconductor region and the fourth semiconductor region. Further, in a plan view, it has a transistor provided between the plurality of pixel regions and for reading out the electric charge generated by photoelectric conversion in at least one of the plurality of pixel regions.
The solid-state imaging device according to any one of claims 1 to 8, wherein the transistor is surrounded by the element separation region in a plan view. The solid-state imaging device according to any one of claims 1 to 9, further comprising a control circuit for applying a variable voltage to the substrate. The light in the first wavelength region is near-infrared light.
The solid-state image sensor according to any one of claims 1 to 10, wherein the light in the second wavelength region is visible light.

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