JPWO2019157414A5 - - Google Patents
Download PDFInfo
- Publication number
- JPWO2019157414A5 JPWO2019157414A5 JP2020542942A JP2020542942A JPWO2019157414A5 JP WO2019157414 A5 JPWO2019157414 A5 JP WO2019157414A5 JP 2020542942 A JP2020542942 A JP 2020542942A JP 2020542942 A JP2020542942 A JP 2020542942A JP WO2019157414 A5 JPWO2019157414 A5 JP WO2019157414A5
- Authority
- JP
- Japan
- Prior art keywords
- precharge
- adc device
- capacitor
- node
- coupled
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims 36
- 238000005070 sampling Methods 0.000 claims 17
- 238000000034 method Methods 0.000 claims 4
- 230000008878 coupling Effects 0.000 claims 2
- 238000010168 coupling process Methods 0.000 claims 2
- 238000005859 coupling reaction Methods 0.000 claims 2
- 238000006243 chemical reaction Methods 0.000 claims 1
Claims (20)
デルタシグマ変調器であって、
少なくとも１つの積分器と、
前記少なくとも１つの積分器の出力を受け取るように構成される量子化器と、
各々が前記少なくとも１つの積分器の入力ノードに選択的に結合される、デジタルアナログコンバータ（ＤＡＣ）コンデンサバンクとサンプリングコンデンサバンクとプリチャージコンデンサバンクとを含む、コンデンサモジュールと、
前記プリチャージコンデンサバンクに選択的に結合されるプリチャージ信号生成器であって、前記量子化器の出力コードに少なくとも部分的に基づいて前記プリチャージコンデンサバンクを充電するためにプリチャージ信号を生成するように構成される、前記プリチャージ信号生成器と、
を有する、前記デルタシグマ変調器を含む、ＡＤＣデバイス。 An analog-to-digital converter (ADC) device
It ’s a delta-sigma modulator ,
With at least one integrator ,
A quantizer configured to receive the output of at least one integrator ,
A capacitor module, each comprising a digital-to-analog converter (DAC) capacitor bank , a sampling capacitor bank , and a precharge capacitor bank, each selectively coupled to an input node of the at least one integrator.
A precharge signal generator selectively coupled to the precharge capacitor bank, which generates a precharge signal to charge the precharge capacitor bank at least partially based on the output code of the quantizer. With the precharge signal generator configured to
An ADC device comprising the delta-sigma modulator .
前記プリチャージ信号生成器が、前記量子化器の出力コードを基準電圧と組み合わせることによって前記プリチャージ信号を生成するように構成される、ＡＤＣデバイス。 The ADC device according to claim 1, wherein the ADC device is used.
An ADC device in which the precharge signal generator is configured to generate the precharge signal by combining the output code of the quantizer with a reference voltage.
前記プリチャージ信号生成器が、重み付け係数に基づいて前記プリチャージ信号を生成するように構成される、ＡＤＣデバイス。 The ADC device according to claim 1, wherein the ADC device is used.
An ADC device in which the precharge signal generator is configured to generate the precharge signal based on a weighting factor.
前記重み付け係数が事前に定義された値である、デバイス。 The ADC device according to claim 3, wherein the ADC device is used.
A device in which the weighting factor is a predefined value.
前記重み付け係数が調節可能である、デバイス。 The ADC device according to claim 3, wherein the ADC device is used.
A device in which the weighting factor is adjustable.
前記プリチャージ信号が、下記式：
プリチャージ信号＝（量子化器出力コード×基準電圧×重み付け係数）／２Ｎ
によって与えられ、Ｎが前記量子化器内のビットの数に依存する、ＡＤＣデバイス。 The ADC device according to claim 3, wherein the ADC device is used.
The precharge signal is the following formula:
Precharge signal = (quantizer output code x reference voltage x weighting factor) / 2N
Given by the ADC device, where N depends on the number of bits in the quantizer.
前記プリチャージコンデンサバンクが、入力ノードと出力ノードとの間に並列に結合される複数のプリチャージコンデンサを含み、前記入力ノードと前記出力ノードとの間に並列に結合される前記複数のプリチャージコンデンサの量が調節可能である、ＡＤＣデバイス。 The ADC device according to claim 1, wherein the ADC device is used.
The precharge capacitor bank includes a plurality of precharge capacitors coupled in parallel between an input node and an output node, and the plurality of precharges coupled in parallel between the input node and the output node. An ADC device with an adjustable amount of capacitors.
前記入力ノードと前記出力ノードとの間に並列に結合される前記複数のプリチャージコンデンサの量が、プログラム可能な利得信号に基づいて調節される、ＡＤＣデバイス。 The ADC device according to claim 7.
An ADC device in which the amount of the plurality of precharge capacitors coupled in parallel between the input node and the output node is adjusted based on a programmable gain signal.
前記サンプリングコンデンサバンクが、入力ノードと出力ノードとの間に並列に結合される複数のサンプリングコンデンサを含み、前記入力ノードと前記出力ノードとの間に並列に結合される前記複数のサンプリングコンデンサの量が調節可能である、ＡＤＣデバイス。 The ADC device according to claim 1, wherein the ADC device is used.
The sampling capacitor bank contains a plurality of sampling capacitors coupled in parallel between an input node and an output node, and the amount of the plurality of sampling capacitors coupled in parallel between the input node and the output node. Is adjustable, ADC device.
前記入力ノードと前記出力ノードとの間に並列に結合される前記複数のサンプリングコンデンサの量が、プログラム可能な利得信号に基づいて調節される、ＡＤＣデバイス。 The ADC device according to claim 9 , wherein the ADC device is used.
An ADC device in which the amount of the plurality of sampling capacitors coupled in parallel between the input node and the output node is adjusted based on a programmable gain signal.
前記プリチャージコンデンサバンクの前記少なくとも１つの積分器の各入力ノードへの選択的結合と、前記サンプリングコンデンサバンクの前記少なくとも１つの積分器の各入力ノードへの選択的結合とを指令するように構成されるクロック位相生成器を更に含む、ＡＤＣデバイス。 The ADC device according to claim 10.
Configured to direct the selective coupling of the precharged capacitor bank to each input node of the at least one integrator and the selective coupling of the sampling capacitor bank to each input node of the at least one integrator. An ADC device further comprising a clock phase generator.
積分器と、前記積分器の入力に結合されるプリチャージ回路とを有するデルタシグマ変調器を含み、
前記プリチャージ回路が、前記積分器に結合される第１の端子と、スイッチを介してプリチャージ信号ノードに結合される第２の端子とを有するプリチャージコンデンサを含み、
前記デルタシグマ変調器のためのサンプリング位相の第１の部分の間に、前記プリチャージ信号ノードが、前記デルタシグマ変調器に関連する量子化器出力コードに少なくとも部分的に基づくプリチャージ信号を前記プリチャージコンデンサに搬送するように構成され、
前記デルタシグマ変調器のための前記サンプリング位相の第２の部分の間に、前記プリチャージコンデンサが入力信号ノードに結合される、ＡＤＣデバイス。 An analog-to-digital converter (ADC) device
Includes a delta-sigma modulator with an integrator and a precharge circuit coupled to the input of the integrator.
The precharge circuit comprises a precharge capacitor having a first terminal coupled to the integrator and a second terminal coupled to a precharge signal node via a switch.
During the first portion of the sampling phase for the delta-sigma modulator, the precharge signal node provides a precharge signal that is at least partially based on the quantizer output code associated with the delta-sigma modulator. Configured to carry to a precharge capacitor
An ADC device in which the precharge capacitor is coupled to an input signal node during a second portion of the sampling phase for the delta-sigma modulator.
前記積分器が差動積分器であり、前記プリチャージコンデンサが第１のコンデンサであり、前記プリチャージ信号ノードが第１のプリチャージ信号ノードであり、前記プリチャージ信号が第１のプリチャージ信号であり、前記スイッチが第１のスイッチであり、
前記プリチャージ回路が、前記差動積分器に結合される第１の端子と、第２のスイッチを介して第２のプリチャージ信号ノードに結合される第２の端子とを有する第２のプリチャージコンデンサを更に含み、
前記第２のプリチャージ信号ノードが、前記量子化器出力コードに少なくとも部分的に基づいて第２のプリチャージ信号を搬送するように構成され、
前記第２のスイッチが、前記第２のプリチャージ信号を用いて前記第２のプリチャージコンデンサを選択的に充電するように構成される、ＡＤＣデバイス。 The ADC device according to claim 12, wherein the ADC device is used.
The integrator is a differential integrator, the precharge capacitor is a first capacitor, the precharge signal node is a first precharge signal node, and the precharge signal is a first precharge signal. And the switch is the first switch,
A second precharge circuit having a first terminal coupled to the differential integrator and a second terminal coupled to a second precharge signal node via a second switch. Including additional charge capacitor,
The second precharge signal node is configured to carry the second precharge signal based at least in part on the quantizer output code.
An ADC device in which the second switch is configured to selectively charge the second precharge capacitor using the second precharge signal.
前記プリチャージ回路が、
第１の差動入力信号ノードと第１のコンデンサの第２の端子との間に結合される第３のスイッチと、
第２の差動入力信号ノードと第２のコンデンサの第２の端子との間に結合される第４のスイッチと、
を更に含み、
前記第１及び第２の差動入力信号ノードが、それぞれの第１及び第２の差動入力信号を搬送するように構成され、
前記第３のスイッチが、前記第１の差動入力信号を用いて前記第１のコンデンサを選択的に充電するように構成され、
前記第４のスイッチが、前記第２の差動入力信号を用いて前記第２のコンデンサを選択的に充電するように構成される、ＡＤＣデバイス。 The ADC device according to claim 13, wherein the ADC device is used.
The precharge circuit
A third switch coupled between the first differential input signal node and the second terminal of the first capacitor,
A fourth switch coupled between the second differential input signal node and the second terminal of the second capacitor,
Including
The first and second differential input signal nodes are configured to carry the respective first and second differential input signals.
The third switch is configured to selectively charge the first capacitor with the first differential input signal.
An ADC device in which the fourth switch is configured to selectively charge the second capacitor with the second differential input signal.
前記第１及び第２のスイッチが、前記デルタシグマ変調器の積分位相の間に開いており、前記デルタシグマ変調器のサンプリング位相の第１の部分の間に閉じており、
前記第３及び第４のスイッチが、前記デルタシグマ変調器の前記積分位相の間に開いており、前記デルタシグマ変調器の前記サンプリング位相の第２の部分の間に閉じている、ＡＤＣデバイス。 The ADC device according to claim 14, wherein the ADC device is used.
The first and second switches are open during the integral phase of the delta-sigma modulator and closed during the first portion of the sampling phase of the delta-sigma modulator.
An ADC device in which the third and fourth switches are open during the integral phase of the delta-sigma modulator and closed during the second portion of the sampling phase of the delta-sigma modulator.
前記プリチャージ回路が、
前記第１及び第２のコンデンサの第２の端子に結合される第５のスイッチと、
前記第１のコンデンサの第１の端子と前記差動積分器との間に結合される第６のスイッチと、
前記第２コンデンサの第１の端子と前記差動積分器との間に結合される７のスイッチと、
を更に含み、
前記第５、第６及び第７のスイッチが、前記デルタシグマ変調器のサンプリング位相の間に開いており、前記デルタシグマ変調器の積分位相の間に閉じている、ＡＤＣデバイス。 The ADC device according to claim 14, wherein the ADC device is used.
The precharge circuit
A fifth switch coupled to the second terminal of the first and second capacitors,
A sixth switch coupled between the first terminal of the first capacitor and the differential integrator,
7 switches coupled between the 1st terminal of the 2nd capacitor and the differential integrator,
Including
An ADC device in which the fifth, sixth, and seventh switches are open during the sampling phase of the delta-sigma modulator and closed during the integral phase of the delta-sigma modulator.
前記プリチャージ回路が、前記第１コンデンサと前記第２コンデンサの第１の端子との間に結合される第８のスイッチを更に含み、
前記第８のスイッチが、前記デルタシグマ変調器の積分位相の間に開かれ、前記デルタシグマ変調器のサンプリング位相の間に閉じられる、ＡＤＣデバイス。 The ADC device according to claim 16.
The precharge circuit further comprises an eighth switch coupled between the first capacitor and the first terminal of the second capacitor.
An ADC device in which the eighth switch is opened during the integrating phase of the delta-sigma modulator and closed during the sampling phase of the delta-sigma modulator.
アナログ入力信号を受け取ることと、
デルタシグマ変調器サンプリング位相と積分位相とに基づいて前記アナログ入力信号に関する出力コードをつくることと、
前記出力コードに基づいてプリチャージ信号を生成することと、
前記生成されたプリチャージ信号に基づいて後続のデルタシグマ変調器サンプリング位相のためのプリチャージオペレーションを行うことと、
を含む、方法。 It is an analog-to-digital conversion method.
Receiving analog input signals and
Creating an output code for the analog input signal based on the delta-sigma modulator sampling phase and integral phase ,
Generating a precharge signal based on the output code and
Performing a precharge operation for the subsequent delta-sigma modulator sampling phase based on the generated precharge signal ,
Including, how.
前記プリチャージ信号を生成することが、前記出力コードを基準電圧電源信号と重み付け係数とで乗算することを含む、方法。 The method according to claim 18.
A method of generating the precharge signal comprising multiplying the output code by a reference voltage power supply signal and a weighting factor .
前記プリチャージオペレーションを行うことが、
前記プリチャージ信号に基づいて前記プリチャージコンデンサバンクを充電するために、前記サンプリング位相の第１の部分の間にプリチャージコンデンサバンクに関連する第１のセットのスイッチを閉じることと、
前記サンプリング位相の第２の部分の間に前記第１のセットのスイッチを開くことと、
前記プリチャージコンデンサバンクをアナログ入力信号ノードに放電するために、前記サンプリング位相の第２の部分の間に前記プリチャージコンデンサバンクに関連する第２のセットのスイッチを閉じることと、
を含む、方法。 The method according to claim 18.
Performing the precharge operation
Closing the first set of switches associated with the precharge capacitor bank during the first portion of the sampling phase to charge the precharge capacitor bank based on the precharge signal.
Opening the switch of the first set during the second part of the sampling phase,
Closing the second set of switches associated with the precharge capacitor bank during the second portion of the sampling phase to discharge the precharge capacitor bank to the analog input signal node.
Including, how.
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201862628305P | 2018-02-09 | 2018-02-09 | |
| US62/628,305 | 2018-02-09 | ||
| US16/121,906 | 2018-09-05 | ||
| US16/121,906 US10284222B1 (en) | 2018-02-09 | 2018-09-05 | Delta-sigma converter with pre-charging based on quantizer output code |
| PCT/US2019/017412 WO2019157414A1 (en) | 2018-02-09 | 2019-02-11 | Delta-sigma converter with pre-charging based on quantizer output code |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2021519004A JP2021519004A (en) | 2021-08-05 |
| JPWO2019157414A5 true JPWO2019157414A5 (en) | 2022-02-16 |
| JP7376017B2 JP7376017B2 (en) | 2023-11-08 |
Family
ID=66333913
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2020542942A Active JP7376017B2 (en) | 2018-02-09 | 2019-02-11 | Delta-sigma converter with precharging based on quantizer output code |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US10284222B1 (en) |
| EP (1) | EP3750245A4 (en) |
| JP (1) | JP7376017B2 (en) |
| WO (1) | WO2019157414A1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10720939B2 (en) * | 2018-06-12 | 2020-07-21 | Asahi Kasei Microdevices Corporation | Delta-sigma ad converter and delta-sigma ad converting method |
| US11264959B2 (en) * | 2020-06-16 | 2022-03-01 | Texas Instruments Incorporated | Reference precharge system |
| CN116961671B (en) * | 2023-09-21 | 2023-12-08 | 苏州领慧立芯科技有限公司 | Low distortion precharge sampling circuit and sigma delta modulator |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE58906716D1 (en) * | 1989-05-08 | 1994-02-24 | Siemens Ag | Integrable sigma-delta modulator using switched capacitor technology. |
| US5727023A (en) * | 1992-10-27 | 1998-03-10 | Ericsson Inc. | Apparatus for and method of speech digitizing |
| JP4181058B2 (en) * | 2004-01-20 | 2008-11-12 | 株式会社東芝 | Analog / digital converter and microcomputer equipped with the same |
| CN101044686B (en) * | 2004-10-18 | 2012-09-05 | 线性技术公司 | Analog signal sampling system and method having reduced average differential input current |
| US7489263B1 (en) * | 2007-09-28 | 2009-02-10 | Cirrus Logic, Inc. | Discrete-time programmable-gain analog-to-digital converter (ADC) input circuit with multi-phase reference application |
| US8907829B1 (en) * | 2013-05-17 | 2014-12-09 | Cirrus Logic, Inc. | Systems and methods for sampling in an input network of a delta-sigma modulator |
| US9641192B1 (en) * | 2016-06-14 | 2017-05-02 | Semiconductor Components Industries, Llc | Methods and apparatus for a delta sigma ADC with parallel-connected integrators |
-
2018
- 2018-09-05 US US16/121,906 patent/US10284222B1/en active Active
-
2019
- 2019-02-11 WO PCT/US2019/017412 patent/WO2019157414A1/en unknown
- 2019-02-11 JP JP2020542942A patent/JP7376017B2/en active Active
- 2019-02-11 EP EP19752059.6A patent/EP3750245A4/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107395206B (en) | Successive approximation type digital-to-analog converter with feedback advance setting and corresponding Delta-SigmaADC framework | |
| US7446686B2 (en) | Incremental delta-sigma data converters with improved stability over wide input voltage ranges | |
| US20200412373A1 (en) | Method and circuit for noise shaping sar analog-to-digital converter | |
| US5008674A (en) | Digital-to-analog converter using switched capacitor and transverse filter | |
| US5087914A (en) | DC calibration system for a digital-to-analog converter | |
| US20220100255A1 (en) | Unit Element for performing Multiply-Accumulate Operations | |
| JPS6035830A (en) | Capaciotr circuit analog-digital converter with switch | |
| JPH08125541A (en) | Delta sigma modulator | |
| US7443333B2 (en) | Single stage cyclic analog to digital converter with variable resolution | |
| US7683815B2 (en) | Cross-coupled switched capacitor circuit with a plurality of branches | |
| US20050052300A1 (en) | Single loop feed-forward modulator with summing flash quantizer and multi-bit feedback | |
| CN104467841A (en) | A/D conversion system | |
| US20220066740A1 (en) | Analog Dot Product Multiplier | |
| JP7376017B2 (en) | Delta-sigma converter with precharging based on quantizer output code | |
| US20120007762A1 (en) | Current reduction in a single stage cyclic analog to digital converter with variable resolution | |
| Caselli et al. | Charge sharing and charge injection A/D converters for analog in-memory computing | |
| JPWO2019157414A5 (en) | ||
| US6965258B2 (en) | Sample-and-hold with no-delay reset | |
| JP4270998B2 (en) | Analog signal output circuit and multilevel ΔΣ modulator using the analog signal output circuit | |
| JPH114166A (en) | Consecutive comparison a/d converter | |
| Chen et al. | Analysis and design of sigma-delta ADCs for automotive control systems | |
| US9998137B1 (en) | Power-efficient successive-approximation analog-to-digital converter using LSB averaging | |
| CN116405032A (en) | Noise shaping successive approximation type analog-to-digital converter and control method | |
| JP3731334B2 (en) | Modulator and oversampled A / D converter | |
| JP2023505822A (en) | neural amplifier, neural network and sensor device |