JPWO2019135063A5

JPWO2019135063A5 -

Info

Publication number: JPWO2019135063A5
Application number: JP2020535645A
Authority: JP
Publication date: 2023-11-14
Anticipated expiration: 2038-12-14

Description

１つの実例では、推測バリア命令が終了するまで、
・条件付き選択命令の結果に対するアドレス依存性を有するロード、ストア、データ、又は命令プリロードＲＷ２が、推測バリア命令後にプログラム順に現れる場合、
○条件付き選択命令は、入力レジスタの１つについて、推測的に実行されたロードＲ１に対するレジスタ・データ依存性を有し、
〇条件付き選択命令は、他の入力レジスタについて、Ｒ１に対するレジスタ依存性を有さず、
〇条件付き選択命令の条件は、Ｒ１が体系的に実行されていない場合に、Ｒ１に依存しない入力が選択されるのであれば、
処理回路構成は、キャッシュ内のどのエントリが割り当てられているか、又は削除されているかを評価することにより、Ｒ１から推測的にロードされた値の任意の部分の値を判定するために使用されることができるような、キャッシュ内のエントリの割当に影響を与えるＲＷ２を阻止するように構成される。これにより、攻撃者は、後続する動作ＲＷ２のキャッシュへの効果を分析することにより、ロードＲ１によって推測的にロードされた値に関する任意の情報を導出できなくなる。
In one example, until the speculative barrier instruction terminates,
- If a load, store, data, or instruction preload RW2 with address dependence on the result of a conditional selection instruction appears in program order after the speculative barrier instruction,
o The conditional select instruction has a register data dependency on one of the input registers, speculatively executed load R1,
〇The conditional selection instruction has no register dependence on R1 for other input registers,
〇The condition of the conditional selection instruction is that if R1 is not systematically executed, an input that does not depend on R1 is selected.
Processing circuitry is used to determine the value of any part of the speculatively loaded value from R1 by evaluating which entries in the cache have been allocated or removed. The cache is configured to prevent RW2 from affecting the allocation of entries in the cache such that the cache may This prevents an attacker from deriving any information about the value speculatively loaded by load R1 by analyzing the effect on the cache of subsequent operation RW2.

別の実例では、推測バリア命令が終了するまで、
・条件付き移動命令の結果に対するアドレス依存性を有するロード、ストア、データ、又は命令プリロードＲＷ２が、推測バリア命令後にプログラム順に現れる場合、
○条件付き移動命令は、その入力レジスタについて、推測的に実行されたロードＲ１に対するレジスタ依存性を有さず、
〇条件付き移動命令の条件は、Ｒ１が体系的に実行されていない場合に、条件を満たすのであれば、
処理回路構成は、キャッシュ内のどのエントリが割り当てられているか、又は削除されているかを評価することにより、Ｒ１から推測的にロードされた値の任意の部分の値を判定するために使用されることができるような、キャッシュ内のエントリの割当に影響を与えるＲＷ２を阻止するように構成される。繰り返すが、これにより、攻撃者が、ロードＲ１の不正な推測を悪用して、キャッシュ割当における後続する動作ＲＷ２の効果の分析に基づいて、Ｒ１によってロードされた値に関する情報を取得することを阻止する。
In another example, until the speculative barrier instruction terminates,
- If a load, store, data, or instruction preload RW2 with address dependence on the result of a conditional move instruction appears in program order after the speculative barrier instruction,
o The conditional move instruction has no register dependencies for its input registers on the speculatively executed load R1;
〇If the condition of the conditional movement command is satisfied when R1 is not systematically executed, then
Processing circuitry is used to determine the value of any part of the speculatively loaded value from R1 by evaluating which entries in the cache have been allocated or removed. The cache is configured to prevent RW2 from affecting the allocation of entries in the cache such that the cache can Again, this prevents an attacker from exploiting load R1's false guesses to obtain information about the value loaded by R1 based on an analysis of the effect of subsequent operation RW2 on cache allocation. do.

Claims

a processing circuit configuration that performs data processing;
an instruction decoding circuit configuration that decodes an instruction that controls the processing circuit configuration to execute the data processing,
The instruction decoding circuitry is configured, in response to a speculative barrier instruction, to cause a subsequent operation that occurs in program order after the speculative barrier instruction and has an address dependency on a previous instruction that precedes the speculative barrier instruction in program order to decode the speculative barrier instruction in a cache. controlling said processing circuitry to prevent speculatively influencing the allocation of entries in;
Until the speculative barrier instruction ends,
A load, store, data, or instruction preload instruction RW2 having an address dependency on the result of the conditional selection instruction appears in program order after the speculative barrier instruction, and
the conditional selection instruction has a register data dependency on one of the input registers of the conditional selection instruction to a load instruction R1 being speculatively executed; and For another input register of a conditional select instruction, if it has no register data dependency on R1, and the condition of the conditional select instruction is that R1 is not executed architecturally, then the input register that does not depend on R1 is If it becomes selected,
assignment of entries in the cache determines the value of any part of the speculatively loaded values from R1 by evaluating which entries in the cache are assigned or removed; wherein the processing circuitry is configured to prevent RW2 from affecting the allocation of the entry .

a processing circuit configuration that performs data processing;
an instruction decoding circuit configuration that decodes an instruction that controls the processing circuit configuration to execute the data processing,
The instruction decoding circuitry is configured, in response to a speculative barrier instruction, to cause a subsequent operation that occurs in program order after the speculative barrier instruction and has an address dependency on a previous instruction that precedes the speculative barrier instruction in program order to decode the speculative barrier instruction in a cache. controlling said processing circuitry to prevent speculatively influencing the allocation of entries in;
Until the speculative barrier instruction ends,
A load, store, data or instruction preload instruction RW2 having an address dependency on the result of a conditional move instruction appears in program order after said speculative barrier instruction, and
The conditional move instruction has no register dependency with respect to the input register of the conditional move instruction on the load instruction R1 that is being executed speculatively, and the condition of the conditional move instruction is such that R1 is architecturally If it is not executed, and the above condition is met,
assignment of entries in the cache determines the value of any part of the speculatively loaded values from R1 by evaluating which entries in the cache are assigned or removed; wherein the processing circuitry is configured to prevent RW2 from affecting the allocation of the entry .

The cache is
data cache,
3. The apparatus of claim 1 or 2, being one of: an instruction cache; and a branch prediction cache.

A computer program for controlling a host processing unit that provides an instruction execution environment for executing instructions of target program code, the computer program comprising:
instruction decoding program logic for decoding instructions of said target program code controlling processing program logic to perform data processing;
The instruction decoding program logic is responsive to a speculative barrier instruction to ensure that subsequent operations that occur in program order after the speculative barrier instruction and that have address dependencies on previous instructions that precede the speculative barrier instruction in program order are cached. prevent speculative influence on the allocation of entries in
Until the speculative barrier instruction ends,
A load, store, data, or instruction preload instruction RW2 having an address dependency on the result of the conditional selection instruction appears in program order after the speculative barrier instruction, and
the conditional selection instruction has a register data dependency on one of the input registers of the conditional selection instruction to a load instruction R1 being speculatively executed; and For another input register of a conditional select instruction, if it has no register data dependency on R1, and the condition of the conditional select instruction is that R1 is not executed architecturally, then the input register that does not depend on R1 is If it becomes selected,
assignment of entries in the cache determines the value of any part of the speculatively loaded values from R1 by evaluating which entries in the cache are assigned or removed; the computer program product, wherein the instruction decoder program logic is configured to prevent RW2 from affecting the assignment of the entries when the instruction decode program logic is used to

A computer program for controlling a host processing unit that provides an instruction execution environment for executing instructions of target program code, the computer program comprising:
instruction decoding program logic for decoding instructions of said target program code controlling processing program logic to perform data processing;
The instruction decoding program logic is responsive to a speculative barrier instruction to ensure that subsequent operations that occur in program order after the speculative barrier instruction and that have address dependencies on previous instructions that precede the speculative barrier instruction in program order are cached. prevent speculative influence on the allocation of entries in
Until the speculative barrier instruction ends,
A load, store, data or instruction preload instruction RW2 having an address dependency on the result of a conditional move instruction appears in program order after said speculative barrier instruction, and
The conditional move instruction has no register dependency with respect to the input register of the conditional move instruction on the load instruction R1 that is being executed speculatively, and the condition of the conditional move instruction is such that R1 is architecturally If it is not executed, and the above condition is met,
assignment of entries in the cache determines the value of any part of the speculatively loaded values from R1 by evaluating which entries in the cache are assigned or removed; the computer program product, wherein the instruction decoder program logic is configured to prevent RW2 from affecting the assignment of the entries when the instruction decode program logic is used to

decoding the speculative barrier instruction;
In response to the decoding of the speculative barrier instruction, a subsequent operation that occurs in program order after the speculative barrier instruction and has an address dependency on a previous instruction that precedes the speculative barrier instruction in program order causes the allocation of an entry in the cache. controlling processing circuitry to prevent a priori from influencing a data processing method, the method comprising:
Until the speculative barrier instruction ends,
A load, store, data, or instruction preload instruction RW2 having an address dependency on the result of the conditional selection instruction appears in program order after the speculative barrier instruction, and
the conditional selection instruction has a register data dependency on one of the input registers of the conditional selection instruction to a load instruction R1 being speculatively executed; and For another input register of a conditional select instruction, if it has no register data dependency on R1, and the condition of the conditional select instruction is that R1 is not executed architecturally, then the input register that does not depend on R1 is If it becomes selected,
assignment of entries in the cache determines the value of any part of the speculatively loaded values from R1 by evaluating which entries in the cache are assigned or removed; the data processing method, the data processing method comprising the step of preventing RW2 from affecting the allocation of the entry when the data processing method can be used to

decoding the speculative barrier instruction;
In response to the decoding of the speculative barrier instruction, a subsequent operation that occurs in program order after the speculative barrier instruction and has an address dependency on a previous instruction that precedes the speculative barrier instruction in program order causes the allocation of an entry in the cache. controlling processing circuitry to prevent a priori from influencing a data processing method, the method comprising:
Until the speculative barrier instruction ends,
A load, store, data or instruction preload instruction RW2 having an address dependency on the result of a conditional move instruction appears in program order after said speculative barrier instruction, and
The conditional move instruction has no register dependency with respect to the input register of the conditional move instruction on the load instruction R1 that is being executed speculatively, and the condition of the conditional move instruction is such that R1 is architecturally If it is not executed, and the above condition is met,
assignment of entries in the cache determines the value of any part of the speculatively loaded values from R1 by evaluating which entries in the cache are assigned or removed; the data processing method, the data processing method comprising the step of preventing RW2 from affecting the allocation of the entry when the data processing method can be used to