JPWO2016189415A1 - Semiconductor device and electronic device - Google Patents

Abstract

A semiconductor device with a small occupation area is provided. Alternatively, a highly productive semiconductor device is provided. A p-channel transistor and an n-channel transistor using an oxide semiconductor are formed over the p-channel transistor to form an integrated circuit. In addition, the p-channel transistor includes a first wiring, a second wiring, a third wiring, and a fourth wiring. The p-channel transistor includes a first conductor, a second conductor, and a third conductor. The n-channel transistor includes a third conductor, a fourth conductor, and a fifth conductor. The third conductor is disposed on the first conductor, and the first wiring is disposed on the third conductor. The second wiring is disposed on the second conductor. Are arranged, the fourth wiring is arranged on the fourth conductor, and the third wiring is arranged on the fifth conductor.

Description

The present invention relates to an object, a method, or a manufacturing method. Or this invention relates to a process, a machine, a manufacture, or a composition (composition of matter). One embodiment of the present invention relates to a semiconductor device, a light-emitting device, a display device, an electronic device, a lighting device, and manufacturing methods thereof. In particular, one embodiment of the present invention relates to a light-emitting device using an organic electroluminescence (hereinafter also referred to as EL) phenomenon and a manufacturing method thereof. In particular, one embodiment of the present invention relates to an electronic device in which a semiconductor integrated circuit including a power device mounted on a power supply circuit, an LSI such as a memory or a CPU, a thyristor, a converter, and an image sensor is mounted as a component.

Note that one embodiment of the present invention is not limited to the above technical field.

Note that in this specification, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. An electro-optical device, a semiconductor circuit, and an electronic device may include a semiconductor device.

In recent years, semiconductor devices have been developed, and LSIs, CPUs, and memories are mainly used. The CPU is an assembly of semiconductor elements each having a semiconductor integrated circuit (at least a transistor and a memory) separated from a semiconductor wafer and having electrodes serving as connection terminals.

A semiconductor circuit (IC chip) such as an LSI, a CPU, or a memory is mounted on a circuit board, for example, a printed wiring board, and used as one of various electronic device components.

In addition, a technique for forming a transistor using a semiconductor thin film formed over a substrate having an insulating surface has attracted attention. The transistor is widely applied to electronic devices such as an integrated circuit (IC) and an image display device (also simply referred to as a display device). A silicon-based semiconductor material is widely known as a semiconductor thin film applicable to a transistor, but an oxide semiconductor has attracted attention as another material.

A transistor using an oxide semiconductor is known to have extremely small leakage current in a non-conduction state. For example, a low power consumption CPU using a characteristic in which an extremely low leakage current of a transistor including an oxide semiconductor is small is disclosed (see Patent Document 1).

JP 2012-257187 A

An object is to provide a semiconductor device with high productivity. Another object is to provide a semiconductor device with high yield. Another object is to provide a semiconductor device with a small occupation area.

Another object is to provide a highly integrated semiconductor device. Another object is to provide a semiconductor device with high operating speed. Another object is to provide a semiconductor device with low power consumption.

Another object is to provide a novel semiconductor device. Another object is to provide a module including the semiconductor device. Another object is to provide an electronic device including the semiconductor device or the module.

Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.

One embodiment of the present invention includes a first transistor, a second transistor, a first wiring, a second wiring, a third wiring, a first conductor, and a second conductor. , A third conductor, a fourth conductor, a fifth conductor, and a sixth conductor, wherein the first transistor includes a first terminal, a second terminal, and The first transistor has a first gate terminal, the second transistor has a third terminal, a fourth terminal, and a second gate terminal, and the first terminal has a first conductor, a third terminal, The terminal is electrically connected to the first wiring through the fourth conductor, and the second terminal is connected to the second wiring through the second conductor and the fifth conductor. The first gate terminal is electrically connected to the second gate terminal through the third conductor, the sixth conductor, and the third wiring. The body is the second The third terminal is disposed on the first conductor, the fourth conductor is disposed on the first conductor, passes through the third terminal, and the first conductor is disposed on the first conductor. The second conductor is disposed on the second terminal, the fifth conductor is disposed on the second conductor, the second conductor is disposed on the fourth conductor, and the second conductor is disposed on the second terminal. The wiring is disposed on the fifth conductor, the third conductor is disposed on the first gate wiring, the sixth conductor is disposed on the third conductor, and the third conductor The wiring is disposed on the sixth conductor.

One embodiment of the present invention includes a first transistor, a second transistor, a first wiring, a second wiring, a third wiring, a first conductor, and a second conductor. , A third conductor, a fourth conductor, a fifth conductor, a sixth conductor, a first structure, and a second structure, The transistor has a first terminal, a second terminal, and a first gate terminal, the second transistor has a third terminal, a fourth terminal, and a second gate terminal, The first terminal is electrically connected to the first wiring through the first conductor, the third terminal, and the fourth conductor, and the second terminal is connected to the second conductor, and The second gate is electrically connected to the second wiring through the fifth conductor, and the first gate terminal is connected to the second wiring through the third conductor, the sixth conductor, and the third wiring. Gate terminal and power The first conductor is disposed on the first terminal, the third terminal is disposed on the first conductor, and the fourth conductor penetrates the third terminal. The first conductor is disposed on the first conductor, the first wiring is disposed on the fourth conductor, the second conductor is disposed on the second terminal, and the fifth conductor is , Penetrating the first structure and disposed on the second conductor, the second wiring is disposed on the fifth conductor and the first structure, and the third conductor is disposed on the first conductor And the sixth conductor penetrates the second structure and is disposed on the third conductor, and the third wiring includes the sixth conductor and the second conductor. It is arranged on the structure.

One embodiment of the present invention includes a first transistor, a second transistor, a first wiring, a second wiring, a third wiring, a first conductor, and a second conductor. , A third conductor, a fourth conductor, a fifth conductor, a sixth conductor, a first structure, and a second structure, The transistor has a first terminal, a second terminal, and a first gate terminal, the second transistor has a third terminal, a fourth terminal, and a second gate terminal, The first terminal is electrically connected to the first wiring through the first conductor, the third terminal, and the fourth conductor, and the second terminal is connected to the second conductor, and The second gate is electrically connected to the second wiring through the fifth conductor, and the first gate terminal is connected to the second wiring through the third conductor, the sixth conductor, and the third wiring. Gate terminal and power The first conductor is disposed on the first terminal, and the fourth conductor is disposed on the first conductor through the third terminal, and the first wiring Is in contact with the side surface of the fourth conductor, the second conductor is disposed on the second terminal, the fifth conductor penetrates the first structure, and is on the second conductor. The second wiring is in contact with the side surface of the fifth conductor, the second wiring is disposed on the first structure, and the third conductor is on the first gate wiring. The sixth conductor passes through the second structure, is disposed on the third conductor, the third wiring is in contact with the side surface of the sixth conductor, and the second wiring is , Disposed on the second structure.

In the above structure, the first structure body includes a first oxide and a sixth conductor, and the second structure body includes a second oxide and a seventh conductor. Yes.

In the above structure, the second transistor includes an oxide semiconductor.

An electronic apparatus having the semiconductor device described above.

A semiconductor device with high productivity can be provided. Alternatively, a semiconductor device with high yield can be provided. Alternatively, a semiconductor device with a small occupation area can be provided.

Alternatively, a highly integrated semiconductor device can be provided. Alternatively, a semiconductor device with high operating speed can be provided. Alternatively, a semiconductor device with low power consumption can be provided.

Alternatively, a novel semiconductor device can be provided. Alternatively, a module including the semiconductor device can be provided. Alternatively, an electronic device including the semiconductor device or the module can be provided.

Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention need not have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.

FIG. 10 is a circuit diagram illustrating one embodiment of a semiconductor device. FIG. 10 is a perspective view illustrating one embodiment of a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a semiconductor device. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 10 is a cross-sectional view illustrating one embodiment of a method for manufacturing a semiconductor device. FIG. 6A and 6B illustrate an atomic ratio of an oxide semiconductor according to one embodiment of the present invention. FIGS. 4A to 4C illustrate structural analysis by XRD of a CAAC-OS and a single crystal oxide semiconductor, and a diagram illustrating a limited-field electron diffraction pattern of the CAAC-OS. Sectional TEM image of CAAC-OS, planar TEM image and image analysis image thereof. The figure which shows the electron diffraction pattern of nc-OS, and the cross-sectional TEM image of nc-OS. Cross-sectional TEM image of a-like OS. FIG. 6 shows changes in crystal parts of an In—Ga—Zn oxide due to electron irradiation. 1 is a block diagram illustrating a semiconductor device according to one embodiment of the present invention. FIG. 10 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. FIG. 11 is a perspective view illustrating an electronic device according to one embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. In the embodiments and examples described below, the same portions or portions having similar functions are denoted by the same reference numerals or the same hatch patterns in different drawings, and description thereof is not repeated. To do.

Note that in each drawing described in this specification, the size, the film thickness, or the region of each component is exaggerated for clarity in some cases. Therefore, it is not necessarily limited to the scale.

Further, the terms such as first, second, and third used in this specification are given for avoiding confusion between components, and are not limited numerically. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”.

The functions of “source” and “drain” may be interchanged when the direction of current changes during circuit operation. Therefore, in this specification, the terms “source” and “drain” can be used interchangeably.

“Parallel” means a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 ° to 30 °. “Vertical” refers to a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.

In this specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

Further, the voltage refers to a potential difference between two points, and the potential refers to electrostatic energy (electric potential energy) possessed by a unit charge in an electrostatic field at a certain point. However, generally, a potential difference between a potential at a certain point and a reference potential (for example, ground potential) is simply referred to as a potential or a voltage, and the potential and the voltage are often used as synonyms. Therefore, in this specification, unless otherwise specified, the potential may be read as a voltage, or the voltage may be read as a potential.

In addition, since a transistor including an oxide semiconductor film is an n-channel transistor, in this specification, a transistor that can be regarded as having no drain current flowing when the gate voltage is 0 V has normally-off characteristics. It is defined as a transistor. A transistor that can be regarded as having a drain current flowing when the gate voltage is 0 V is defined as a transistor having normally-on characteristics.

Note that the channel length refers to, for example, a region where a gate electrode overlaps with an oxide semiconductor film (or a portion where current flows in the oxide semiconductor film when the transistor is on) in a top view of a transistor, or a channel The distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the region where is formed. Note that in one transistor, the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

The channel width refers to a source in a region where an oxide semiconductor film (or a portion where current flows in the oxide semiconductor film when the transistor is on) and a gate electrode overlap, or a region where a channel is formed, for example And the length of the part where the drain faces. Note that in one transistor, the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

Note that depending on the structure of the transistor, the channel width in a region where a channel is actually formed (hereinafter referred to as an effective channel width) and the channel width (hereinafter referred to as an apparent channel width) shown in the top view of the transistor May be different). For example, in a transistor having a three-dimensional structure, the effective channel width is larger than the apparent channel width shown in the top view of the transistor, and the influence may not be negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of a channel region formed on the side surface of the oxide semiconductor film may increase. In that case, the effective channel width in which the channel is actually formed is larger than the apparent channel width shown in the top view.

By the way, in a transistor having a three-dimensional structure, it may be difficult to estimate an effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the oxide semiconductor film is known. Therefore, when the shape of the oxide semiconductor film is not accurately known, it is difficult to accurately measure the effective channel width.

Therefore, in this specification, an apparent channel width which is the length of a portion where a source and a drain face each other in a region where an oxide semiconductor film and a gate electrode overlap with each other in a top view of a transistor is referred to as an “enclosed channel”. Sometimes referred to as “Surrounded Channel Width (SCW)”. In this specification, in the case where the term “channel width” is simply used, it may denote an enclosed channel width or an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may denote an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, and the like can be determined by obtaining a cross-sectional TEM image and analyzing the image. it can.

Note that in the case where the field-effect mobility of a transistor, the current value per channel width, and the like are calculated and calculated, the calculation may be performed using the enclosed channel width. In that case, the value may be different from that calculated using the effective channel width.

(Embodiment 1)
In this embodiment, a structure and a manufacturing method of a semiconductor device will be described.

<CMOS inverter>
The circuit diagram shown in FIG. 1 shows a configuration of a so-called CMOS inverter in which a p-channel transistor 200 and an n-channel transistor 100 are connected in series and their gates are connected.

The CMOS inverter has a layered structure of layers 299, 199, and 399 indicated by dotted lines in the drawing. A p-channel transistor 200 is provided in the hierarchy 299, an n-channel transistor 100 is provided in the hierarchy 199, and a wiring 310, a wiring 320, and a wiring 330 are provided in the hierarchy 399.

<Structure 1 of Semiconductor Device>
FIG. 3 is a cross-sectional view of the semiconductor device corresponding to FIG. The semiconductor device illustrated in FIG. 2 includes a hierarchy 299, a hierarchy 199, and a hierarchy 399. The semiconductor device illustrated in FIG. 3 includes the transistor 200 provided in the hierarchy 299, the transistor 100 provided in the hierarchy 199, the wiring 310, the wiring 320, and the wiring 330 provided in the hierarchy 399. Further, the transistor 100 is disposed above the transistor 200.

Further, a layered structure including a wiring may be provided between the layers. For example, as illustrated in FIG. 3, a stacked structure including an insulator 281 and an insulator 282, a conductor 312, a wiring 340, a conductor 332, and a conductor 352 is provided between the hierarchy 299 and the hierarchy 199. Is provided. In addition, a stacked structure including an insulator 181 and an insulator 182 is provided between the layers 199 and 399.

FIG. 2 is a perspective view illustrating overlapping of the top views of the layers 399, 299, 199, the stacked structure between the layers 399 and 199, and the stacked structure between the layers 199 and 299 in FIG. It is. 3A shows a cross-sectional view of the plane X1-X2-X3-X4 in FIG. FIG. 3B is a cross-sectional view of the plane Y1-Y2-Y3-Y4 in FIG.

Part of the structure of the transistor 200 and the transistor 100 is connected by a conductor. Here, the conductor 333, the conductor 332, the conductor 331, and the wiring 330 are arranged so as to overlap with the one-dot broken line B1-B2. Therefore, the wiring 330 includes the insulator 182, the insulator 181, the insulator 180, the insulator 120, the insulator 112, the insulator 111, the insulator 110, and the oxide 130 a and the oxide 130 b that are components of the transistor 100. And formed through the conductor 140b.

Further, the conductor 353, the conductor 352, the conductor 351, and the wiring 350 are arranged so as to overlap with the one-dot broken line C1-C2. Furthermore, the conductor 313, the conductor 312, the conductor 311, and the wiring 310 are arranged so that a part thereof overlaps on the one-dot broken line A1-A2. In other words, the transistor 200 and the transistor 100 may be partially or entirely overlapped with each other in a region (space) having the dashed line A1-A2, the dashed line B1-B2, and the dashed line C1-C2 as outer edges. It is.

By making the n-channel transistor above the p-channel transistor, the degree of integration of the semiconductor device can be increased. Further, by forming the n-channel transistor above the p-channel transistor, the wiring routing distance can be shortened, and high-speed operation can be realized by reducing parasitic capacitance and resistance.

Further, the p-channel transistor and the n-channel transistor are formed in different layers. Therefore, different materials can be selected as materials for the gate conductor and the gate insulating film in accordance with the conductivity type of the transistor so that the electrical characteristics of the transistor are improved.

<< Level 299 >>
As illustrated in FIG. 3, the hierarchy 299 includes a transistor 200, a region 210, a conductor 313, a conductor 333, a conductor 353, and an insulator 280. Note that the transistor 200 is separated from an adjacent transistor by the region 210 or the like. The region 210 is a region having an insulating property. The transistor 200 is electrically connected to the transistor 100, the wiring 310, or the wiring 330 through the conductor 313, the conductor 333, or the conductor 353.

Further, the transistor 200 provided in the hierarchy 299 is a transistor using the semiconductor substrate 201. The transistor 200 includes a region 240 a in the semiconductor substrate 201, a region 240 b in the semiconductor substrate 201, an insulator 250, an insulator 255, an insulator 280, and a conductor 260.

In the transistor 200, the region 240a and the region 240b function as a source region and a drain region. The insulator 250 functions as a gate insulator. The conductor 260 functions as a gate electrode. Therefore, the resistance of the channel formation region can be controlled by the potential applied to the conductor 260. That is, the conduction / non-conduction between the region 240a and the region 240b can be controlled by the potential applied to the conductor 260.

As the semiconductor substrate 201, for example, a single semiconductor substrate such as silicon or germanium, or a semiconductor substrate such as silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide may be used. Preferably, a single crystal silicon substrate is used as the semiconductor substrate 201.

As the semiconductor substrate 201, a semiconductor substrate having an impurity imparting n-type conductivity is used. However, as the semiconductor substrate 201, a semiconductor substrate having an impurity imparting p-type conductivity may be used. In that case, a well having an impurity imparting n-type conductivity may be provided in a region to be the transistor 200. Alternatively, the semiconductor substrate 201 may be i-type.

The upper surface of the semiconductor substrate 201 preferably has a (110) plane. Thus, the on characteristics of the transistor 200 can be improved.

The regions 240a and 240b are regions having an impurity imparting p-type conductivity. In this way, the transistor 200 constitutes a p-channel transistor. Note that the transistor 200 may have any structure as long as it is a p-channel transistor.

Further, as illustrated in FIG. 3, an insulator 281 and an insulator 282 are provided over the layer 299. The insulator 281 and the insulator 282 are embedded with a conductor 313 and a conductor 312 that reaches the conductor 311. In addition, a wiring 340 reaching the conductor 165 is embedded. In addition, a conductor 333 reaching the conductor 333 and the conductor 332 reaching the conductor 331 are embedded. Further, a conductor 353 reaching the conductor 353 and a conductor 352 reaching the conductor 351 is embedded.

Examples of the insulator 281 and the insulator 282 include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. An insulator containing may be used as a single layer or a stacked layer.

One or more of the insulator 281 and the insulator 282 preferably include an insulator having a function of blocking impurities such as hydrogen and oxygen. When an insulator having a function of blocking impurities such as hydrogen and oxygen is provided in the vicinity of the transistor 100, electrical characteristics of the transistor 100 can be stabilized.

Examples of the insulator having a function of blocking impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, and lanthanum. An insulator containing neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer.

Examples of the conductor 312, the wiring 340, and the conductor 332 include boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, A conductor including one or more of molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten may be used as a single layer or a stacked layer. For example, it may be an alloy or a compound, a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, a conductor containing titanium and nitrogen Etc. may be used.

<< Level 199 >>
As shown in FIG. 3, a layer 199 is provided on the insulator 282. The hierarchy 199 includes the transistor 100, the conductor 311, and the conductor 331. Note that the transistor 100 is electrically connected to the transistor 200 through the conductor 331 and the conductor 351.

The transistor 100 provided in the layer 199 includes an insulator 110 in which a conductor 165 is embedded, a conductor 165 that functions as a gate electrode, an insulator 111 that functions as a gate insulator, an insulator 112, and an insulator 120. An oxide 130 having a region where a channel is formed, a conductor 140a functioning as one of a source and a drain, a conductor 140b functioning as the other of a source and a drain, and a conductor 160 functioning as a gate electrode And an insulator 150 functioning as a gate insulator, and an insulator 180.

Note that the conductor 165 controls electrical characteristics such as a threshold voltage of the transistor 100 by applying a certain potential to the conductor 165 through the wiring 340, for example. Alternatively, for example, the conductor 165 and the conductor 160 functioning as a gate electrode of the transistor 100 may be electrically connected by electrically connecting the conductor 165 to the conductor 351 and the like. . Thus, the on-state current of the transistor 100 can be increased. In addition, since the punch-through phenomenon can be suppressed, electrical characteristics in the saturation region of the transistor 100 can be stabilized. In that case, the wiring 340 is not necessarily formed.

The insulator 111, the insulator 112, and the insulator 120 include a wiring 330 that reaches the conductor 331 through a conductor 140b that is one of the source and the drain of the transistor 100, and a wiring 310 that reaches the conductor 311. The wiring 350 reaching the conductor 351 passes therethrough. For example, in the insulator 111, the wiring 330 is embedded in the opening reaching the conductor 331, that is, the bottom surface of the wiring 330 and the bottom surface of the insulator 111 have the same height from the substrate. Also, it is assumed that it has penetrated. The same applies to the opening reaching the conductor 321, the opening reaching the conductor 311, and the opening reaching the conductor 351.

The insulator 111, the insulator 112, and the insulator 120 are preferably insulators containing oxygen, such as a silicon oxide film or a silicon oxynitride film. Note that an insulator containing excess oxygen (containing oxygen in excess of the stoichiometric composition) is preferably used as the insulator 120. By providing such an insulator containing excess oxygen in contact with the oxide 130, oxygen vacancies in the oxide 130 can be compensated.

The oxide 130 includes an oxide 130a, an oxide 130b over the oxide 130a, and an oxide 130c over the oxide 130b.

Note that the oxide constituting the oxide 130 has a large energy gap of 3.0 eV or more, and an oxide film obtained by processing the oxide under appropriate conditions and sufficiently reducing the carrier density is applied. In the transistor, the leakage current (off current) between the source and the drain in the off state can be made extremely low as compared with a conventional transistor using silicon.

An applicable oxide preferably contains at least indium (In) or zinc (Zn). In particular, In and Zn are preferably included. Further, as a stabilizer for reducing variation in electrical characteristics of transistors using the oxide, in addition to them, gallium (Ga), tin (Sn), hafnium (Hf), zirconium (Zr), titanium (Ti), It is preferable that one or more kinds selected from scandium (Sc), yttrium (Y), and lanthanoid (for example, cerium (Ce), neodymium (Nd), and gadolinium (Gd)) are included.

Here, a case where the oxide 130 includes indium, the element M, and zinc is considered. Here, the element M is preferably aluminum, gallium, yttrium, tin, or the like. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, the element M may be a combination of a plurality of the aforementioned elements. A preferable range of the ratio of the number of atoms of indium, the element M, and zinc included in the oxide 130, and x: y: z will be described with reference to FIGS. 32A and 32B.

32A and 32B illustrate the range of the ratio of the number of atoms of indium, the element M, and zinc included in the oxide 130. FIG. Here, FIGS. 32A and 32B show an example in which the element M is Ga. Note that the atomic ratio of oxygen is not described in FIGS. 32A and 32B.

For example, an oxide containing indium, element M, and zinc is known to have a homologous phase (homologus series) represented by InMO ₃ (ZnO) _m (m is a natural number). Here, a case where the element M is Ga is considered as an example. The region shown by a thick straight line in FIG. 32 can be a single-phase solid solution region when, for example, powders of In ₂ O ₃ , Ga ₂ O ₃ , and ZnO are mixed and fired at 1350 ° C. It is a known composition. Further, the coordinates indicated by the square symbols in FIG. 32 are compositions that are known to have a mixture of spinel crystal structures.

For example, a compound represented by ZnM ₂ O ₄ such as ZnGa ₂ O ₄ is known as a compound having a spinel crystal structure. Further, as shown in FIGS. 32A and 32B, the composition in the vicinity of ZnGa ₂ O ₄ , that is, x, y, and z are close to (x: y: z) = (0: 2: 1). If it has a value, a spinel crystal structure is likely to be formed or mixed.

Here, the oxide 130 is preferably a CAAC-OS (c-axis-aligned crystal oxide semiconductor) film. In addition, the CAAC-OS film preferably does not include a spinel crystal structure. In order to increase carrier mobility, it is preferable to increase the In content. In the oxide 130 containing indium, element M, and zinc, the s orbital of heavy metal mainly contributes to carrier conduction. By increasing the indium content, more s orbitals overlap, so the indium content is low. A large amount of oxide has higher mobility than an oxide with a small content of indium. Therefore, carrier mobility can be increased by using an oxide containing a large amount of indium for the oxide 130.

Therefore, the ratio of the number of atoms of indium, the element M, and zinc included in the oxide 130, x: y: z, is preferably in the range of the region 11 illustrated in FIG. 32B, for example. Here, the region 11 includes a first coordinate K (x: y: z = 8: 14: 7), a second coordinate L (x: y: z = 2: 5: 7), a third coordinate The coordinate M (x: y: z = 51: 149: 300), the fourth coordinate N (x: y: z = 46: 288: 833), and the fifth coordinate O (x: y: z = 0) : 2: 11), the sixth coordinate P (x: y: z = 0: 0: 1), and the seventh coordinate Q (x: y: z = 1: 0: 0) in order This is a region having a ratio of the number of atoms within a range connected by line segments. Note that the region 11 includes coordinates on a straight line.

By setting x: y: z to the region 11 shown in FIG. 32B, the proportion of the spinel crystal structure observed in the nanobeam analysis can be eliminated or extremely reduced. Thus, an excellent CAAC-OS film can be obtained. In addition, since carrier scattering and the like at the boundary between the CAAC structure and the spinel crystal structure can be reduced, a transistor with high field-effect mobility can be realized when the oxide 130 is used for a transistor. In addition, a highly reliable transistor can be realized.

In addition, the influence of impurities in the oxide 130 will be described. Note that in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide 130 so as to reduce carrier density and purity. Note that the carrier density of the oxide 130 is less than 8 × 10 ¹¹ / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹⁰ / cm ³ , and 1 × 10 ⁻⁹ / It is preferable to use an oxide having a carrier density of cm ³ or more. In order to reduce the impurity concentration in the oxide 130, it is preferable to reduce the impurity concentration in the adjacent film.

In addition, when nitrogen is contained in the oxide 130, the carrier density may be increased. The nitrogen concentration of the oxide 130 is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, more preferably 5 or less in SIMS. × 10 ¹⁷ atoms / cm ³ or less.

In addition, when hydrogen is contained in the oxide 130, the carrier density may be increased. Further, in the oxide 130, when hydrogen contained as an impurity moves to the oxide surface, it may be combined with oxygen near the surface and desorbed as water molecules. At that time, oxygen deficient V _O is formed at the position of O desorbed as water molecules. Therefore, it is desirable that the hydrogen concentration of the oxide 130 be sufficiently reduced. Therefore, the oxide 130 has a surface temperature range of 100 ° C. or higher and 700 ° C. or lower or 100 ° C. or higher and 500 ° C. or lower in terms of the number of water molecules in TDS analysis (Thermal Desorption Spectrometry). What can be observed as water molecules of 1.0 × 10 ²¹ molecules / cm ³ (1.0 particles / nm ³ ) or less, preferably 1.0 × 10 ²⁰ molecules / cm ³ (0.1 particles / nm ³ ) or less. And

Here, a method for measuring the amount of water discharge using TDS analysis will be described below.

The total amount of gas released when the measurement sample is subjected to TDS analysis is proportional to the integrated value of the ionic strength of the released gas. The total amount of gas released can be calculated by comparison with a standard sample.

For example, from the TDS analysis result of a silicon substrate containing hydrogen of a predetermined density as a standard sample and the TDS analysis result of the measurement sample, the amount of released oxygen molecules (N _H2O ) of the measurement sample is obtained by the following formula Can do. Here, it is assumed that all of the gases detected at a mass to charge ratio of 18 obtained by TDS analysis are derived from water molecules. The mass to charge ratio of CH ₄ is 18, but is not considered here as it is unlikely to exist. Further, a water molecule containing hydrogen molecules of mass numbers 2 and 3 that are hydrogen isotopes, and a water molecule containing oxygen atoms of mass number 17 and oxygen atoms of mass number 18 that are isotopes of oxygen atoms. However, since the existence ratio in the natural world is extremely small, it is not considered.

N _H2 is a value obtained by converting hydrogen molecules desorbed from the standard sample by density. _SH2 is an integral value of ion intensity when the standard sample is subjected to TDS analysis. Here, the reference value of the standard sample is N _H2 / SH ₂ . _{SH 2 O} is an integral value of ion intensity when the measurement sample is subjected to TDS analysis. α is a coefficient that affects the ionic strength in the TDS analysis. For details of the above formula, refer to JP-A-6-275697. The amount of released oxygen was measured using a thermal desorption analyzer EMD-WA1000S / W manufactured by Electronic Science Co., Ltd. and using a silicon substrate containing a certain amount of hydrogen atoms as a standard sample.

N _H2O is the amount of water molecules released. The release amount when converted to hydrogen atoms is twice the release amount of water molecules.

Note that hydrogen as an impurity in the oxide is in a state of a hydrogen atom, a hydrogen ion, a hydrogen molecule, a hydroxy group, a hydroxide ion, or the like, and is difficult to exist as a water molecule.

By using an oxide including a crystal whose hydrogen concentration is sufficiently reduced for a channel formation region of a transistor, stable electrical characteristics can be imparted. That is, it is possible to suppress fluctuations in electrical characteristics and improve reliability. In addition, a semiconductor device with reduced power consumption can be provided.

In the semiconductor device illustrated in FIG. 2, a barrier film may be provided between the oxide 130 and the conductor 160 in addition to the insulator 150. Alternatively, the oxide 130c may have a barrier property.

Note that an insulating film having a barrier property against oxygen or hydrogen is preferably used as the barrier film. As such an insulator, for example, aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, silicon nitride, or the like can be used. When formed using such a material, the barrier film suppresses the release of oxygen from the oxide 130 and the diffusion of oxygen from the insulator 120 to other than the oxide 130, and the entry of impurities such as hydrogen from the outside. Functions as a layer to prevent

An insulating film containing excess oxygen is provided in contact with the oxide 130, and is further surrounded by a barrier film, so that the oxide substantially matches the stoichiometric composition, or is supersaturated with more oxygen than the stoichiometric composition. It can be in the state of. In addition, entry of impurities such as hydrogen into the oxide 130 can be prevented.

In addition, the conductor 140a and the conductor 140b include a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above-described element as a component. (Titanium nitride film, molybdenum nitride film, tungsten nitride film) or the like. Or indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide added It is also possible to apply a conductive material such as indium tin oxide. Alternatively, a stacked structure of the conductive material and the metal material can be employed.

Further, the conductor 160 and the conductor 165 are a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing the above-described element as a component. (Titanium nitride film, molybdenum nitride film, tungsten nitride film) or the like may be used. Or indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide added It is also possible to apply a conductive material such as indium tin oxide. Alternatively, a stacked structure of the conductive material and the metal material can be employed.

Note that the conductor 311, the conductor 331, and the conductor 351 are preferably formed at the same time when the conductor 165 is formed. Therefore, the conductor 311, the conductor 331, and the conductor 351 can be formed using a material similar to that of the conductor 160 and the conductor 165.

The insulator 180 includes a wiring 330 reaching the conductor 331 through the conductor 140b that is one of the source and the drain of the transistor 100 and a wiring reaching the conductor 104a that is the other of the source and the drain of the transistor 100. 320 and the wiring 350 reaching the conductor 351 pass therethrough. The insulator 180 is embedded with a conductor 160 which is a gate electrode of the transistor 100, an insulator 150 which is a gate insulator, and an oxide 130.

Note that an insulator containing excess oxygen (containing oxygen in excess of the stoichiometric composition) is preferably used as the insulator 120. By providing such an insulator containing excess oxygen in contact with the oxide 130, oxygen vacancies in the oxide 130 can be compensated.

Further, as illustrated in FIG. 3, an insulator 181 and an insulator 182 are provided on the layer 199. In addition, the insulator 181 and the insulator 182 are penetrated by the wiring 310, the wiring 320, and the wiring 330.

Examples of the insulator 181 and the insulator 182 include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. An insulator containing may be used as a single layer or a stacked layer.

One or more of the insulator 181 and the insulator 182 preferably include an insulator having a function of blocking impurities such as hydrogen and oxygen. When an insulator having a function of blocking impurities such as hydrogen and oxygen is provided in the vicinity of the transistor 100, electrical characteristics of the transistor 100 can be stabilized.

Examples of the insulator having a function of blocking impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, and lanthanum. An insulator containing neodymium, hafnium, or tantalum may be used as a single layer or a stacked layer.

<< Level 399 >>
As shown in FIG. 3, a layer 399 is provided on the insulator 182. The hierarchy 399 includes a wiring 310, a wiring 320, and a wiring 330, and an insulator 360 in which the wiring 310, the wiring 320, and the wiring 330 are embedded.

In addition, the insulator 360 passes through the wiring 310 reaching the conductor 311, the wiring 320 reaching the conductor 140 a, the wiring 330 reaching the conductor 331, and the wiring 350 reaching the conductor 351.

As the insulator 360, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum is used. Or a single layer or a stacked layer.

Examples of the wiring 310, the wiring 320, and the wiring 330 include boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, A conductor containing one or more of ruthenium, silver, indium, tin, tantalum, and tungsten may be used in a single layer or a stacked layer. For example, it may be an alloy or a compound, a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin and oxygen, a conductor containing titanium and nitrogen Etc. may be used.

<Structure 2 of Semiconductor Device>
Note that the semiconductor device illustrated in FIG. 4 is a semiconductor device in which only the structure of the transistor 200 of the semiconductor device illustrated in FIGS. 1, 2, and 3 is different. Therefore, for the semiconductor device illustrated in FIG. 4, the description of the semiconductor device illustrated in FIGS. 1, 2, and 3 is referred to. Specifically, the semiconductor device illustrated in FIG. 4 illustrates the case where the transistor 200 is a Fin type. When the transistor 200 is of the Fin type, an effective channel width can be increased, whereby the on-state characteristics of the transistor 200 can be improved. In addition, since the contribution of the electric field of the gate conductor can be increased, off characteristics of the transistor 200 can be improved.

According to this embodiment, a CMOS inverter can be manufactured with a small number of masks by replacing an n-channel Si transistor with an oxide semiconductor transistor without a complicated doping process. Therefore, productivity and yield can be increased. In addition, the degree of integration of the semiconductor device can be increased by forming the n-channel transistor above the p-channel transistor. Further, by forming the n-channel transistor above the p-channel transistor, the wiring routing distance can be shortened, and high-speed operation can be realized by reducing parasitic capacitance and resistance.

Further, the p-channel transistor and the n-channel transistor are formed in different layers. Therefore, different materials can be selected as materials for the gate conductor and the gate insulating film in accordance with the conductivity type of the transistor so that the electrical characteristics of the transistor are improved.

(Embodiment 2)
In this embodiment, a modification of the transistor 100 is described with reference to FIGS. Note that the component denoted by the same reference numeral as the structure described in Embodiment 1 can refer to the semiconductor device described in Embodiment 1. In particular, the semiconductor device described in Embodiment 1 can be referred to because the layer 299 and the stacked structure between the layers 299 and 199 are similar to those in Embodiment 1.

<Structure 3 of Semiconductor Device>
FIG. 5 is a cross-sectional view of a semiconductor device different from that in the first embodiment. The semiconductor device illustrated in FIG. 5 includes a hierarchy 299, a hierarchy 199, and a hierarchy 399. Note that the semiconductor device in FIG. 5 is different from the semiconductor device in Embodiment 1 in the structure of the hierarchy 299 and the hierarchy 399. 5 includes the transistor 200 provided in the hierarchy 299, the transistor 100, the structure 101, and the structure 102 provided in the hierarchy 199, the wiring 310, the wiring 320, and the wiring provided in the hierarchy 399. A wiring 330 is included. Further, the transistor 100 is disposed above the transistor 200. Further, a layered structure including a wiring may be provided between the layers.

Part of the structure of the transistor 200 and the transistor 100 is connected by a conductor. Here, the conductor 333, the conductor 332, the conductor 331, the conductor 336, and the wiring 330 are arranged so as to overlap with the one-dot broken line B1-B2. Therefore, the conductor 336 includes the insulator 182, the insulator 181, the insulator 180, the insulator 120, the insulator 112, the insulator 111, the insulator 110, and the oxides 130 a and 130 b that are components of the transistor 100. And through the conductor 140b.

In addition, the conductor 353, the conductor 352, the conductor 351, the structure 102, and the wiring 350 are arranged so as to overlap with the one-dot broken line C1-C2. Further, the conductor 313, the conductor 312, the conductor 311, the structure body 101, and the wiring 310 are arranged so that a part thereof overlaps on the one-dot broken line A1-A2. In other words, the transistor 200 and the transistor 100 may be partially or entirely overlapped with each other in a region (space) having the dashed line A1-A2, the dashed line B1-B2, and the dashed line C1-C2 as outer edges. It is.

By making the n-channel transistor above the p-channel transistor, the degree of integration of the semiconductor device can be increased. Further, by forming the n-channel transistor above the p-channel transistor, the wiring routing distance can be shortened, and high-speed operation can be realized by reducing parasitic capacitance and resistance.

Further, the p-channel transistor and the n-channel transistor are formed in different layers. Therefore, different materials can be selected as materials for the gate conductor and the gate insulating film in accordance with the conductivity type of the transistor so that the electrical characteristics of the transistor are improved.

<< Level 199 >>
As illustrated in FIG. 5, a layer 199 is provided over the insulator 282. The hierarchy 199 includes the transistor 100, the conductor 311, the conductor 331, the structure 101, and the structure 102. Note that the transistor 100 is electrically connected to the transistor 200 through the structure body 101 and the conductor 331. In addition, the transistor 100 is electrically connected to the transistor 200 through the structure body 102 and the conductor 351.

The transistor 100 provided in the layer 199 includes an insulator 110 in which a conductor 165 is embedded, a conductor 165 that functions as a gate electrode, an insulator 111 that functions as a gate insulator, an insulator 112, and an insulator 120. An oxide 130 having a region where a channel is formed, a conductor 140a functioning as one of a source and a drain, a conductor 140b functioning as the other of a source and a drain, and a conductor 160 functioning as a gate electrode And an insulator 150 functioning as a gate insulator, and an insulator 180.

Note that the conductor 165 controls electrical characteristics such as a threshold voltage of the transistor 100 by applying a certain potential to the conductor 165 through the wiring 340, for example. Alternatively, for example, the conductor 165 and the conductor 160 functioning as a gate electrode of the transistor 100 may be electrically connected by electrically connecting the conductor 165 to the conductor 351 and the like. . Thus, the on-state current of the transistor 100 can be increased. In addition, since the punch-through phenomenon can be suppressed, electrical characteristics in the saturation region of the transistor 100 can be stabilized. In that case, the wiring 340 is not necessarily formed.

The structure body 101 provided in the layer 199 has a stacked structure of an oxide 131a, an oxide 131b, and a conductor 141. In addition, a conductor 316 reaching the conductor 311 passes through the structure 101.

The structure body 102 provided in the layer 199 has a stacked structure of the oxide 132a, the oxide 132b, and the conductor 142. In addition, a conductor 356 reaching the conductor 311 passes through the structure 101.

The insulator 111, the insulator 112, and the insulator 120 include a conductor 336 that reaches the conductor 331 through a conductor 140b that is one of the source and the drain of the transistor 100, and a conductor that reaches the conductor 351. 356 and a conductor 316 reaching the conductor 311 pass therethrough.

The insulator 180 passes through the conductor 140b that is one of the source and the drain of the transistor 100 and reaches the conductor 331 and the conductor 104a that is the other of the source and the drain of the transistor 100. The wiring 320 and the conductor 356 reaching the conductor 351 pass therethrough. The insulator 180 is embedded with a conductor 160 which is a gate electrode of the transistor 100, an insulator 150 which is a gate insulator, and an oxide 130.

The conductor 336 passes through the insulator 180, the conductor 140b that is one of the source and the drain of the transistor 100, the oxide 130, the insulator 120, the insulator 112, and the insulator 111, and the wiring 330 and the conductor 331 is connected. In this structure, the conductor 336 is in contact with the conductor 140b which is one of the source and the drain of the transistor 100 as well as the side surface. Therefore, a sufficient contact area between the conductor 336 and the conductor 140b can be secured, and a stable voltage can be applied to the conductor 140b, so that a semiconductor device with high electrical characteristics can be provided.

Further, in this configuration, since the area of the upper surface of the conductor 336 is larger than the area in contact with the conductor 336 and the wiring 330, alignment with the wiring 330 to be formed later is also easy. Therefore, a highly productive semiconductor device can be provided. Alternatively, a semiconductor device with high yield can be provided.

The conductor 316 and the conductor 356 pass through the structure body 101 and the structure body 102 and are connected to the wiring 310 and the wiring 350, respectively. Accordingly, the upper surface of the conductor 316 and the upper surface of the conductor 356 can be made larger than the surface where the conductor 316 and the wiring 310 are in contact with each other, and the surface where the conductor 356 and the wiring 350 are in contact with each other. Also, alignment with the wiring 350 is easy. Therefore, a highly productive semiconductor device can be provided. Alternatively, a semiconductor device with high yield can be provided.

Further, as illustrated in FIG. 5, an insulator 181 having an opening and an insulator 182 are provided over the layer 199. In addition, the wiring 310, the wiring 320, and a part of the wiring 330 are embedded in the openings.

<< Level 399 >>
As illustrated in FIG. 5, a layer 399 is provided over the insulator 182. The hierarchy 399 includes a wiring 310, a wiring 320, and a wiring 330, and an insulator 360 in which the wiring 310, the wiring 320, and the wiring 330 are embedded.

In addition, the insulator 360 passes through the wiring 310 reaching the conductor 311, the wiring 320 reaching the conductor 140 a, the wiring 330 reaching the conductor 331, and the wiring 350 reaching the conductor 351.

<Structure 4 of Semiconductor Device>
Note that the semiconductor device illustrated in FIG. 6 is a semiconductor device in which only the structure of the transistor 200 of the semiconductor device illustrated in FIG. 5 is different. Therefore, the description of the semiconductor device illustrated in FIG. 5 is referred to for the semiconductor device illustrated in FIG. Specifically, the semiconductor device illustrated in FIG. 6 illustrates the case where the transistor 200 is a Fin type. When the transistor 200 is of the Fin type, an effective channel width can be increased, whereby the on-state characteristics of the transistor 200 can be improved. In addition, since the contribution of the electric field of the gate conductor can be increased, off characteristics of the transistor 200 can be improved.

By making the n-channel transistor above the p-channel transistor, the degree of integration of the semiconductor device can be increased. Further, by forming the n-channel transistor above the p-channel transistor, the wiring routing distance can be shortened, and high-speed operation can be realized by reducing parasitic capacitance and resistance.

Further, the p-channel transistor and the n-channel transistor are formed in different layers. Therefore, different materials can be selected as materials for the gate conductor and the gate insulating film in accordance with the conductivity type of the transistor so that the electrical characteristics of the transistor are improved.

(Embodiment 3)
In this embodiment, a modification of the transistor 100 is described with reference to FIGS. Note that the component denoted by the same reference numeral as the structure described in Embodiment 1 can refer to the semiconductor device described in Embodiment 1. In particular, the semiconductor device described in Embodiment 1 can be referred to because the layer 299 and the stacked structure between the layers 299 and 199 are similar to those in Embodiment 1.

<Structure 5 of Semiconductor Device>
FIG. 7 is a cross-sectional view of a semiconductor device different from that of the first embodiment. The semiconductor device illustrated in FIG. 7 includes a hierarchy 299, a hierarchy 199, and a hierarchy 399. The semiconductor device illustrated in FIG. 7 is different from the semiconductor device in Embodiment 1 in the structure of the hierarchy 299 and the hierarchy 399. 7 includes the transistor 200 provided in the hierarchy 299, the transistor 100, the structure 101, and the structure 102 provided in the hierarchy 199, the wiring 310, the wiring 320, and the wiring provided in the hierarchy 399. 330. Further, the transistor 100 is disposed above the transistor 200.

Further, a layered structure including a wiring may be provided between the layers. For example, as illustrated in FIG. 7, a stacked structure including an insulator 281, an insulator 282, a conductor 312, a wiring 340, and a conductor 332 is provided between the hierarchy 299 and the hierarchy 199. . An insulator 181 is provided between the layer 199 and the layer 399.

Part of the structure of the transistor 200 and the transistor 100 is connected by a conductor. Here, the conductor 333, the conductor 332, the conductor 331, the conductor 336, and the wiring 330 are arranged so as to overlap with the one-dot broken line B1-B2. Therefore, the conductor 336 includes the insulator 181, the insulator 180, the insulator 120, the insulator 112, the insulator 111, the insulator 110, and the oxide 130 a, the oxide 130 b, and the conductor that are components of the transistor 100. It is formed through 140b.

In addition, the conductor 353, the conductor 352, the conductor 351, the structure 102, and the wiring 350 are arranged so as to overlap with the one-dot broken line C1-C2. Further, the conductor 313, the conductor 312, the conductor 311, the structure body 101, and the wiring 310 are arranged so that a part thereof overlaps on the one-dot broken line A1-A2. In other words, the transistor 200 and the transistor 100 may be partially or entirely overlapped with each other in a region (space) having the dashed line A1-A2, the dashed line B1-B2, and the dashed line C1-C2 as outer edges. It is.

By making the n-channel transistor above the p-channel transistor, the degree of integration of the semiconductor device can be increased. Further, by forming the n-channel transistor above the p-channel transistor, the wiring routing distance can be shortened, and high-speed operation can be realized by reducing parasitic capacitance and resistance.

Further, the p-channel transistor and the n-channel transistor are formed in different layers. Therefore, different materials can be selected as materials for the gate conductor and the gate insulating film in accordance with the conductivity type of the transistor so that the electrical characteristics of the transistor are improved.

<< Level 199 >>
As shown in FIG. 7, a layer 199 is provided over the insulator 282. The hierarchy 199 includes the transistor 100, the conductor 311, the conductor 331, the structure 101, and the structure 102. Note that the transistor 100 is electrically connected to the transistor 200 through the structure body 101 and the conductor 331. In addition, the transistor 100 is electrically connected to the transistor 200 through the structure body 102 and the conductor 351.

The transistor 100 provided in the layer 199 includes an insulator 110 in which a conductor 165 is embedded, a conductor 165 that functions as a gate electrode, an insulator 111 that functions as a gate insulator, an insulator 112, and an insulator 120. An oxide 130 having a region where a channel is formed, a conductor 140a functioning as one of a source and a drain, a conductor 140b functioning as the other of a source and a drain, and a conductor 160 functioning as a gate electrode And an insulator 150 functioning as a gate insulator, and an insulator 180.

Note that the conductor 165 controls electrical characteristics such as a threshold voltage of the transistor 100 by applying a certain potential to the conductor 165 through the wiring 340, for example. Alternatively, for example, the conductor 165 and the conductor 160 functioning as a gate electrode of the transistor 100 may be electrically connected by electrically connecting the conductor 165 to the conductor 351 and the like. . Thus, the on-state current of the transistor 100 can be increased. In addition, since the punch-through phenomenon can be suppressed, electrical characteristics in the saturation region of the transistor 100 can be stabilized. In that case, the wiring 340 is not necessarily formed.

The structure body 101 provided in the layer 199 has a stacked structure of an oxide 131a, an oxide 131b, and a conductor 141. In addition, a conductor 316 reaching the conductor 311 passes through the structure 101.

The structure body 102 provided in the layer 199 has a stacked structure of the oxide 132a, the oxide 132b, and the conductor 142. In addition, a conductor 156 reaching the conductor 311 passes through the structure 101.

The insulator 111, the insulator 112, and the insulator 120 include a conductor 336 that reaches the conductor 331 and a conductor that reaches the conductor 311 through the conductor 140b that is one of the source and the drain of the transistor 100. 316 and the conductor 356 reaching the conductor 351 pass therethrough.

The insulator 180 passes through the conductor 140b that is one of the source and the drain of the transistor 100 and reaches the conductor 331 and the conductor 104a that is the other of the source and the drain of the transistor 100. The wiring 320 and the conductor 356 reaching the conductor 351 pass therethrough. The insulator 180 is embedded with a conductor 160 which is a gate electrode of the transistor 100, an insulator 150 which is a gate insulator, and an oxide 130.

The conductor 336 passes through the insulator 180, the conductor 140b that is one of the source and the drain of the transistor 100, the oxide 130, the insulator 120, the insulator 112, and the insulator 111, and the wiring 330 and the conductor 331 is connected. In this configuration, since the wiring 330 is also in contact with the upper surface of the conductor 140a, a sufficient contact area between the conductor 104a and the wiring 330 can be secured. Therefore, a stable voltage can be applied to the conductor 140b, and thus the electrical characteristics are high. A semiconductor device can be provided.

Further, as illustrated in FIG. 7, an insulator 181 having an opening is provided over the layer 199. In addition, the wiring 310, the wiring 320, and a part of the wiring 330 are embedded in the openings.

<< Level 399 >>
As illustrated in FIG. 7, a layer 399 is provided over the insulator 181. The hierarchy 399 includes a wiring 310, a wiring 320, and a wiring 330, and an insulator 360 in which the wiring 310, the wiring 320, and the wiring 330 are embedded.

In addition, the insulator 360 passes through the wiring 310 reaching the conductor 311, the wiring 320 reaching the conductor 140 a, the wiring 330 reaching the conductor 331, and the wiring 350 reaching the conductor 351.

<Structure 6 of Semiconductor Device>
Note that the semiconductor device illustrated in FIG. 8 is a semiconductor device in which only the structure of the transistor 200 of the semiconductor device illustrated in FIG. 7 is different. Therefore, the description of the semiconductor device illustrated in FIG. 7 is referred to for the semiconductor device illustrated in FIG. Specifically, the semiconductor device illustrated in FIG. 8 illustrates the case where the transistor 200 is a Fin type. When the transistor 200 is of the Fin type, an effective channel width can be increased, whereby the on-state characteristics of the transistor 200 can be improved. In addition, since the contribution of the electric field of the gate conductor can be increased, off characteristics of the transistor 200 can be improved.

According to this embodiment, a CMOS inverter can be manufactured with a small number of masks by replacing an n-channel Si transistor with an oxide semiconductor transistor without a complicated doping process. Therefore, productivity and yield can be increased. In addition, the degree of integration of the semiconductor device can be increased by forming the n-channel transistor above the p-channel transistor. Further, by forming the n-channel transistor above the p-channel transistor, the wiring routing distance can be shortened, and high-speed operation can be realized by reducing parasitic capacitance and resistance.

Further, the p-channel transistor and the n-channel transistor are formed in different layers. Therefore, different materials can be selected as materials for the gate conductor and the gate insulating film in accordance with the conductivity type of the transistor so that the electrical characteristics of the transistor are improved.

(Embodiment 4)
In this embodiment, a method for manufacturing a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. Note that the component denoted by the same reference numeral as the structure described in Embodiment 1 can refer to the semiconductor device described in Embodiment 1.

A method for manufacturing the semiconductor device illustrated in FIG. 3 is described with reference to FIGS. Here, a method for manufacturing a hierarchy above the hierarchy 299 will be described.

First, the insulator 280 is formed over the P-channel transistor 200. Note that although the insulator 280 has a single-layer structure in this embodiment, a stacked structure including two or more layers may be used.

The insulator 280 is formed by a sputtering method, a chemical vapor deposition (CVD) method (thermal CVD method, a metal organic chemical vapor deposition (MOCVD) method, a plasma enhanced chemical vapor deposition (PECVD)), or plasma enhanced chemical vapor deposition (PECVD). ) Method, molecular epitaxy (MBE) method, atomic layer deposition (ALD) method, or pulsed laser deposition (PLD) method. . In particular, it is preferable to form the insulator by a CVD method, preferably an ALD method, because coverage can be improved. In order to reduce damage caused by plasma, thermal CVD, MOCVD, or ALD is preferable. Alternatively, a silicon oxide film with good step coverage formed by reacting TEOS (Tetra-Ethyl-Ortho-Silicate) or silane with oxygen, nitrous oxide, or the like can be used.

Subsequently, a mask 291 is formed over the insulator 280 (see FIG. 9A). The mask 291 may be manufactured by a lithography method using a resist, for example. Further, a hard mask made of an inorganic film or a metal film may be formed.

Next, part of the insulator 280 is etched using the mask 291 to form an opening (see FIG. 9B). Next, the mask 291 is removed, and then a conductor 301 and a conductor 302 are formed in the opening and over the insulator 280 (see FIG. 9C).

Next, the conductor 301 and the conductor 302 are partially removed by planarization treatment (arrows in the drawing) to expose the insulator 280, whereby the conductor 311, the conductor 331, and the conductor 351 are formed. It is formed (see FIG. 9D). For the removal of the conductor 301 and the conductor 302, it is preferable to use a polishing method such as a chemical mechanical polishing (CMP) method. Alternatively, dry etching may be used. For example, a technique such as etch back may be used. When a polishing method such as a CMP method is used, the polishing rates of the conductor 301 and the conductor 302 may have a distribution in the plane of the sample. In this case, the exposure time of the insulator 280 may be long at a location where the polishing rate is high. Therefore, it is preferable that the polishing rate of the insulator 280 be lower than the polishing rate of the conductors 301 and 302. Since the polishing speed of the insulator 280 is low, the insulator 280 can serve as a polishing stopper film in the polishing process of the conductor 301 and the conductor 302. In addition, the flatness of the surface of the insulator 280 can be improved.

Here, the CMP method is a method of planarizing the surface of a workpiece by a combined chemical and mechanical action. Generally, a polishing cloth is attached on a polishing stage, and a slurry (abrasive) is supplied between the work piece and the polishing cloth while rotating or swinging the polishing stage and the work piece to slurry. The surface of the workpiece is polished by a chemical reaction between the surface of the workpiece and the surface of the workpiece and by mechanical polishing between the polishing cloth and the workpiece.

In the CMP method, for example, foamed polyurethane, non-woven fabric, suede or the like can be used as the polishing cloth. As the abrasive grains, for example, silica (silicon oxide), cerium oxide, manganese oxide, aluminum oxide, or the like can be used. Further, for example, fumed silica or colloidal silica can be used as silica.

The slurry used in the CMP method may be adjusted in pH from the viewpoint of easy removal of the workpiece and the stability of the slurry solution. For example, when an acidic slurry is used, it is preferable that the insulator 280 serving as a stopper film has high resistance to acid. In the case where an alkaline slurry is used, the insulator 280 is preferably highly resistant to alkali.

Further, for example, hydrogen peroxide or the like may be used as an oxidizing agent in the slurry.

Here, as an example, a case where at least one of the conductor 301 and the conductor 302 includes tungsten and the insulator 280 includes silicon oxide is described. As the slurry, for example, fumed silica or colloidal silica is preferably used for the abrasive grains. For example, it is preferable to use an acidic slurry, and for example, it is preferable to use hydrogen peroxide as an oxidizing agent.

Next, the insulator 281 is formed over the insulator 280, the conductor 311, the conductor 331, and the conductor 351, so that the wiring 340, the conductor 312, the conductor 332, and the conductor 352 are formed (FIG. 10). (See (A).) Note that the insulator 280 can be referred to for a method for manufacturing the insulator 281. For the method for manufacturing the wiring 340, the conductor 312, the conductor 332, and the conductor 352, the conductor 311, the conductor 331, and the conductor 351 can be referred to.

Next, the insulator 282 and the insulator 110 are formed over the insulator 281, the wiring 340, the conductor 312, the conductor 332, and the conductor 352. Subsequently, a mask 191 is formed over the insulator 110 (see FIG. 10B).

Next, an opening is formed in the insulator 282 and the insulator 110 and the insulator 120 (see FIG. 10C). After that, the mask 191 is removed, and then a mask 192 is formed (FIG. 11A). The opening of the insulator 110 is widened using the mask 192 (FIG. 11B). Subsequently, a conductor 303 and a conductor 304 are formed (FIG. 11C). Next, the surface of the conductor is removed so as to be planarized, so that a conductor 165, a conductor 313, a conductor 333, and a conductor 353 are formed (see FIG. 12A). Here, as an example, a layer containing tungsten is used as the conductor 303, the conductor 304, and the like, and a layer containing silicon oxide is used as the insulator 110, whereby the conductor 303 and the conductor 304 are removed by a CMP method. In some cases, the etching rate of the insulator 110 may be reduced. Therefore, the planarity of the surface of the insulator 110 may be improved. In addition, variation in height of the conductor 313 may be reduced.

Next, the transistor 100 is formed over the insulator 120. First, the insulator 111, the insulator 112, and the insulator 120 are formed. Note that the insulator 120 is preferably an insulator containing excess oxygen. As a method for forming an insulator containing excess oxygen, a film formation condition in a CVD method or a sputtering method can be set as appropriate to form a silicon oxide film or a silicon oxynitride film containing a large amount of oxygen in the film. . Alternatively, oxygen may be added by an ion implantation method, an ion doping method, or plasma treatment after the silicon oxide film or the silicon oxynitride film is formed.

Subsequently, an oxide 130A and an oxide 130B are formed. In this embodiment, the oxide 130A and the oxide 130B have a two-layer structure, but a single layer may be used. Moreover, you may form by the laminated structure which consists of n layer (n is 3 or more).

For example, by forming the second semiconductor over the first semiconductor with reduced impurities, the second semiconductor is formed with less impurities than the first semiconductor, and diffusion of impurities from the lower layer Can be prevented. In the case where stacking is performed over the oxide semiconductor in a later step, the third semiconductor is thinly formed over the second semiconductor, so that the upper layer of the oxide semiconductor can be transferred from the upper layer to the second semiconductor. Impurity diffusion can also be suppressed. By forming the transistor so that the second semiconductor with reduced impurities serves as a channel region, a highly reliable semiconductor device can be provided.

The thickness of the oxide semiconductor is, for example, 1 nm to 500 nm, preferably 1 nm to 300 nm.

Heat treatment is preferably performed after the oxide 130A and the oxide 130B are formed. The heat treatment may be performed at a temperature of 250 ° C. to 650 ° C., preferably 300 ° C. to 500 ° C., in an inert gas atmosphere, an atmosphere containing an oxidizing gas of 10 ppm or more, or a reduced pressure atmosphere. Further, the heat treatment may be performed in an atmosphere containing 10 ppm or more of an oxidizing gas in order to supplement the desorbed oxygen after performing the heat treatment in an inert gas atmosphere. By the heat treatment here, impurities such as hydrogen and water can be removed from the oxide 130A and the oxide 130B. Further, by this heat treatment, oxygen can be supplied from the insulator 120 to the oxide 130A and the oxide 130B. At this time, it is preferable that the insulator 120 contain excess oxygen because oxygen can be efficiently supplied to the oxide semiconductor.

Subsequently, a conductor 140A is formed over the oxide 130B. Note that although a single layer structure is shown here, the conductor 140A may have a single layer structure or a stacked structure of two or more layers.

The conductor 140A includes a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film (titanium nitride film, A molybdenum nitride film, a tungsten nitride film, or the like can be used. Further, as the conductor 140A, a semiconductor typified by polycrystalline silicon doped with an impurity element such as phosphorus, or a silicide film such as nickel silicide may be used. Or indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide film A conductive material such as added indium tin oxide can also be used. Alternatively, a stacked structure of the conductive material and the metal material can be employed. For example, a stack of a 5 nm titanium film, a 10 nm titanium nitride film, and a 100 nm tungsten film can be formed.

The conductor 140A can be formed by a sputtering method, an evaporation method, a CVD method (including a thermal CVD method, an MOCVD method, a PECVD method, or the like). In order to reduce damage caused by plasma, thermal CVD, MOCVD, or ALD is preferable.

Subsequently, a mask 193 is formed, the conductor 140A is processed, and the conductor 140B is formed. After that, the oxide 130A and the oxide 130B are processed using the conductor 140B as a hard mask, so that the oxide 130a and the oxide 130b are formed (FIGS. 13A and 13B). For example, dry etching or the like may be used for processing.

Next, an insulator 180 is formed, and a mask 194 is formed (FIG. 14A). Subsequently, an opening is formed in the insulator 180. For example, dry etching or the like may be used for processing. Note that the insulator 180A is preferably an insulator containing excess oxygen. As a method for forming an insulator containing excess oxygen, a film formation condition in a CVD method or a sputtering method can be set as appropriate to form a silicon oxide film or a silicon oxynitride film containing a large amount of oxygen in the film. . Alternatively, oxygen may be added by an ion implantation method, an ion doping method, or plasma treatment after the silicon oxide film or the silicon oxynitride film is formed.

Subsequently, the conductor 140a and the conductor 140b are formed by removing part of the conductor 140 using the insulator 180 as a mask, and at the same time, an opening is formed (FIG. 14B).

Next, the oxide 130C, the insulator 150A, and the conductor 160A are formed (FIG. 15A).

The oxide 130C can be formed in a manner similar to that of the oxide 130A and the oxide 130B. Note that the thickness of the oxide 130C is preferably as small as possible to increase the on-state current of the transistor. For example, the oxide 130C may have a region less than 20 nm, preferably 10 nm or less, and more preferably 5 nm or less. On the other hand, the oxide 130C has a function of blocking entry of elements other than oxygen (such as hydrogen and silicon) included in the adjacent insulator into the oxide 130b where a channel is formed. Therefore, the oxide 130C preferably has a certain thickness. For example, the oxide 130C may have a thickness of 0.3 nm or more, preferably 1 nm or more, and more preferably 2 nm or more. In addition, the oxide 130C has a property of blocking oxygen in order to suppress outward diffusion of oxygen released from the insulator 110 or an insulator interposed between the insulator 110 and the oxide 130B. It is preferable.

The thickness of the insulator 150A is, for example, 1 nm to 20 nm, and a sputtering method, an MBE method, a CVD method, a pulse laser deposition method, an ALD method, or the like can be used as appropriate. Alternatively, the insulator 150A may be formed using a sputtering apparatus that forms a film in a state where a plurality of substrate surfaces are set substantially perpendicular to the sputtering target surface. Further, the MOCVD method may be used. For example, a gallium oxide film formed by an MOCVD method can be used as the insulator 150A.

As a material of the insulator 150A, a silicon oxide film, a gallium oxide film, a gallium zinc oxide film, a zinc oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, or a silicon nitride oxide film is used. Can be formed. The insulator 150A preferably contains oxygen in a portion in contact with the oxide 130B. In particular, the insulator 150A preferably includes oxygen (excess oxygen) in an amount exceeding the stoichiometric composition in the film (in the bulk). In this embodiment, the insulator 150A is formed by a CVD method as the insulator 150A. A silicon oxynitride film is used. When a silicon oxynitride film containing excess oxygen is used as the insulator 150A, oxygen can be supplied to the oxide 130B and characteristics can be improved. Further, since the insulator 150A is processed into the insulator 150 in a later step, the insulator 150A is preferably formed in consideration of the size of a transistor to be manufactured and the like.

Further, as the material of the insulator 150A, hafnium oxide, yttrium oxide, hafnium silicate (HfSi _x O _y (x> 0, y> 0)), hafnium silicate to which nitrogen is added (HfSi _x O _y N _Z (x> 0) , Y> 0, z> 0)), hafnium aluminate (HfAl _x O _y (x> 0, y> 0)), and high-k materials such as lanthanum oxide can also be used. Note that the insulator 150A may have a single-layer structure or a stacked structure.

The conductor 160A is formed by a sputtering method, an evaporation method, a CVD method, or the like. Note that the conductor 160A includes a metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film (titanium nitride film) containing the above-described element as a component. , Molybdenum nitride film, tungsten nitride film) or the like can be used. Further, as the conductor 160A, a semiconductor typified by polycrystalline silicon doped with an impurity element such as phosphorus, or silicide such as nickel silicide may be used. Or indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide A conductive material such as added indium tin oxide can also be used. Alternatively, a stacked structure of the conductive material and the metal material can be employed. For example, a stack of a 5 nm titanium film, a 10 nm titanium nitride film, and a 100 nm tungsten film can be formed.

Subsequently, part of the conductor 160A, the insulator 150A, and the oxide 130C is removed by CMP treatment or the like until the insulator 180 is exposed, so that the oxide 130c, the insulator 150, and the conductor 160 are formed (FIG. 15 (B)). At this time, the insulator 180 can also be used as a stopper layer, and the thickness of the insulator 180 may decrease.

The CMP process may be performed only once or a plurality of times. When performing the CMP process in a plurality of times, it is preferable to perform primary polishing at a low polishing rate after performing primary polishing at a high polishing rate. By combining polishing with different polishing rates in this way, the flatness of the polishing surface can be further improved.

Next, the insulator 181, the insulator 182, and the insulator 360 are formed over the transistor 100. For the method for manufacturing the insulator 181, the insulator 182, and the insulator 360, the insulator 280 can be referred to.

Next, a mask 195 is formed over the insulator 360 (FIG. 16A). After that, openings are provided in the insulator 360, the insulator 182, the insulator 181, the insulator 180, the insulator 120, the insulator 112, and the insulator 111 (FIG. 16B). Subsequently, after removing the mask 195, a mask 196 is formed (FIG. 17A). An opening is provided in the insulator 360 using the mask 196 (FIG. 17B).

Next, a conductor 307 and a conductor 308 are formed (FIG. 18A). For the manufacturing methods of the conductor 307 and the conductor 308, the conductor 301 and the conductor 302 can be referred to.

Next, the surface of the conductor is removed so as to be planarized, so that the wiring 310, the wiring 320, the wiring 330, and the wiring 350 are formed (see FIG. 18B). Here, as an example, the conductor 307 and the layer having tungsten as the conductor 308 are used, and the layer having silicon oxide is used as the insulator 360, whereby the conductor 307 and the conductor 308 are removed by a CMP method. In some cases, the etching rate of the insulator 360 may be reduced. Accordingly, the planarity of the surface of the insulator 360 may be improved. In addition, variation in the height of the wiring 310 and the like can be reduced in some cases.

According to this embodiment, a CMOS inverter can be manufactured with a small number of masks by replacing an n-channel Si transistor with an oxide semiconductor transistor without a complicated doping process. Therefore, productivity and yield can be increased. In addition, the degree of integration of the semiconductor device can be increased by forming the n-channel transistor above the p-channel transistor. Further, by forming the n-channel transistor above the p-channel transistor, the wiring routing distance can be shortened, and high-speed operation can be realized by reducing parasitic capacitance and resistance.

As described above, a transistor having stable electric characteristics and high operation speed can be provided even with a fine structure. Further, by using the transistor, a semiconductor device with high integration can be provided with less variation between transistors.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 5)
In this embodiment, a method for manufacturing a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. Note that the component denoted by the same reference numeral as the structure described in Embodiment 1 can refer to the semiconductor device described in Embodiment 1.

A method for manufacturing the semiconductor device illustrated in FIG. 5 is described with reference to FIGS. Here, a method for creating a hierarchy of levels 199 and higher will be described.

First, Embodiment Mode 4 can be referred to up to the step of forming the conductor 140A. After that, a mask 193 is formed (FIG. 19A). Subsequently, the conductor 140A is processed using the mask 193 to form the conductor 141, the conductor 142, and the conductor 140B. After that, the oxide 130A and the oxide 130B are processed using the conductor 141, the conductor 142, and the conductor 140B as a hard mask, and the oxide 130a, the oxide 131a, the oxide 132a, and the oxide 130b are oxidized. A material 131b and an oxide 132b are formed (FIG. 19B). For example, dry etching or the like may be used for processing.

Next, an insulator 180 is formed, and a mask 194 is formed (FIG. 20A). Subsequently, an opening is formed in the insulator 180. For example, dry etching or the like may be used for processing.

Subsequently, using the insulator 180 as a mask, a part of the conductor 140 is removed to form the conductor 140a and the conductor 140b, and at the same time, an opening is formed (FIG. 20B).

Next, the oxide 130C, the insulator 150A, and the conductor 160A are formed (FIG. 21A). Subsequently, part of the conductor 160A, the insulator 150A, and the oxide 130C is removed by CMP treatment or the like until the insulator 180 is exposed, so that the oxide 130c, the insulator 150, and the conductor 160 are formed (FIG. 21 (B)). At this time, the insulator 180 can also be used as a stopper layer, and the thickness of the insulator 180 may decrease.

Next, a mask 195 is formed (FIG. 22A). Next, openings are formed in the insulator 180, the conductor 141, the conductor 142, the oxide 131a, the oxide 132a, the oxide 131b, and the oxide 132b, and the conductor 313, the conductor 333, and the conductor 353 are formed. It is exposed (FIG. 22B). For example, dry etching or the like may be used for processing.

After that, after removing the mask 195, a mask 196 is formed (FIG. 23A). The opening of the insulator 180 is widened using the mask 196 (FIG. 23B). Subsequently, a conductor 307 and a conductor 308 are formed (FIG. 24A). Next, the surface of the conductor is removed so as to be planarized, so that a conductor 316, a conductor 336, and a conductor 356 are formed (see FIG. 24B).

Next, after an insulator 181, an insulator 182 and an insulator 360 are formed over the transistor 100, a mask 197 is formed (FIG. 25A). For the method for manufacturing the insulator 181, the insulator 182, and the insulator 360, the insulator 280 can be referred to.

Next, an opening is provided in the insulator 360, the insulator 182, and the insulator 181 using the mask 197. Subsequently, after the mask 197 is removed, another mask is formed, and an opening is provided in the insulator 360 using the mask. Next, a conductor is formed and removed so that the surface of the conductor is planarized, whereby the wiring 310, the wiring 320, the wiring 330, and the wiring 350 are formed (see FIG. 25B).

According to this embodiment, a CMOS inverter can be manufactured with a small number of masks by replacing an n-channel Si transistor with an oxide semiconductor transistor without a complicated doping process. Therefore, productivity and yield can be increased. In addition, the degree of integration of the semiconductor device can be increased by forming the n-channel transistor above the p-channel transistor. Further, by forming the n-channel transistor above the p-channel transistor, the wiring routing distance can be shortened, and high-speed operation can be realized by reducing parasitic capacitance and resistance.

As described above, a transistor having stable electric characteristics and high operation speed can be provided even with a fine structure. Further, by using the transistor, a semiconductor device with high integration can be provided with less variation between transistors.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 6)
In this embodiment, a method for manufacturing a semiconductor device of one embodiment of the present invention will be described with reference to FIGS. Note that the component denoted by the same reference numeral as the structure described in Embodiment 1 can refer to the semiconductor device described in Embodiment 1.

A method for manufacturing the semiconductor device illustrated in FIG. 5 is described with reference to FIGS. Here, a method for creating a hierarchy of levels 199 and higher will be described.

First, Embodiment Mode 4 can be referred to up to the step of forming the conductor 140A. After that, a mask 193 is formed (FIG. 26A). Subsequently, the conductor 140A is processed using the mask 193 to form the conductor 141, the conductor 142, and the conductor 140B. After that, the oxide 130A and the oxide 130B are processed using the conductor 141, the conductor 142, and the conductor 140B as a hard mask, and the oxide 130a, the oxide 131a, the oxide 132a, and the oxide 130b are oxidized. A material 131b and an oxide 132b are formed (FIG. 26B). For example, dry etching or the like may be used for processing.

Next, the insulator 180 is formed, and a mask 194 is formed (FIG. 27A). Subsequently, an opening is formed in the insulator 180. For example, dry etching or the like may be used for processing.

Subsequently, using the insulator 180 as a mask, the conductor 140 and a part of the conductor 142 are removed to form the conductor 140a and the conductor 140b, and at the same time, an opening is formed (FIG. 27B). ).

Next, the oxide 130C, the insulator 150A, and the conductor 160A are formed (FIG. 28A). Subsequently, part of the conductor 160A, the insulator 150A, and the oxide 130C is removed by CMP treatment or the like until the insulator 180 is exposed, so that the oxide 130c, the insulator 150, and the conductor 160 are formed (FIG. 28 (B)). At this time, the insulator 180 can also be used as a stopper layer, and the thickness of the insulator 180 may decrease.

Next, a mask 195 is formed (FIG. 29A). Next, openings are formed in the insulator 180, the conductor 141, the conductor 142, the oxide 131a, the oxide 132a, the oxide 131b, and the oxide 132b, and the conductor 313, the conductor 333, and the conductor 353 are formed. It is exposed (FIG. 29B). For example, dry etching or the like may be used for processing.

Next, a conductor 316, a conductor 336, and a conductor to be the conductor 356 are formed, and the conductor is removed so as to flatten the surface of the conductor, whereby the conductor 316 and the conductor 336 are formed. And a conductor 356 are formed (see FIG. 30A).

Next, after an insulator 181 and an insulator 360 are formed over the transistor 100, a mask 196 is formed (FIG. 30B). For the method for manufacturing the insulator 181 and the insulator 360, the insulator 280 can be referred to.

Next, openings are provided in the insulator 360, the insulator 181, and the insulator 180 using the mask 196. Here, when the opening is formed in the insulator 360, the insulator 181, and the insulator 180, dry etching, wet etching, or the like can be used. At the same time, part of the insulator 150 may be removed. Further, part of the oxide 130c may be removed by cleaning or the like after etching.

Note that in the formation of the opening, when the etching rates of the conductor 316, the conductor 336, and the conductor 356 are slower than the etching rate of the insulator 180, as shown in FIG. The conductor 316, the conductor 336, and the conductor 356 form a convex portion in the opening.

Next, after the mask 196 is removed, a conductor to be the wiring 310, the wiring 320, and the wiring 350 is formed, and the surface of the conductor is removed so as to be planarized, so that the wiring 310, the wiring 320, and the wiring are formed. 350 is formed (see FIG. 31B).

According to this embodiment mode, a semiconductor device with good contact characteristics can be manufactured without increasing the number of masks. Therefore, a highly productive semiconductor device can be provided.

Further, the CMOS inverter can be manufactured with a small number of masks by replacing the n-channel Si transistor with an oxide semiconductor transistor without a complicated doping process. Therefore, productivity and yield can be increased. In addition, the degree of integration of the semiconductor device can be increased by forming the n-channel transistor above the p-channel transistor. Further, by forming the n-channel transistor above the p-channel transistor, the wiring routing distance can be shortened, and high-speed operation can be realized by reducing parasitic capacitance and resistance.

As described above, a transistor having stable electric characteristics and high operation speed can be provided even with a fine structure. Further, by using the transistor, a semiconductor device with high integration can be provided with less variation between transistors.

The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, methods, and the like described in the other embodiments.

(Embodiment 7)
<Structure of oxide semiconductor>
Hereinafter, the structure of the oxide semiconductor is described.

An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. As the non-single-crystal oxide semiconductor, a CAAC-OS (c-axis-aligned crystal oxide semiconductor), a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), a pseudo-amorphous oxide semiconductor (a-like oxide semiconductor) : Amorphous-like oxide semiconductor) and amorphous oxide semiconductors.

From another point of view, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors. Examples of a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.

Amorphous structures are generally isotropic, have no heterogeneous structure, are metastable, have no fixed atomic arrangement, have a flexible bond angle, have short-range order, but long-range order It is said that it does not have.

That is, a stable oxide semiconductor cannot be called a complete amorphous oxide semiconductor. In addition, an oxide semiconductor that is not isotropic (for example, has a periodic structure in a minute region) cannot be called a complete amorphous oxide semiconductor. On the other hand, an a-like OS is not isotropic but has an unstable structure having a void (also referred to as a void). In terms of being unstable, a-like OS is physically close to an amorphous oxide semiconductor.

<CAAC-OS>
First, the CAAC-OS will be described.

A CAAC-OS is a kind of oxide semiconductor having a plurality of c-axis aligned crystal parts (also referred to as pellets).

A case where the CAAC-OS is analyzed by X-ray diffraction (XRD: X-Ray Diffraction) is described. For example, when CAAC-OS having an InGaZnO ₄ crystal classified into the space group R-3m is subjected to structural analysis by an out-of-plane method, a diffraction angle (2θ) as illustrated in FIG. Shows a peak near 31 °. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, in CAAC-OS, the crystal has a c-axis orientation, and the plane on which the c-axis forms a CAAC-OS film (formation target) It can also be confirmed that it faces a direction substantially perpendicular to the upper surface. In addition to the peak where 2θ is around 31 °, a peak may also appear when 2θ is around 36 °. The peak where 2θ is around 36 ° is attributed to the crystal structure classified into the space group Fd-3m. Therefore, the CAAC-OS preferably does not show the peak.

On the other hand, when structural analysis is performed on the CAAC-OS by an in-plane method in which X-rays are incident from a direction parallel to a formation surface, a peak appears at 2θ of around 56 °. This peak is attributed to the (110) plane of the InGaZnO ₄ crystal. Even when 2θ is fixed in the vicinity of 56 ° and the analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), as shown in FIG. No peak appears. On the other hand, when φ scan is performed with 2θ fixed at around 56 ° with respect to single crystal InGaZnO ₄ , six peaks attributed to a crystal plane equivalent to the (110) plane are observed as shown in FIG. Is done. Therefore, structural analysis using XRD can confirm that the CAAC-OS has irregular orientations in the a-axis and the b-axis.

Next, a CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including an InGaZnO ₄ crystal in parallel with a formation surface of the CAAC-OS, a diffraction pattern (restricted field of view) illustrated in FIG. Sometimes referred to as an electron diffraction pattern). This diffraction pattern includes spots caused by the (009) plane of the InGaZnO ₄ crystal. Therefore, electron diffraction shows that the pellets included in the CAAC-OS have c-axis alignment, and the c-axis is in a direction substantially perpendicular to the formation surface or the top surface. On the other hand, FIG. 33E shows a diffraction pattern obtained when an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. A ring-shaped diffraction pattern is confirmed from FIG. Therefore, it can be seen that the a-axis and the b-axis of the pellet included in the CAAC-OS have no orientation even by electron diffraction using an electron beam with a probe diameter of 300 nm. Note that the first ring in FIG. 33E is considered to be caused by the (010) plane and the (100) plane of the InGaZnO ₄ crystal. In addition, the second ring in FIG. 33E is considered to be due to the (110) plane and the like.

In addition, when a composite analysis image (also referred to as a high-resolution TEM image) of a bright field image and a diffraction pattern of a CAAC-OS is observed with a transmission electron microscope (TEM), a plurality of pellets are confirmed. Can do. On the other hand, even in a high-resolution TEM image, the boundary between pellets, that is, a crystal grain boundary (also referred to as a grain boundary) may not be clearly confirmed. Therefore, it can be said that the CAAC-OS does not easily lower the electron mobility due to the crystal grain boundary.

FIG. 34A shows a high-resolution TEM image of a cross section of the CAAC-OS observed from a direction substantially parallel to the sample surface. For observation of the high-resolution TEM image, a spherical aberration correction function was used. A high-resolution TEM image using the spherical aberration correction function is particularly referred to as a Cs-corrected high-resolution TEM image. The Cs-corrected high resolution TEM image can be observed, for example, with an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

FIG. 34A shows a pellet that is a region where metal atoms are arranged in a layered manner. It can be seen that the size of one pellet is 1 nm or more and 3 nm or more. Therefore, the pellet can also be referred to as a nanocrystal (nc). In addition, the CAAC-OS can be referred to as an oxide semiconductor including CANC (C-Axis aligned nanocrystals). The pellet reflects the unevenness of the surface or top surface of the CAAC-OS film, and is parallel to the surface or top surface of the CAAC-OS.

34B and 34C show Cs-corrected high-resolution TEM images of the plane of the CAAC-OS observed from the direction substantially perpendicular to the sample surface. FIGS. 34D and 34E are images obtained by performing image processing on FIGS. 34B and 34C, respectively. Hereinafter, an image processing method will be described. First, an FFT image is obtained by performing Fast Fourier Transform (FFT) processing on FIG. Then, relative to the origin in the FFT image acquired, for masking leaves a range between 5.0 nm ^-1 from 2.8 nm ^-1. Next, the FFT-processed mask image is subjected to an inverse fast Fourier transform (IFFT) process to obtain an image-processed image. The image acquired in this way is called an FFT filtered image. The FFT filtered image is an image obtained by extracting periodic components from the Cs-corrected high-resolution TEM image, and shows a lattice arrangement.

In FIG. 34D, the portion where the lattice arrangement is disturbed is indicated by a broken line. A region surrounded by a broken line is one pellet. And the location shown with the broken line is the connection part of a pellet and a pellet. Since the broken line has a hexagonal shape, it can be seen that the pellet has a hexagonal shape. In addition, the shape of a pellet is not necessarily a regular hexagonal shape, and is often a non-regular hexagonal shape.

In FIG. 34 (E), a portion where the orientation of the lattice arrangement changes between a region where the lattice arrangement is aligned and a region where another lattice arrangement is aligned is indicated by a dotted line, and the change in the orientation of the lattice arrangement is shown. It is indicated by a broken line. A clear crystal grain boundary cannot be confirmed even in the vicinity of the dotted line. A distorted hexagon can be formed by connecting the surrounding lattice points around the lattice points near the dotted line. That is, it can be seen that the formation of crystal grain boundaries is suppressed by distorting the lattice arrangement. This is because the CAAC-OS can tolerate distortion due to the fact that the atomic arrangement is not dense in the ab plane direction and the bond distance between atoms changes due to substitution of metal elements. Conceivable.

As described above, the CAAC-OS has a c-axis alignment and a crystal structure in which a plurality of pellets (nanocrystals) are connected in the ab plane direction to have a strain. Therefore, the CAAC-OS can also be referred to as CAAcrystal (c-axis-aligned a-b-plane-anchored crystal).

The CAAC-OS is an oxide semiconductor with high crystallinity. Since the crystallinity of an oxide semiconductor may be deteriorated by entry of impurities, generation of defects, or the like, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

Note that the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element such as silicon, which has a stronger bonding force with oxygen than a metal element included in an oxide semiconductor, disturbs the atomic arrangement of the oxide semiconductor by depriving the oxide semiconductor of oxygen, thereby reducing crystallinity. It becomes a factor. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radii (or molecular radii), which disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity.

In the case where an oxide semiconductor has impurities or defects, characteristics may fluctuate due to light, heat, or the like. For example, an impurity contained in the oxide semiconductor might serve as a carrier trap or a carrier generation source. For example, oxygen vacancies in the oxide semiconductor may serve as carrier traps or may serve as carrier generation sources by capturing hydrogen.

A CAAC-OS with few impurities and oxygen vacancies is an oxide semiconductor with low carrier density. Specifically, less than 8 × ^{10 11} atoms / cm ^3, preferably 1 × ¹⁰ 11 / cm less than ^3, more preferably less than 1 × ^{10 10} atoms / cm ^3, 1 × ^{10 -9} / cm ³ or An oxide semiconductor having the above carrier density can be obtained. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. The CAAC-OS has a low impurity concentration and a low density of defect states. That is, it can be said that the oxide semiconductor has stable characteristics.

<Nc-OS>
Next, the nc-OS will be described.

A case where the nc-OS is analyzed by XRD will be described. For example, when structural analysis is performed on the nc-OS by an out-of-plane method, a peak indicating orientation does not appear. That is, the nc-OS crystal has no orientation.

For example, when an nc-OS including an InGaZnO ₄ crystal is thinned and an electron beam with a probe diameter of 50 nm is incident on a region with a thickness of 34 nm parallel to the surface to be formed, FIG. A ring-shaped diffraction pattern (nanobeam electron diffraction pattern) as shown is observed. FIG. 35B shows a diffraction pattern (nanobeam electron diffraction pattern) obtained when an electron beam with a probe diameter of 1 nm is incident on the same sample. From FIG. 35B, a plurality of spots are observed in the ring-shaped region. Therefore, nc-OS does not confirm order when an electron beam with a probe diameter of 50 nm is incident, but confirms order when an electron beam with a probe diameter of 1 nm is incident.

Further, when an electron beam having a probe diameter of 1 nm is incident on a region having a thickness of less than 10 nm, an electron diffraction pattern in which spots are arranged in a substantially regular hexagonal shape is observed as shown in FIG. There is a case. Therefore, it can be seen that the nc-OS has a highly ordered region, that is, a crystal in a thickness range of less than 10 nm. Note that there are some regions where a regular electron diffraction pattern is not observed because the crystal faces in various directions.

FIG. 35D shows a Cs-corrected high-resolution TEM image of a cross section of the nc-OS observed from a direction substantially parallel to the formation surface. The nc-OS has a region in which a crystal part can be confirmed, such as a portion indicated by an auxiliary line, and a region in which a clear crystal part cannot be confirmed in a high-resolution TEM image. A crystal part included in the nc-OS has a size of 1 nm to 10 nm, particularly a size of 1 nm to 3 nm in many cases. Note that an oxide semiconductor in which the size of a crystal part is greater than 10 nm and less than or equal to 100 nm is sometimes referred to as a microcrystalline oxide semiconductor. For example, the nc-OS may not be able to clearly confirm a crystal grain boundary in a high-resolution TEM image. Note that the nanocrystal may have the same origin as the pellet in the CAAC-OS. Therefore, the crystal part of nc-OS is sometimes referred to as a pellet below.

Thus, the nc-OS has a periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS has no regularity in crystal orientation between different pellets. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.

Note that since the crystal orientation is not regular between pellets (nanocrystals), nc-OS is an oxide semiconductor having RANC (Random Aligned Nanocrystals), or an oxide having NANC (Non-Aligned nanocrystals). It can also be called a semiconductor.

The nc-OS is an oxide semiconductor that has higher regularity than an amorphous oxide semiconductor. Therefore, the nc-OS has a lower density of defect states than an a-like OS or an amorphous oxide semiconductor. Note that the nc-OS does not have regularity in crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

<A-like OS>
The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor.

FIG. 36 shows a high-resolution cross-sectional TEM image of the a-like OS. Here, FIG. 36A is a high-resolution cross-sectional TEM image of the a-like OS at the start of electron irradiation. FIG. 36B is a high-resolution cross-sectional TEM image of the a-like OS after irradiation with electrons (e ⁻ ) of 4.3 × 10 ⁸ e ⁻ / nm ² . From FIG. 36A and FIG. 36B, it can be seen that the a-like OS observes a striped bright region extending in the vertical direction from the start of electron irradiation. It can also be seen that the shape of the bright region changes after electron irradiation. The bright region is assumed to be a void or a low density region.

Since it has a void, the a-like OS has an unstable structure. Hereinafter, in order to show that the a-like OS has an unstable structure as compared with the CAAC-OS and the nc-OS, changes in the structure due to electron irradiation are shown.

As samples, a-like OS, nc-OS, and CAAC-OS are prepared. Each sample is an In—Ga—Zn oxide.

First, a high-resolution cross-sectional TEM image of each sample is acquired. Each sample has a crystal part by a high-resolution cross-sectional TEM image.

Note that a unit cell of an InGaZnO ₄ crystal has a structure in which three In—O layers and six Ga—Zn—O layers have a total of nine layers stacked in the c-axis direction. Are known. The spacing between these adjacent layers is about the same as the lattice spacing (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, in the following, a portion where the interval between lattice fringes is 0.28 nm or more and 0.30 nm or less is regarded as a crystal part of InGaZnO ₄ . Note that the lattice fringes correspond to the ab plane of the InGaZnO ₄ crystal.

FIG. 37 shows an example in which the average size of the crystal parts (22 to 30 locations) of each sample was investigated. Note that the length of the lattice stripes described above is the size of the crystal part. From FIG. 37, it can be seen that in the a-like OS, the crystal part becomes larger in accordance with the cumulative dose of electrons related to the acquisition of the TEM image and the like. From FIG. 37, the crystal part (also referred to as the initial nucleus), which was about 1.2 nm in the initial observation by TEM, has a cumulative electron (e ⁻ ) irradiation dose of 4.2 × 10 ⁸ e ⁻ / nm. ^{In FIG. 2} , it can be seen that the crystal has grown to a size of about 1.9 nm. On the other hand, in the nc-OS and the CAAC-OS, there is no change in the size of the crystal part in the range of the cumulative electron dose from the start of electron irradiation to 4.2 × 10 ⁸ e ⁻ / nm ^2. I understand. FIG. 37 indicates that the crystal part sizes of the nc-OS and the CAAC-OS are approximately 1.3 nm and 1.8 nm, respectively, regardless of the cumulative electron dose. Note that a Hitachi transmission electron microscope H-9000NAR was used for electron beam irradiation and TEM observation. The electron beam irradiation conditions were an acceleration voltage of 300 kV, a current density of 6.7 × 10 ⁵ e ⁻ / (nm ² · s), and an irradiation region diameter of 230 nm.

As described above, in the a-like OS, a crystal part may be grown by electron irradiation. On the other hand, in the nc-OS and the CAAC-OS, the crystal part is hardly grown by electron irradiation. That is, it can be seen that the a-like OS has an unstable structure compared to the nc-OS and the CAAC-OS.

In addition, since it has a void, the a-like OS has a lower density than the nc-OS and the CAAC-OS. Specifically, the density of the a-like OS is 78.6% or more and less than 92.3% of the density of the single crystal having the same composition. Further, the density of the nc-OS and the density of the CAAC-OS are 92.3% or more and less than 100% of the density of the single crystal having the same composition. An oxide semiconductor having a density of less than 78% of the single crystal is difficult to form.

For example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of single crystal InGaZnO ₄ having a rhombohedral structure is 6.357 g / cm ³ . Thus, for example, in an oxide semiconductor that satisfies In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of a-like OS is 5.0 g / cm ³ or more and less than 5.9 g / cm ^3. . For example, in the oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of the nc-OS and the density of the CAAC-OS is 5.9 g / cm ³ or more and 6.3 g / less than cm ³ .

Note that when single crystals having the same composition do not exist, it is possible to estimate a density corresponding to a single crystal having a desired composition by combining single crystals having different compositions at an arbitrary ratio. What is necessary is just to estimate the density corresponding to the single crystal of a desired composition using a weighted average with respect to the ratio which combines the single crystal from which a composition differs. However, the density is preferably estimated by combining as few kinds of single crystals as possible.

As described above, oxide semiconductors have various structures and various properties. Note that the oxide semiconductor may be a stacked film including two or more of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example.

(Embodiment 8)
In this embodiment, an example of a CPU including a transistor according to one embodiment of the present invention and a semiconductor device such as the memory device described above will be described.

<Configuration of CPU>
FIG. 38 is a block diagram illustrating a configuration example of a CPU in which some of the transistors described above are used.

38 includes an ALU 1191 (ALU: arithmetic logic unit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, and a bus interface 1198. A rewritable ROM 1199 and a ROM interface 1189. As the substrate 1190, a semiconductor substrate, an SOI substrate, a glass substrate, or the like is used. The ROM 1199 and the ROM interface 1189 may be provided in separate chips. Needless to say, the CPU illustrated in FIG. 38 is just an example in which the configuration is simplified, and an actual CPU may have various configurations depending on the application. For example, the configuration including the CPU or the arithmetic circuit illustrated in FIG. 38 may be a single core, and a plurality of the cores may be included, and each core may operate in parallel. Further, the number of bits that the CPU can handle with the internal arithmetic circuit or the data bus can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, or the like.

Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195.

The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. The interrupt controller 1194 determines and processes an interrupt request from an external input / output device or a peripheral circuit from the priority or mask state during execution of the CPU program. The register controller 1197 generates an address of the register 1196, and reads and writes the register 1196 according to the state of the CPU.

In addition, the timing controller 1195 generates a signal for controlling the operation timing of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal based on the reference clock signal, and supplies the internal clock signal to the various circuits.

In the CPU illustrated in FIG. 38, a memory cell is provided in the register 1196. As the memory cell of the register 1196, the above-described transistor, memory device, or the like can be used.

In the CPU shown in FIG. 38, the register controller 1197 selects a holding operation in the register 1196 in accordance with an instruction from the ALU 1191. That is, whether to hold data by a flip-flop or to hold data by a capacitor in a memory cell included in the register 1196 is selected. When data retention by the flip-flop is selected, the power supply voltage is supplied to the memory cell in the register 1196. When holding of data in the capacitor is selected, data is rewritten to the capacitor and supply of power supply voltage to the memory cells in the register 1196 can be stopped.

FIG. 39 is an example of a circuit diagram of a memory element 1200 that can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatilized by power-off, a circuit 1202 in which stored data is not volatilized by power-off, a switch 1203, a switch 1204, a logic element 1206, a capacitor 1207, and a selection function. A circuit 1220. The circuit 1202 includes a capacitor 1208, a transistor 1209, and a transistor 1210. Note that the memory element 1200 may further include other elements such as a diode, a resistance element, and an inductor, as necessary.

Here, the memory device described above can be used for the circuit 1202. When supply of power supply voltage to the memory element 1200 is stopped, GND (0 V) or a potential at which the transistor 1209 is turned off is continuously input to the gate of the transistor 1209 of the circuit 1202. For example, the gate of the transistor 1209 is grounded through a load such as a resistor.

The switch 1203 is configured using a transistor 1213 of one conductivity type (eg, n-channel type), and the switch 1204 is configured using a transistor 1214 of conductivity type (eg, p-channel type) opposite to the one conductivity type. An example is shown. Here, the first terminal of the switch 1203 corresponds to one of the source and the drain of the transistor 1213, the second terminal of the switch 1203 corresponds to the other of the source and the drain of the transistor 1213, and the switch 1203 corresponds to the gate of the transistor 1213. In accordance with the control signal RD input to the second terminal, conduction or non-conduction between the first terminal and the second terminal (that is, the conduction state or non-conduction state of the transistor 1213) is selected. The first terminal of the switch 1204 corresponds to one of the source and the drain of the transistor 1214, the second terminal of the switch 1204 corresponds to the other of the source and the drain of the transistor 1214, and the switch 1204 is input to the gate of the transistor 1214. The control signal RD selects the conduction or non-conduction between the first terminal and the second terminal (that is, the conduction state or non-conduction state of the transistor 1214).

One of a source and a drain of the transistor 1209 is electrically connected to one of a pair of electrodes of the capacitor 1208 and a gate of the transistor 1210. Here, the connection part is referred to as a node M2. One of a source and a drain of the transistor 1210 is electrically connected to a wiring that can supply a low power supply potential (eg, a GND line), and the other is connected to the first terminal of the switch 1203 (the source and the drain of the transistor 1213 On the other hand). A second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is electrically connected to a first terminal of the switch 1204 (one of the source and the drain of the transistor 1214). A second terminal of the switch 1204 (the other of the source and the drain of the transistor 1214) is electrically connected to a wiring that can supply the power supply potential VDD. A second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213), a first terminal of the switch 1204 (one of a source and a drain of the transistor 1214), an input terminal of the logic element 1206, and the capacitor 1207 One of the pair of electrodes is electrically connected. Here, the connection part is referred to as a node M1. The other of the pair of electrodes of the capacitor 1207 can be configured to receive a constant potential. For example, a low power supply potential (such as GND) or a high power supply potential (such as VDD) can be input. The other of the pair of electrodes of the capacitor 1207 is electrically connected to a wiring (eg, a GND line) that can supply a low power supply potential. The other of the pair of electrodes of the capacitor 1208 can have a constant potential. For example, a low power supply potential (such as GND) or a high power supply potential (such as VDD) can be input. The other of the pair of electrodes of the capacitor 1208 is electrically connected to a wiring (eg, a GND line) that can supply a low power supply potential.

Note that the capacitor 1207 and the capacitor 1208 can be omitted by positively using a parasitic capacitance of a transistor or a wiring.

A control signal WE is input to the gate of the transistor 1209. The switch 1203 and the switch 1204 are selected to be in a conductive state or a non-conductive state between the first terminal and the second terminal by a control signal RD different from the control signal WE. When the terminals of the other switch are in a conductive state, the first terminal and the second terminal of the other switch are in a non-conductive state.

A signal corresponding to data held in the circuit 1201 is input to the other of the source and the drain of the transistor 1209. FIG. 39 illustrates an example in which the signal output from the circuit 1201 is input to the other of the source and the drain of the transistor 1209. A signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is an inverted signal obtained by inverting the logic value by the logic element 1206 and is input to the circuit 1201 through the circuit 1220. .

Note that FIG. 39 illustrates an example in which a signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is input to the circuit 1201 through the logic element 1206 and the circuit 1220. It is not limited to. A signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) may be input to the circuit 1201 without inversion of the logical value. For example, when there is a node in the circuit 1201 that holds a signal in which the logical value of the signal input from the input terminal is inverted, the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) An output signal can be input to the node.

In FIG. 39, among the transistors used for the memory element 1200, a transistor other than the transistor 1209 can be a transistor in which a channel is formed in a film or a substrate 1190 made of a semiconductor other than an oxide semiconductor. For example, a transistor in which a channel is formed in a silicon film or a silicon substrate can be used. Further, all the transistors used for the memory element 1200 can be transistors whose channels are formed using an oxide semiconductor. Alternatively, the memory element 1200 may include a transistor whose channel is formed using an oxide semiconductor in addition to the transistor 1209, and the remaining transistors are formed using a semiconductor layer other than the oxide semiconductor or the substrate 1190. It can also be a transistor.

As the circuit 1201 in FIG. 39, for example, a flip-flop circuit can be used. As the logic element 1206, for example, an inverter, a clocked inverter, or the like can be used.

In the semiconductor device according to one embodiment of the present invention, data stored in the circuit 1201 can be held by the capacitor 1208 provided in the circuit 1202 while the power supply voltage is not supplied to the memory element 1200.

In addition, a transistor in which a channel is formed in an oxide semiconductor has extremely low off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor is significantly lower than the off-state current of a transistor in which a channel is formed in crystalline silicon. Therefore, by using the transistor as the transistor 1209, the signal held in the capacitor 1208 is maintained for a long time even when the power supply voltage is not supplied to the memory element 1200. In this manner, the memory element 1200 can hold stored data (data) even while the supply of power supply voltage is stopped.

Further, by providing the switch 1203 and the switch 1204, the memory element is characterized by performing a precharge operation; therefore, after the supply of power supply voltage is resumed, the time until the circuit 1201 retains the original data again is shortened. be able to.

In the circuit 1202, the signal held by the capacitor 1208 is input to the gate of the transistor 1210. Therefore, after the supply of the power supply voltage to the memory element 1200 is restarted, the signal held by the capacitor 1208 is converted into the state of the transistor 1210 (a conductive state or a non-conductive state) and read from the circuit 1202 Can do. Therefore, the original signal can be accurately read even if the potential corresponding to the signal held in the capacitor 1208 slightly fluctuates.

By using such a storage element 1200 for a storage device such as a register or a cache memory included in the processor, loss of data in the storage device due to stop of supply of power supply voltage can be prevented. In addition, after the supply of the power supply voltage is resumed, the state before the power supply stop can be restored in a short time. Accordingly, power can be stopped in a short time in the entire processor or in one or a plurality of logic circuits constituting the processor, so that power consumption can be suppressed.

Although the memory element 1200 has been described as an example of use for a CPU, the memory element 1200 can be applied to an LSI such as a DSP (Digital Signal Processor), a custom LSI, or an RF (Radio Frequency) device. The present invention can also be applied to LSI and RF (Radio Frequency) devices such as programmable logic circuits (PLD) such as FPGA (Field Programmable Gate Array) and CPLD (Complex PLD).

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

(Embodiment 9)
In this embodiment, electronic devices using a transistor or the like according to one embodiment of the present invention will be described.

<Electronic equipment>
A semiconductor device according to one embodiment of the present invention includes a display device, a personal computer, and an image reproducing device including a recording medium (typically a display that can reproduce a recording medium such as a DVD: Digital Versatile Disc and display the image) Device). In addition, as an electronic device in which the semiconductor device according to one embodiment of the present invention can be used, a mobile phone, a game machine including a portable type, a portable data terminal, an electronic book terminal, a video camera, a digital still camera, or the like, goggles Type displays (head-mounted displays), navigation systems, sound playback devices (car audio, digital audio players, etc.), copiers, facsimiles, printers, multifunction printers, automated teller machines (ATMs), vending machines, etc. It is done. Specific examples of these electronic devices are shown in FIGS.

FIG. 40A illustrates a portable game machine including a housing 901, a housing 902, a display portion 903, a display portion 904, a microphone 905, a speaker 906, operation keys 907, a stylus 908, and the like. Note that although the portable game machine illustrated in FIG. 40A includes the two display portions 903 and 904, the number of display portions included in the portable game device is not limited thereto.

FIG. 40B illustrates a portable data terminal, which includes a first housing 911, a second housing 912, a first display portion 913, a second display portion 914, a connection portion 915, operation keys 916, and the like. The first display unit 913 is provided in the first housing 911, and the second display unit 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected by the connection portion 915, and the angle between the first housing 911 and the second housing 912 can be changed by the connection portion 915. is there. It is good also as a structure which switches the image | video in the 1st display part 913 according to the angle between the 1st housing | casing 911 and the 2nd housing | casing 912 in the connection part 915. FIG. In addition, a display device in which a function as a position input device is added to at least one of the first display portion 913 and the second display portion 914 may be used. Note that the function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can be added by providing a photoelectric conversion element called a photosensor in a pixel portion of a display device.

FIG. 40C illustrates a laptop personal computer, which includes a housing 921, a display portion 922, a keyboard 923, a pointing device 924, and the like.

FIG. 40D illustrates an electric refrigerator-freezer, which includes a housing 931, a refrigerator door 932, a refrigerator door 933, and the like.

FIG. 40E illustrates a video camera, which includes a first housing 941, a second housing 942, a display portion 943, operation keys 944, a lens 945, a connection portion 946, and the like. The operation key 944 and the lens 945 are provided in the first housing 941, and the display portion 943 is provided in the second housing 942. The first housing 941 and the second housing 942 are connected by a connection portion 946, and the angle between the first housing 941 and the second housing 942 can be changed by the connection portion 946. is there. It is good also as a structure which switches the image | video in the display part 943 according to the angle between the 1st housing | casing 941 and the 2nd housing | casing 942 in the connection part 946. FIG.

FIG. 40F illustrates a passenger car that includes a car body 951, wheels 952, a dashboard 953, lights 954, and the like.

The structure described in this embodiment can be combined as appropriate with any of the structures described in the other embodiments.

Note that one embodiment of the present invention has been described in the above embodiment. Note that one embodiment of the present invention is not limited thereto. In other words, in the present embodiment and the like, various aspects of the invention are described, and thus one embodiment of the present invention is not limited to a particular embodiment. For example, although an example in which the channel formation region, the source region, the drain region, and the like of the transistor include an oxide semiconductor is described as one embodiment of the present invention, one embodiment of the present invention is not limited thereto. In some cases or depending on circumstances, various transistors in one embodiment of the present invention, a channel formation region of the transistor, a source region, a drain region, and the like of the transistor may include various semiconductors. Depending on circumstances or circumstances, various transistors in one embodiment of the present invention, a channel formation region of the transistor, a source region, a drain region, and the like of the transistor can be formed using, for example, silicon, germanium, silicon germanium, or silicon carbide. Gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor may be included. Alternatively, for example, depending on circumstances or circumstances, various transistors, channel formation regions of the transistors, source regions and drain regions of the transistors do not include an oxide semiconductor in one embodiment of the present invention. May be.

1 Structure 2 Structure 3 Structure 4 Structure 5 Structure 6 Structure 9 Total 11 Region 100 Transistor 101 Structure 102 Structure 104a Conductor 110 Insulator 111 Insulator 112 Insulator 120 Insulator 130 Oxide 130a Oxide 130A Oxide 130b Oxidation 130b Oxidation 130B oxide 130c oxide 130C oxide 131a oxide 131b oxide 132a oxide 132b oxide 140 conductor 140a conductor 140A conductor 140b conductor 140B conductor 141 conductor 142 conductor 150 insulator 150A insulator 156 Conductor 160 Conductor 160A Conductor 165 Conductor 180 Insulator 180A Insulator 181 Insulator 182 Insulator 191 Mask 192 Mask 193 Mask 194 Mask 195 Mask 196 Mask 197 Mask 199 Layer 200 Transition 201 Semiconductor substrate 210 Region 240a Region 240b Region 250 Insulator 255 Insulator 260 Conductor 280 Insulator 281 Insulator 282 Insulator 291 Mask 299 Hierarchy 301 Conductor 302 Conductor 303 Conductor 304 Conductor 307 Conductor 308 Conductor 310 wiring 311 conductor 312 conductor 313 conductor 316 conductor 320 wiring 321 conductor 330 wiring 331 conductor 332 conductor 333 conductor 336 conductor 340 wiring 350 wiring 351 conductor 352 conductor 353 conductor 356 conductor 360 Insulator 399 Hierarchy 901 Case 902 Case 903 Display portion 904 Display portion 905 Microphone 906 Speaker 907 Operation key 908 Stylus 911 Case 912 Case 913 Display portion 914 Display portion 915 Connection portion 916 Operation key 92 Enclosure 922 Display unit 923 Keyboard 924 Pointing device 931 Enclosure 932 Refrigeration room door 933 Freezer compartment door 941 Enclosure 942 Enclosure 943 Display unit 944 Operation key 945 Lens 946 Connection unit 951 Car body 952 Wheel 953 Dashboard 954 Light 1189 ROM interface 1190 board 1191 ALU
1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM
1200 memory element 1201 circuit 1202 circuit 1203 switch 1204 switch 1206 logic element 1207 capacitor element 1208 capacitor element 1209 transistor 1210 transistor 1213 transistor 1214 transistor 1220 circuit

Claims (6)

A first transistor, a second transistor, a first wiring, a second wiring, a third wiring, a first conductor, a second conductor, and a third conductor; , A fourth conductor, a fifth conductor, and a sixth conductor,
The first transistor has a first terminal, a second terminal, and a first gate terminal;
The second transistor has a third terminal, a fourth terminal, and a second gate terminal;
The first terminal is electrically connected to the first wiring through the first conductor, the third terminal, and the fourth conductor;
The second terminal is electrically connected to the second wiring through the second conductor and the fifth conductor,
The first gate terminal is electrically connected to the second gate terminal via the third conductor, the sixth conductor, and the third wiring;
The first conductor is disposed on the first terminal;
The third terminal is disposed on the first conductor;
The fourth conductor passes through the third terminal and is disposed on the first conductor;
The first wiring is disposed on the fourth conductor;
The second conductor is disposed on the second terminal;
The fifth conductor is disposed on the second conductor;
The second wiring is disposed on the fifth conductor;
The third conductor is disposed on the first gate wiring;
The sixth conductor is disposed on the third conductor;
The semiconductor device, wherein the third wiring is disposed on the sixth conductor. A first transistor, a second transistor, a first wiring, a second wiring, a third wiring, a first conductor, a second conductor, and a third conductor; , A fourth conductor, a fifth conductor, a sixth conductor, a first structure, and a second structure,
The first transistor has a first terminal, a second terminal, and a first gate terminal;
The second transistor has a third terminal, a fourth terminal, and a second gate terminal;
The first terminal is electrically connected to the first wiring through the first conductor, the third terminal, and the fourth conductor;
The second terminal is electrically connected to the second wiring through the second conductor and the fifth conductor,
The first gate terminal is electrically connected to the second gate terminal via the third conductor, the sixth conductor, and the third wiring;
The first conductor is disposed on the first terminal;
The third terminal is disposed on the first conductor;
The fourth conductor passes through the third terminal and is disposed on the first conductor;
The first wiring is disposed on the fourth conductor;
The second conductor is disposed on the second terminal;
The fifth conductor penetrates the first structure and is disposed on the second conductor;
The second wiring is disposed on the fifth conductor and the first structure,
The third conductor is disposed on the first gate wiring;
The sixth conductor penetrates the second structure and is disposed on the third conductor;
The semiconductor device, wherein the third wiring is disposed on the sixth conductor and the second structure. A first transistor, a second transistor, a first wiring, a second wiring, a third wiring, a first conductor, a second conductor, and a third conductor; , A fourth conductor, a fifth conductor, a sixth conductor, a first structure, and a second structure,
The first transistor has a first terminal, a second terminal, and a first gate terminal;
The second transistor has a third terminal, a fourth terminal, and a second gate terminal;
The first terminal is electrically connected to the first wiring through the first conductor, the third terminal, and the fourth conductor;
The second terminal is electrically connected to the second wiring through the second conductor and the fifth conductor,
The first gate terminal is electrically connected to the second gate terminal via the third conductor, the sixth conductor, and the third wiring;
The first conductor is disposed on the first terminal;
The fourth conductor passes through the third terminal and is disposed on the first conductor;
The first wiring is in contact with a side surface of the fourth conductor;
The second conductor is disposed on the second terminal;
The fifth conductor penetrates the first structure and is disposed on the second conductor;
The second wiring is in contact with a side surface of the fifth conductor;
The second wiring is disposed on the first structure,
The third conductor is disposed on the first gate wiring;
The sixth conductor penetrates the second structure and is disposed on the third conductor;
The third wiring is in contact with a side surface of the sixth conductor;
The semiconductor device, wherein the second wiring is disposed on the second structure. In claim 2 or claim 3,
The first structure has a first oxide and a sixth conductor,
The semiconductor device, wherein the second structure body includes a second oxide and a seventh conductor. In any one of Claim 1 thru | or 3,
The semiconductor device, wherein the second transistor includes an oxide semiconductor. An electronic apparatus comprising the semiconductor device according to claim 1.

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