JPWO2016079639A1 - Semiconductor device, circuit board, and electronic equipment - Google Patents

Abstract

A novel semiconductor device, a semiconductor device with low power consumption, or a semiconductor device whose area can be reduced is provided. An internal circuit; an input / output terminal; a signal line; a power line; a resistor; a first transistor; and a control signal generation circuit. The internal circuit is connected to the input / output terminal via the signal line. Electrically connected, the first terminal of the first transistor is electrically connected to the power supply line, and the second terminal of the first transistor is electrically connected to the first terminal of the resistor portion. The second terminal of the resistor portion is electrically connected to the signal line, the control signal generation circuit is electrically connected to the gate of the first transistor, and the resistor portion and the first transistor are oxide semiconductors. Have

Description

One embodiment of the present invention relates to a semiconductor device, a circuit board, and an electronic device.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, machine, manufacture or composition (composition of matter). Alternatively, one embodiment of the present invention relates to a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an imaging device, a driving method thereof, or a manufacturing method thereof.

In a semiconductor device such as an integrated circuit (IC) or a display device, a pull-up (or pull-down) resistor is used to prevent the input / output terminals of the circuit from becoming unstable. For example, a technique using gate polysilicon as a pull-up (or pull-down) resistor of a CMOS inverter is disclosed (see Patent Document 1).

Japanese Patent Laid-Open No. 11-274440

For example, in a CMOS circuit, the pull-up (or pull-down) resistor may require a very large resistance value of several kilo Ω to several mega Ω. As shown in Patent Document 1 described above, when polysilicon is used as a resistor in a gate array semiconductor circuit device, the area occupied by the polysilicon is increased, which increases the cell size.

In addition, an IC having a pull-up (or pull-down) resistor has a problem in that power consumption increases because a current of about several μA always flows while a signal is input to or output from the input / output terminal.

Further, as described above, an IC having a pull-up (or pull-down) resistor increases power consumption. For this reason, in order to suppress this power consumption and make an IC with lower power consumption, a switch for disconnecting a pull-up (or pull-down) resistor may be provided after the IC starts stable operation. The switch can be mainly formed of a transistor. However, even when the transistor is turned off and the switch is disconnected, an off-leakage current flows, so that an increase in power consumption is observed.

Thus, an object of one embodiment of the present invention is to provide a novel semiconductor device, circuit board, or electronic device. Another object of one embodiment of the present invention is to reduce a layout area or provide a structure that can realize the layout area. Another object of one embodiment of the present invention is to prevent a constant current from being generated or to provide a structure capable of realizing the same. Another object of one embodiment of the present invention is to reduce power consumption or provide a structure that can realize the power consumption. Alternatively, according to one embodiment of the present invention, it is an object to shorten a time during which a through current is generated or to provide a structure capable of realizing the same.

Note that one embodiment of the present invention does not necessarily have to solve all of the problems described above, and may be one that can solve at least one problem. Further, the description of the above problem does not disturb the existence of other problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other issues from the description of the specification, drawings, claims, etc. .

One embodiment of the present invention includes an internal circuit, an input / output terminal, a signal line, a power supply line, a resistance portion, a first transistor, and a control signal generation circuit. The first terminal of the first transistor is electrically connected to the power supply line, and the second terminal of the first transistor is connected to the first of the resistor section. The second terminal of the resistor portion is electrically connected to the signal line, and the control signal generation circuit is electrically connected to the gate of the first transistor. The transistor is a semiconductor device including an oxide semiconductor.

One embodiment of the present invention includes an internal circuit, an input / output terminal, a signal line, a power supply line, a resistance portion, a first transistor, and a control signal generation circuit. And the first terminal of the first transistor is electrically connected to the second terminal of the resistor portion, and the second terminal of the first transistor is connected to the signal terminal. The first terminal of the resistor portion is electrically connected to the power supply line, and the control signal generation circuit is electrically connected to the gate of the first transistor. The transistor is a semiconductor device including an oxide semiconductor.

One embodiment of the present invention includes an internal circuit, an input / output terminal, a signal line, a power supply line, a first transistor, and a control signal generation circuit. The internal circuit is input via the signal line. The output terminal is electrically connected, the first terminal of the first transistor is electrically connected to the power supply line, the second terminal of the first transistor is electrically connected to the signal line, and is controlled The signal generation circuit is electrically connected to the gate of the first transistor, and the first transistor is a semiconductor device including an oxide semiconductor.

Another embodiment of the present invention includes the above semiconductor device and a second transistor, and the control signal generation circuit is electrically connected to the first terminal of the second transistor. The second terminal of the transistor is electrically connected to the gate of the first transistor, and the second transistor is a semiconductor device including an oxide semiconductor.

Another embodiment of the present invention includes the above semiconductor device and a capacitor, and the capacitor is electrically connected to the second terminal of the second transistor and the gate of the first transistor. This is a semiconductor device.

Further, the control signal generation circuit and the gate of the second transistor may be electrically connected. The gate of the second transistor may be connected to another wiring.

Another embodiment of the present invention is a circuit board including the semiconductor device described above and a printed board.

Another embodiment of the present invention is an electronic device including the semiconductor device described above or the circuit board described above, and a display portion, a microphone, a speaker, or an operation key.

Note that in this specification and the like, a resistor including a layer including an oxide semiconductor is preferably used as the resistor.

According to one embodiment of the present invention, a novel semiconductor device, circuit board, or electronic device can be provided. Alternatively, according to one embodiment of the present invention, a layout area can be reduced or a structure capable of realizing the layout area can be provided. Alternatively, according to one embodiment of the present invention, a current can be prevented from being constantly generated, or a structure capable of realizing the same can be provided. Alternatively, according to one embodiment of the present invention, power consumption can be reduced or a structure that can realize the power consumption can be provided. Alternatively, according to one embodiment of the present invention, a time during which a through current is generated can be shortened or a structure capable of realizing the same can be provided.

Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.

6A and 6B illustrate an example of a semiconductor device. 6A and 6B illustrate an example of a semiconductor device. 6A and 6B illustrate an example of a semiconductor device. 6A and 6B illustrate an example of a semiconductor device. Timing chart. 6A and 6B illustrate an example of a semiconductor device. 6A and 6B illustrate an example of a semiconductor device. 6A and 6B illustrate an example of a semiconductor device. 6A and 6B illustrate an example of a semiconductor device. 6A and 6B illustrate an example of a structure of a transistor. 6A and 6B illustrate an example of a structure of a transistor. 6A and 6B illustrate an example of a structure of a transistor. 6A and 6B illustrate an example of a structure of a transistor. 6A and 6B illustrate an example of a structure of a transistor. 6A and 6B illustrate an example of a structure of a transistor. 6A and 6B illustrate an example of a structure of a transistor. 10A and 10B each illustrate an energy band diagram of a transistor. 6A and 6B illustrate an example of a semiconductor device. The flowchart figure which shows the preparation process of an electronic component, and a perspective schematic diagram. 10A and 10B each illustrate an electronic device.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the description in the following embodiments, and those skilled in the art can easily understand that the forms and details can be variously changed without departing from the spirit and scope of the present invention. Is done. Therefore, the present invention should not be construed as being limited to the description of the following embodiments.

Note that the size, the thickness of films (layers), or regions in drawings is sometimes exaggerated for simplicity.

Note that in this specification, the expression “film” and the expression “layer” can be interchanged with each other.

In many cases, the voltage indicates a potential difference between a certain potential and a reference potential (for example, a ground potential (GND) or a source potential). Thus, a voltage can be rephrased as a potential. Generally, the potential (voltage) is relative and is determined by a relative magnitude from a reference potential. Therefore, even when “ground potential” is described, the potential is not always 0V. For example, the lowest potential in the circuit may be the “ground potential”. Alternatively, an intermediate potential in the circuit may be a “ground potential”. In that case, a positive potential and a negative potential are defined based on the potential.

In this specification and the like, the high power supply potential VDD (hereinafter also simply referred to as “VDD” or “H potential”) is also referred to as the low power supply potential VSS (hereinafter simply referred to as “VSS” or “L potential”). ) Indicates a power supply potential higher than. The low power supply potential VSS is a power supply potential lower than the high power supply potential VDD. Alternatively, the ground potential can be used as VDD or VSS. For example, when VDD is a ground potential, VSS is a potential lower than the ground potential, and when VSS is a ground potential, VDD is a potential higher than the ground potential.

The ordinal numbers attached as the first and second are used for convenience and do not indicate the order of steps or the order of lamination. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”. In addition, the ordinal numbers described in this specification and the like may not match the ordinal numbers used to specify one embodiment of the present invention.

One embodiment of the present invention includes, in its category, any device including a display device, an RF tag, and an imaging device in addition to an integrated circuit. In addition, the display device includes a liquid crystal display device, a light-emitting device including a light-emitting element typified by an organic light-emitting element in each pixel, electronic paper, DMD (Digital Micromirror Device), PDP (Plasma Display Panel), FED (Field Emission). Display) including an integrated circuit such as Display) is included in the category.

Note that in describing the structure of the invention with reference to the drawings, the same reference numerals may be used in common in different drawings.

Further, in this specification and the like, a part of the drawings or texts described in one embodiment can be extracted to constitute one embodiment of the invention. Therefore, when a figure or a sentence describing a certain part is described, the content of the extracted part of the figure or the sentence is also disclosed as one aspect of the invention and may constitute one aspect of the invention. It shall be possible. And it can be said that one aspect of the invention is clear. Therefore, for example, drawings or texts in which one or more active elements (transistors, etc.), wiring, passive elements (capacitance elements, etc.), conductive layers, insulating layers, semiconductor layers, components, devices, operating methods, manufacturing methods, etc. are described. In the above, it is possible to take out a part thereof to constitute one embodiment of the invention. For example, from a circuit diagram having N (N is an integer) circuit elements (transistors, capacitors, etc.), M (M is an integer, M <N) circuit elements (transistors, capacitors) Etc.) can be extracted to constitute one embodiment of the invention. As another example, some elements are arbitrarily extracted from a sentence that states that “A has B, C, D, E, or F”, and “A has B and E”. , “A has E and F”, “A has C, E and F”, or “A has B, C, D and E”. It is possible to configure aspects.

Further, in this specification and the like, when at least one specific example is described in a diagram or text described in one embodiment, it is easy for those skilled in the art to derive a superordinate concept of the specific example. To be understood. Therefore, in the case where at least one specific example is described in a drawing or text described in one embodiment, the superordinate concept of the specific example is also disclosed as one aspect of the invention. Aspects can be configured. One embodiment of the invention is clear.

Further, in this specification and the like, at least the contents described in the drawings (may be part of the drawings) are disclosed as one embodiment of the invention and can constitute one embodiment of the invention. It is. Therefore, if a certain content is described in the figure, even if it is not described using sentences, the content is disclosed as one aspect of the invention and may constitute one aspect of the invention. Is possible. Similarly, a drawing obtained by extracting a part of the drawing is also disclosed as one embodiment of the invention, and can constitute one embodiment of the invention. And it can be said that one aspect of the invention is clear.

In addition, it is possible to constitute one aspect of the invention that stipulates that the contents not specified in the text and drawings in the specification are excluded. Or, when a numerical value range indicated by an upper limit value and a lower limit value is described for a certain value, the range is unified by arbitrarily narrowing the range or by removing one point in the range. One aspect of the invention excluding a part can be defined. Thus, for example, it can be defined that the prior art does not fall within the technical scope of one embodiment of the present invention.

Further, in this specification and the like, those skilled in the art will understand that the present invention can be applied to any terminal of an active element (such as a transistor) and passive element (such as a capacitor) without specifying the connection destination. It may be possible to configure aspects. That is, it can be said that one aspect of the invention is clear without specifying the connection destination. And, when the content specifying the connection destination is described in this specification etc., it is possible to determine that one aspect of the invention that does not specify the connection destination is described in this specification etc. There is. In particular, when there are a plurality of terminal connection destination candidates, it is not necessary to limit the terminal connection destination to a specific location. Therefore, it may be possible to configure one embodiment of the invention by specifying the connection destination of only some terminals of an active element (such as a transistor) and a passive element (such as a capacitor).

Further, in this specification and the like, it may be possible for those skilled in the art to specify the invention when at least the connection destination of a circuit is specified. Alternatively, it may be possible for those skilled in the art to specify the invention when at least the function of a circuit is specified. That is, if the function is specified, it can be said that one aspect of the invention is clear. Then, it may be possible to determine that one embodiment of the invention whose function is specified is described in this specification and the like. Therefore, if a connection destination is specified for a certain circuit without specifying a function, the circuit is disclosed as one embodiment of the invention, and can constitute one embodiment of the invention. Alternatively, if a function is specified for a certain circuit without specifying a connection destination, the circuit is disclosed as one embodiment of the invention, and can constitute one embodiment of the invention.

In addition, in this specification and the like, when it is explicitly described that X and Y are connected, X and Y are electrically connected, and X and Y function. And the case where X and Y are directly connected are disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or text, and anything other than the connection relation shown in the figure or text is also described in the figure or text.

Here, X and Y are assumed to be objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

As an example of the case where X and Y are directly connected, an element that enables electrical connection between X and Y (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, a display, etc.) Element, light emitting element, load, etc.) are not connected between X and Y, and elements (for example, switches, transistors, capacitive elements, inductors) that enable electrical connection between X and Y In this case, X and Y are connected 4 without passing through a resistance element, a diode, a display element, a light emitting element, a load, or the like.

As an example of the case where X and Y are electrically connected, an element (for example, a switch, a transistor, a capacitive element, an inductor, a resistance element, a diode, a display, etc.) that enables electrical connection between X and Y is shown. More than one element, light emitting element, load, etc.) can be connected between X and Y. Note that the switch has a function of controlling on / off. That is, the switch is in a conductive state (on state) or a non-conductive state (off state), and has a function of controlling whether or not to pass a current. Alternatively, the switch has a function of selecting and switching a path through which a current flows. Note that the case where X and Y are electrically connected includes the case where X and Y are directly connected.

As an example of the case where X and Y are functionally connected, a circuit (for example, a logic circuit (an inverter, a NAND circuit, a NOR circuit, etc.) that enables a functional connection between X and Y, signal conversion, etc. Circuit (DA conversion circuit, AD conversion circuit, gamma correction circuit, etc.), potential level conversion circuit (power supply circuit (boost circuit, step-down circuit, etc.), level shifter circuit that changes signal potential level, etc.), voltage source, current source, switching Circuit, amplifier circuit (circuit that can increase signal amplitude or current amount, operational amplifier, differential amplifier circuit, source follower circuit, buffer circuit, etc.), signal generation circuit, memory circuit, control circuit, etc.) One or more can be connected between them. As an example, even if another circuit is interposed between X and Y, if the signal output from X is transmitted to Y, X and Y are functionally connected. To do. Note that the case where X and Y are functionally connected includes the case where X and Y are directly connected and the case where X and Y are electrically connected.

In addition, when it is explicitly described that X and Y are electrically connected, a case where X and Y are electrically connected (that is, there is a separate connection between X and Y). And when X and Y are functionally connected (that is, functionally connected with another circuit between X and Y) And the case where X and Y are directly connected (that is, the case where another element or another circuit is not connected between X and Y). It shall be disclosed in the document. In other words, when it is explicitly described that it is electrically connected, the same contents as when it is explicitly described only that it is connected are disclosed in this specification and the like. It is assumed that

Note that for example, the source (or the first terminal) of the transistor is electrically connected to X through (or not through) Z1, and the drain (or the second terminal or the like) of the transistor is connected to Z2. Through (or without), Y is electrically connected, or the source (or the first terminal, etc.) of the transistor is directly connected to a part of Z1, and another part of Z1 Is directly connected to X, the drain (or second terminal, etc.) of the transistor is directly connected to a part of Z2, and another part of Z2 is directly connected to Y. It can be expressed as follows.

For example, “X and Y, and the source (or the first terminal or the like) of the transistor and the drain (or the second terminal or the like) are electrically connected to each other. Terminal, etc., the drain of the transistor (or the second terminal, etc.) and Y are electrically connected in this order. ” Or “the source (or the first terminal or the like) of the transistor is electrically connected to X, the drain (or the second terminal or the like) of the transistor is electrically connected to Y, and X or the source ( Alternatively, the first terminal and the like, the drain of the transistor (or the second terminal, and the like) and Y are electrically connected in this order. Or “X is electrically connected to Y through the source (or the first terminal or the like) and the drain (or the second terminal or the like) of the transistor, and X is the source of the transistor (or the first terminal or the first terminal). Terminal, etc.), the drain of the transistor (or the second terminal, etc.), and Y are provided in this connection order. By using the same expression method as in these examples and defining the order of connection in the circuit configuration, the source (or the first terminal or the like) and the drain (or the second terminal or the like) of the transistor are separated from each other. Apart from that, the technical scope can be determined.

Alternatively, as another expression method, for example, “the source (or the first terminal or the like) of the transistor is electrically connected to X through at least the first connection path, and the first connection path is The second connection path is between the source (or the first terminal) of the transistor and the drain (or the second terminal) of the transistor via the transistor. The first connection path is a path through Z1, and the drain (or the second terminal, etc.) of the transistor is electrically connected to Y through at least the third connection path, The third connection path does not have the second connection path, and the third connection path is a path through Z2. " Or “the source (or the first terminal or the like) of the transistor is electrically connected to X through Z1 by at least the first connection path, and the first connection path is connected to the second connection path. The second connection path has a connection path through the transistor, and the drain (or the second terminal or the like) of the transistor is connected to Y through Z2 by at least the third connection path. And the third connection path does not have the second connection path. ” Or “the source of the transistor (or the first terminal or the like) is electrically connected to X via Z1 by at least a first electrical path, and the first electrical path is a second electrical path. The second electrical path is an electrical path from the source of the transistor (or the first terminal, etc.) to the drain of the transistor (or the second terminal, etc.), The drain (or the second terminal or the like) is electrically connected to Y through Z2 by at least a third electrical path, and the third electrical path has a fourth electrical path. The fourth electrical path is an electrical path from the drain (or the second terminal or the like) of the transistor to the source (or the first terminal or the like) of the transistor. . By defining the connection path in the circuit configuration using the same expression method as in these examples, the source (or the first terminal, etc.) and the drain (or the second terminal, etc.) of the transistor are distinguished from each other. The technical scope can be determined.

In addition, these expression methods are examples, and are not limited to these expression methods. Here, it is assumed that X, Y, Z1, and Z2 are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, and the like).

In addition, even when the components shown in the circuit diagram are electrically connected to each other, even when one component has the functions of a plurality of components. There is also. For example, in the case where part of the wiring also functions as an electrode, one conductive film has both the functions of both the wiring function and the electrode function. Therefore, the term “electrically connected” in this specification includes in its category such a case where one conductive film has functions of a plurality of components.

(Embodiment 1)
In this embodiment, an example of a semiconductor device according to one embodiment of the present invention will be described. A semiconductor device according to one embodiment of the present invention includes a pull-up circuit for preventing an input / output terminal of a circuit from entering an indefinite state in a circuit including an internal circuit and an input / output terminal that inputs and outputs a signal to the internal circuit. A circuit with an up (or pull-down) resistor.

<Configuration example of semiconductor device>
FIG. 1A is a circuit diagram of a semiconductor device 10 according to one embodiment of the present invention. A semiconductor device 10 illustrated in FIG. 1A includes a transistor 11, a resistor portion 12, an input / output terminal 13, an internal circuit 14, a power supply line 15, a signal line 16, and a control signal generation circuit 17. Have.

In the semiconductor device 10, the first terminal of the transistor 11 is connected to the power supply line 15, and the second terminal of the transistor 11 is connected to the first terminal of the resistor portion 12. The gate of the transistor 11 is connected to the control signal generation circuit 17. The second terminal of the resistor unit 12 is connected to the signal line 16, and the input / output terminal 13 is connected to the internal circuit 14 via the signal line 16.

The input / output terminal 13 is a terminal for inputting a signal (high level signal, low level signal or analog signal) to the internal circuit 14 or outputting a signal (high level signal, low level signal or analog signal) from the internal circuit 14. is there. The control signal generation circuit 17 is a circuit for sending a signal to the gate of the transistor 11 to control the on / off state of the transistor 11.

The power supply line 15 can be a high potential power supply line VDD for applying a high level (H) potential or a low potential power supply line VSS (VSS <VDD) for applying a low level (L) potential. When the power supply line 15 is VDD, the resistance unit 12 in the semiconductor device 10 functions as a pull-up resistor. When the power supply line 15 is VSS, the resistance unit 12 in the semiconductor device 10 functions as a pull-down resistor.

When there is no pull-up (or pull-down) resistor, when a device serving as a circuit or a load is not connected to the input / output terminal 13 from the outside, or when no signal is input / output to the input / output terminal 13, The input / output terminal 13 is in an indefinite state (a state that is neither H nor L, or a state in which H or L is unknown). If the input / output terminal 13 becomes indefinite, the internal circuit 14 may malfunction.

Therefore, by providing a pull-up (or pull-down) resistor as shown in FIG. 1A, the input / output terminal 13 can be fixed at H or L, thereby preventing malfunction of the internal circuit.

The transistor 11 is on when a signal (high level signal, low level signal or analog signal) is not input / output to the input / output terminal 13. Therefore, when the power supply line 15 is VDD, the input / output terminal is held at a high level when no signal is input to the input / output terminal 13. When the power supply line 15 is VSS, the input / output terminal is held at the low level when no signal is input / output to / from the input / output terminal 13.

The transistor 11 is turned off after a signal (a high level signal, a low level signal or an analog signal) is input to the input / output terminal 13 and the internal circuit 14 is normally started. As a result, current can be stopped from flowing between the power supply line 15 and the signal line 16. Therefore, it is possible to prevent a current from being constantly consumed in the resistance unit 12 and reduce the power consumption of the semiconductor device 10.

The transistor 11 and the resistor portion 12 include an oxide semiconductor. An oxide semiconductor is a wide gap semiconductor, and the effective mass of holes is also very large. Further, the carrier concentration of the oxide semiconductor can be reduced by reducing impurities contained in the oxide semiconductor as much as possible and further reducing oxygen vacancies. By using the highly purified intrinsic oxide semiconductor for a transistor, a transistor with extremely low off-state current can be formed. Thus, by using an oxide semiconductor for the transistor 11, power consumption of the semiconductor device 10 can be reduced. Further, when used for the resistance portion 12, the oxide semiconductor as described above has a very high resistance, so that the area for obtaining a required resistance value is reduced by using the oxide semiconductor as the resistance portion. That is, by using an oxide semiconductor for the resistor portion 12, the layout area of the resistor portion 12 can be reduced.

In addition, a transistor and a resistor portion including an oxide semiconductor can easily be stacked. For example, it can be formed by stacking with a transistor using silicon or the like. Therefore, for example, as in the semiconductor device 10 according to one embodiment of the present invention, the transistor 11 and the resistor portion 12 are formed using an oxide semiconductor, and the internal circuit 14 is formed using a transistor using silicon or the like. Since the transistor 11 and the resistor portion 12 and the internal circuit 14 can be stacked, the layout area can be reduced. Alternatively, the transistor 11 and the resistor portion 12 may be stacked.

In addition, a resistance portion including an oxide semiconductor functioning as a resistance layer and a conductive layer in contact with the oxide semiconductor may have a nonlinear resistance.

FIG. 1B is a circuit diagram of the semiconductor device 20 according to one embodiment of the present invention. The semiconductor device 20 has a structure in which the connection of the transistor 11 and the resistor portion 12 in the semiconductor device 10 illustrated in FIG. The semiconductor device 20 includes a transistor 21, a resistance unit 22, an input / output terminal 23, an internal circuit 24, a power supply line 25, a signal line 26, and a control signal generation circuit 27.

In the semiconductor device 20, the first terminal of the transistor 21 is connected to the second terminal of the resistor 22, and the second terminal of the transistor 21 is connected to the signal line 26. The gate of the transistor 21 is connected to the control signal generation circuit 27. The first terminal of the resistor 22 is connected to the power supply line 25, and the input / output terminal 23 is connected to the internal circuit 24 via the signal line 26.

FIG. 1C is a circuit diagram of a semiconductor device 30 according to one embodiment of the present invention. The semiconductor device 30 includes a transistor 31, an input / output terminal 33, an internal circuit 34, a power supply line 35, a signal line 36, and a control signal generation circuit 37.

The semiconductor device 30 has a structure in which the resistor portion 12 is not provided in the semiconductor device 10 of FIG. That is, the semiconductor device 30 in FIG. 1C includes only the transistor 31 between the power supply line 35 and the signal line 36.

In the semiconductor device 30, the first terminal of the transistor 31 is connected to the power supply line 35, and the second terminal of the transistor 31 is connected to the signal line 36. The gate of the transistor 31 is connected to the control signal generation circuit 37. The input / output terminal 33 is connected to the internal circuit 34 via the signal line 36.

The semiconductor device 30 has a configuration in which there is no resistance portion between the power supply line 35 and the signal line 36, but the on-state channel resistance of the transistor 31 can be used instead of the resistance portion, and a pull-up ( Also functions as a pull-down resistor. In particular, an oxide semiconductor is preferably used for the transistor 31 because high channel resistance is easily formed and off-state current is extremely small.

FIG. 1D is a circuit diagram of a semiconductor device 40 according to one embodiment of the present invention. The semiconductor device 40 includes a resistance unit 42, an input / output terminal 43, an internal circuit 44, a power supply line 45, and a signal line 46.

The semiconductor device 40 has a structure in which the transistor 11 and the control signal generation circuit 17 are not provided in the semiconductor device 10 of FIG. That is, the semiconductor device 40 in FIG. 1D has a configuration in which only the resistance portion 42 is provided between the power supply line 45 and the signal line 46.

In the semiconductor device 40, the first terminal of the resistor portion 42 is connected to the power supply line 45, and the second terminal of the resistor portion 42 is connected to the signal line 46. The input / output terminal 43 is connected to the internal circuit 44 via the signal line 46.

The semiconductor device 40 has a configuration in which no transistor is provided between the power supply line 45 and the signal line 46. As described above, even if a transistor is not formed between the power supply line 45 and the signal line 46, since the resistor portion 42 is provided, it is possible to suppress the signal line 46 from being indefinite. However, in that case, while the semiconductor device 40 is activated, current constantly flows, so that the power consumption of the semiconductor device 40 increases, but the area for forming the transistor is not necessary. The layout can be reduced.

In the semiconductor device 10 illustrated in FIG. 1A, a plurality of transistors 11 and resistor portions 12 can be used. For example, as in the semiconductor device 70 illustrated in FIG. 2A, a configuration using two resistance portions 12 may be employed. In addition, it is good also as a structure using three or more resistance parts 12. FIG. Alternatively, a structure in which two transistors 11 are used as in the semiconductor device 80 illustrated in FIG. Note that three or more transistors 11 may be used. In addition, the transistors 11 and the resistor portions 12 do not need to be connected alternately, and may be configured such that the same transistors are continuously connected.

As an example of the internal circuit 14 in the semiconductor device 10 shown in FIG. 1A, a gate driver circuit is used as shown in FIG. 3A and a clock generator is used as shown in FIG. it can. In addition to the above, various circuits can be used.

FIG. 4A is a circuit diagram of the semiconductor device 50 according to one embodiment of the present invention. The semiconductor device 50 has a structure in which a transistor is further provided between the gate of the transistor 11 and the control signal generation circuit 17 in the structure of the semiconductor device 10 in FIG.

The semiconductor device 50 includes a transistor 51, a resistance unit 52, an input / output terminal 53, an internal circuit 54, a power supply line 55, a signal line 56, a control signal generation circuit 57, and a transistor 58.

In the semiconductor device 50, the first terminal of the transistor 51 is connected to the power supply line 55, the second terminal of the transistor 51 is connected to the first terminal of the resistor unit 52, and the second terminal of the resistor unit 52 is a signal. Connected to line 56. The gate of the transistor 51 is connected to the first terminal of the transistor 58, and the second terminal of the transistor 58 is connected to the control signal generation circuit 57. The gate of the transistor 58 is connected to the control signal generation circuit 57. The input / output terminal 53 is connected to the internal circuit 54 via the signal line 56. In addition, a floating node (FN) is formed at a connection point between the gate of the transistor 51 and the first terminal of the transistor 58.

The transistor 58 includes an oxide semiconductor like the transistor 51 and the resistor portion 52. A transistor including an oxide semiconductor has very low off-state current. Therefore, in the semiconductor device 50, the voltage for operating the transistor 51 can be held at FN by switching the transistor 58 on and off. Therefore, the control signal generation circuit 57 can be stopped during a period in which the transistor 51 is kept on or off. With this configuration, the power consumption of the semiconductor device 50 can be reduced.

In the semiconductor device 50 illustrated in FIG. 4A, the gate of the transistor 58 is connected to the control signal generation circuit 57; however, the gate of the transistor 58 may not be connected to the control signal generation circuit 57. Good. That is, the gate of the transistor 58 can be connected to another wiring or circuit.

FIG. 4B is a circuit diagram of the semiconductor device 60 according to one embodiment of the present invention. The semiconductor device 60 has a structure in which a capacitor is further connected to a floating node formed at a connection point between the gate of the transistor 51 and the transistor 58 in the structure of the semiconductor device 50 in FIG.

The semiconductor device 60 includes a transistor 61, a resistor 62, an input / output terminal 63, an internal circuit 64, a power supply line 65, a signal line 66, a control signal generation circuit 67, a transistor 68, and a capacitor element 69. Have.

In the semiconductor device 60, the first terminal of the transistor 61 is connected to the power supply line 65, the second terminal of the transistor 61 is connected to the first terminal of the resistor 62, and the second terminal of the resistor 62 is a signal Connected to line 66. The gate of the transistor 61 is connected to the first terminal of the transistor 68 and the capacitor 69, and the second terminal of the transistor 68 is connected to the control signal generation circuit 67. The gate of the transistor 68 is connected to the control signal generation circuit 67. The input / output terminal 63 is connected to the internal circuit 64 via the signal line 66. In addition, a floating node (FN) is formed at a connection point between the gate of the transistor 61, the first terminal of the transistor 68, and the capacitor 69.

Similar to the semiconductor device 50, the semiconductor device 60 can hold the voltage for operating the transistor 61 at FN by switching the transistor 68 on and off. Further, the semiconductor device 60 has a configuration in which the voltage is more easily held in the FN because the capacitor 69 is connected to the FN. Therefore, it becomes easier to hold the transistor 61 in an on state or an off state, and the control signal generation circuit 67 can be stopped, so that power consumption of the semiconductor device 60 can be reduced.

In the semiconductor device 60 illustrated in FIG. 4B, the gate of the transistor 68 is connected to the control signal generation circuit 67. However, the gate of the transistor 68 may not be connected to the control signal generation circuit 67. Good. That is, the gate of the transistor 68 can be connected to another wiring or circuit.

<Operation example of semiconductor device>
Next, an operation in the case where the semiconductor device 10 illustrated in FIG. 1A is controlled based on the timing charts illustrated in FIGS. 5A and 5B will be described. However, the semiconductor device 10 illustrated in FIG. 1A can perform a variety of other operations by appropriately controlling the potential of each wiring.

FIG. 5A is a timing chart illustrating the case where the power supply line 15 of the semiconductor device 10 in FIG. 1A functions as the high potential power supply line VDD. That is, the resistance unit 12 functions as a pull-up resistor.

FIG. 5A shows a potential V15 of the power supply line 15, a potential V17 of the control signal generation circuit 17, and a potential V13 of the input / output terminal 13.

In a period T <b> 11 illustrated in FIG. 5A, the potentials of the power supply line 15 and the control signal generation circuit 17 are gradually increased and boosted to the threshold voltage (Vth) of the transistor 11. The potential of the input / output terminal 13 is indefinite because the transistor 11 is in an off state and is in a floating state.

In the period T12, the potentials of the power supply line 15 and the control signal generation circuit 17 are further increased and boosted to VDD (H). Thereafter, the potentials of the power supply line 15 and the control signal generation circuit 17 are held at VDD (H). The potential of the input / output terminal 13 is the same potential (VDD) as that of the power supply line 15 because the transistor 11 is turned on.

In the period T13, the potentials of the power supply line 15 and the control signal generation circuit 17 are held at VDD (H). A low level (L) signal (VSS) is input to the input / output terminal 13. That is, since current flows through the transistor 11 and the resistance portion 12 in the period T13, the power consumption of the semiconductor device 10 increases. Therefore, it is preferable that the period T13 is shorter.

In the period T14, the potential of the power supply line 15 is held at VDD. A low level (L) signal (VSS) is input to the control signal generation circuit 17, and the transistor 11 is turned off. The potential of the input / output terminal 13 is held at VSS (L).

In the period T15, the potential of the power supply line 15 is held at VDD (H). A high level signal (VDD) is input to the control signal generation circuit 17, and the transistor 11 is turned on. The potential of the input / output terminal 13 is held at VSS (L). That is, since current flows through the transistor 11 and the resistance portion 12 in the period T15, the power consumption of the semiconductor device 10 increases. Therefore, it is preferable that the period T15 is short.

In the period T16, the potentials of the power supply line 15 and the control signal generation circuit 17 are held at VDD. The potential of the input / output terminal 13 is VDD (H) because the input of the low level (L) signal is stopped.

FIG. 5B is a timing chart illustrating a case where the power supply line 15 of the semiconductor device 10 in FIG. 1A functions as the low potential power supply line VSS. That is, the resistance unit 12 functions as a pull-down resistor.

FIG. 5B shows a potential V15 of the power supply line 15, a potential V17 of the control signal generation circuit 17, and a potential V13 of the input / output terminal 13.

In the period T21 illustrated in FIG. 5B, the power supply line 15 is held at VSS (L). The potential of the control signal generation circuit 17 gradually increases and is boosted to the threshold voltage (Vth) of the transistor 11. Further, the potential of the input / output terminal 13 is in a floating state because the transistor 11 is in an off state and is in an indefinite state.

In the period T22, the power supply line 15 is held at VSS (L). The potential of the control signal generation circuit 17 further increases and is boosted to VDD (H). Thereafter, the potential of the control signal generation circuit 17 is held at VDD (H). The potential of the input / output terminal 13 is the same potential (VSS) as that of the power supply line 15 because the transistor 11 is turned on.

In the period T23, the power supply line 15 is held at VSS (L). The potential of the control signal generation circuit 17 is held at VDD. A high level signal (VDD) is input to the input / output terminal 13. That is, since current flows through the transistor 11 and the resistance portion 12 in the period T23, the power consumption of the semiconductor device 10 increases. Therefore, it is preferable that the period T23 is short.

In the period T24, the power supply line 15 is held at VSS (L). A low level (L) signal (VSS) is input to the control signal generation circuit 17, and the transistor 11 is turned off. The potential of the input / output terminal 13 is held at VDD (H).

In the period T25, the power supply line 15 is held at VSS (L). A high level signal (VDD) is input to the control signal generation circuit 17, and the transistor 11 is turned on. The potential of the input / output terminal 13 is held at VDD (H). That is, in the period T25, current flows through the transistor 11 and the resistance unit 12, and thus power consumption of the semiconductor device 10 increases. Therefore, it is preferable that the period T25 is shorter.

In the period T26, the potential of the power supply line 15 is held at VSS (L). The potential of the control signal generation circuit 17 is held at VDD. Since the input of the high level (H) signal is stopped, the potential of the input / output terminal 13 becomes VSS (L).

As described above, the semiconductor device 10 illustrated in FIG. 1 can function as a semiconductor device having a pull-up (or pull-down) resistance such as an IC.

Note that one embodiment of the present invention is described in this embodiment. Alternatively, in another embodiment, one embodiment of the present invention will be described. Note that one embodiment of the present invention is not limited thereto. That is, in this embodiment and other embodiments, various aspects of the invention are described; therefore, one embodiment of the present invention is not limited to a particular aspect. For example, as an embodiment of the present invention, an example in which a pull-up (or pull-down) resistor is applied has been described. However, one embodiment of the present invention is not limited thereto. Depending on circumstances or circumstances, one embodiment of the present invention may be applied to another circuit. Or, for example, in some cases or depending on circumstances, one embodiment of the present invention may not apply a pull-up (or pull-down) resistor. For example, although an example in which an oxide semiconductor is included in a transistor is described as one embodiment of the present invention, one embodiment of the present invention is not limited thereto. Depending on circumstances or circumstances, in one embodiment of the present invention, the transistor includes silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor. As such, various semiconductor materials may be included. Alternatively, for example, depending on circumstances or circumstances, in one embodiment of the present invention, the transistor may not include an oxide semiconductor.

Note that this embodiment can be combined with any of the other embodiments as appropriate. Therefore, the contents described in this embodiment (may be a part of contents) may be different from the contents described in the embodiment (may be a part of contents) and / or one or more other contents. Application, combination, replacement, or the like can be performed on the contents described in the embodiment (may be part of the contents). Note that the contents described in the embodiments are contents described using various drawings or contents described in the specification in each embodiment. In addition, a diagram (or a part) described in one embodiment may include another part of the diagram, another diagram (or part) described in the embodiment, and / or one or more. More diagrams can be formed by combining the diagrams (may be a part) described in another embodiment. The same applies to the following embodiments.

(Embodiment 2)
In this embodiment, a configuration example of the transistor 11 and the resistor portion 12 in the semiconductor device 10 described in Embodiment 1 will be described.

<Configuration example 1>
FIG. 6 shows a circuit diagram, a top view, and a cross-sectional view of the transistor 100 and the resistor portion 200. Note that the transistor 100 can be used as the transistor 11 in FIG. Further, the resistance portion 200 can be used for the resistance portion 12 in FIG. In addition, a structure in which the transistor 100 and the resistor portion 200 in this embodiment include an oxide semiconductor will be described.

FIG. 6A shows a circuit diagram in which the transistor 100 and the resistor portion 200 are connected. 6B is a top view illustrating an example of a structure of the transistor 100 and the resistor portion 200 illustrated in FIG. 6C is a cross-sectional view taken along the dashed-dotted line A1-A2 in FIG. 6A, FIG. 6D is a cross-sectional view taken along the dashed-dotted line A3-A4, and FIG. 6E is a dashed-dotted line A5. Sectional drawing in -A6 is shown. Here, the direction of the alternate long and short dash line A1-A2 may be referred to as a channel length direction, and the direction of the alternate long and short dash line A3-A4 may be referred to as a channel width direction. 6C is a diagram illustrating a cross-sectional structure of the transistor 100 in the channel length direction, and FIG. 6D is a diagram illustrating a cross-sectional structure of the transistor 100 in the channel width direction. Note that some components are omitted in FIG. 6B in order to clarify the device structure.

A transistor 100 illustrated in FIG. 6 includes an insulating layer 112 over a substrate 110, an oxide semiconductor layer 120 over the insulating layer 112, and a conductive layer 141 and a conductive layer 142 formed in part with the oxide semiconductor layer 120. And the oxide semiconductor layer 120, the conductive layer 141, and the insulating layer 113 over the conductive layer 142, and the oxide semiconductor layer 120 overlapping with the conductive layer 130 over the insulating layer 113, and over the conductive layer 130 and the insulating layer 113. And an insulating layer 115.

6 includes the insulating layer 112 over the substrate 110, the oxide semiconductor layer 121 over the insulating layer 112, and the conductive layer 142 and the conductive layer formed in part with the oxide semiconductor layer 121. The insulating layer 113 over the layer 143, the oxide semiconductor layer 121, the conductive layer 142, and the conductive layer 143, and the insulating layer 115 over the insulating layer 113 are included.

In the transistor 100, the insulating layer 112 can function as a base insulating layer. The oxide semiconductor layer 120 can function as an active layer of the transistor 100. The conductive layer 141 and the conductive layer 142 can function as a source electrode and a drain electrode. The insulating layer 113 has a region functioning as a gate insulating layer. The conductive layer 130 can function as a gate electrode. The insulating layer 115 can function as an interlayer insulating layer.

In the resistance portion 200, the oxide semiconductor layer 121 can function as a resistance layer.

<Configuration example 2>
FIG. 7 shows a circuit diagram, a top view, and a cross-sectional view of the transistor and the resistor portion 101. Note that the transistor and the resistor portion 101 can be used for the transistor 11 and the resistor portion 12 in FIG. In addition, a structure in which the transistor and the resistor portion 101 in this embodiment include an oxide semiconductor will be described.

The transistor and resistance unit 101 illustrated in FIG. 7 has a configuration in which the transistor 100 and the resistance unit 200 in FIG. 6 are combined into one. In particular, by using a transistor including an oxide semiconductor and the resistor portion 101, an active layer of a transistor having a low off-state current and a resistor layer having a high resistance value can be directly connected. Thus, the layout area can be reduced by combining the transistor and the resistance portion.

FIG. 7A shows a circuit diagram of the transistor and resistor 101. FIG. 7B is a top view illustrating an example of the structure of the transistor and the resistor portion 101 illustrated in FIG. 7C is a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. 7A, FIG. 7D is a cross-sectional view taken along dashed-dotted line A3-A4, and FIG. 7E is a dashed-dotted line A5. Sectional drawing in -A6 is shown. Note that some components are omitted in FIG. 7B in order to clarify the device structure.

7 includes the insulating layer 112 over the substrate 110, the oxide semiconductor layer 122 over the insulating layer 112, and the conductive layer 141 formed in part with the oxide semiconductor layer 122. And the conductive layer 143, the oxide semiconductor layer 122, the conductive layer 141, the insulating layer 114 over the conductive layer 143, and the oxide semiconductor layer 122, and the conductive layer 131 over the insulating layer 114 and the conductive layer 131. And an insulating layer 115 over the insulating layer 114.

In the transistor and the resistor portion 101, the insulating layer 112 can function as a base insulating layer. In the oxide semiconductor layer 122, a region overlapping with the conductive layer 131 in the transistor and the resistor portion 101 can function as an active layer of the transistor. The conductive layer 141 and the conductive layer 143 can function as a source electrode and a drain electrode. The insulating layer 114 has a region functioning as a gate insulating layer. The conductive layer 131 can function as a gate electrode. The insulating layer 115 can function as an interlayer insulating layer.

In the transistor and the resistor portion 101, the oxide semiconductor layer 122 can function as a resistor layer in the resistor portion in a region between the conductive layer 131 and the conductive layer 143.

<Configuration example 3>
FIG. 8 shows a circuit diagram, a top view, and a cross-sectional view of the transistor 400 and the resistor portion 401. Note that the transistor 400 and the resistor portion 401 can be used for the transistor 11 and the resistor portion 12 in FIG. In addition, a structure in which the transistor 400 and the resistor portion 401 in this embodiment include an oxide semiconductor will be described.

A transistor 400 illustrated in FIG. 8 is not a top-gate transistor as illustrated in FIGS. 6 and 7, but a bottom-gate transistor.

FIG. 8A shows a circuit diagram of the transistor 400 and the resistor portion 401. FIG. 8B is a top view illustrating an example of a structure of the transistor 400 and the resistor portion 401 illustrated in FIG. FIG. 8C illustrates a cross-sectional view taken along dashed-dotted line A1-A2 in FIG. Note that some components are omitted in FIG. 8B in order to clarify the device structure.

8 includes an insulating layer 112 over a substrate 110, a conductive layer 410 over the insulating layer 112, an insulating layer 412 over the conductive layer 410, an oxide semiconductor layer 414 over the insulating layer 412, and an oxide layer. The conductive layer 418 and the conductive layer 420 which are partly in contact with the physical semiconductor layer 414 and the oxide semiconductor layer 414, the conductive layer 418, and the insulating layer 424 over the conductive layer 420 are included.

8 is partially in contact with the insulating layer 112 over the substrate 110, the insulating layer 412 over the insulating layer 112, the oxide semiconductor layer 416 over the insulating layer 412, and the oxide semiconductor layer 416. The conductive layer 420 and the conductive layer 422 are formed, and the oxide semiconductor layer 416 and the insulating layer 424 over the conductive layer 420 and the conductive layer 422 are formed.

In the transistor 400, the insulating layer 112 can function as a base insulating layer. The oxide semiconductor layer 414 can function as an active layer of the transistor 400. The conductive layer 418 and the conductive layer 420 can function as a source electrode and a drain electrode. The insulating layer 412 has a region functioning as a gate insulating layer. The conductive layer 410 can function as a gate electrode. The insulating layer 424 can function as an interlayer insulating layer.

In the resistance portion 401, the oxide semiconductor layer 416 can function as a resistance layer.

The bottom-gate transistor 400 illustrated in FIG. 8 has a channel-etched structure, but may be a channel-protective transistor 402 as illustrated in FIG. 9A.

A transistor 402 illustrated in FIG. 9A includes an insulating layer 112 over a substrate 110, a conductive layer 410 over the insulating layer 112, an insulating layer 412 over the conductive layer 410, and an oxide semiconductor layer 414 over the insulating layer 412. And the insulating layer 428 over the oxide semiconductor layer 414, the conductive layer 430 and the conductive layer 432, and the oxide semiconductor layer 414 and the insulating layer 428 which are partly in contact with the oxide semiconductor layer 414 and the insulating layer 428. A conductive layer 430 and an insulating layer 434 over the conductive layer 432.

In the transistor 402, the insulating layer 112 can function as a base insulating layer. The oxide semiconductor layer 414 can function as an active layer of the transistor 400. The conductive layer 430 and the conductive layer 432 can function as a source electrode and a drain electrode. The insulating layer 412 has a region functioning as a gate insulating layer. The conductive layer 410 can function as a gate electrode. The insulating layer 434 can function as an interlayer insulating layer. The insulating layer 428 can function as a channel protective layer.

A transistor 403 illustrated in FIG. 9B has a structure in which the conductive layer 411 is included in the transistor 400 in FIG. In the transistor 403, the conductive layer 411 can function as a back gate electrode.

Further, the resistor portion 401 illustrated in FIG. 8 may further include a conductive layer. A resistor 404 having a conductive layer 435 in addition to the resistor 401 is illustrated in FIG.

9C includes an insulating layer 112 over the substrate 110, a conductive layer 435 over the insulating layer 112, an insulating layer 438 over the conductive layer 435, and an oxide semiconductor over the insulating layer 438. The conductive layer 440 and the conductive layer 442 which are partly in contact with the oxide semiconductor layer 444 and the insulating layer 446 over the oxide semiconductor layer 444, the conductive layer 440, and the conductive layer 442 are provided.

In the resistor portion 404, the oxide semiconductor layer 444 can function as a resistor layer.

Further, the resistor portion 405 illustrated in FIG. 9D has a structure in which the conductive layer 448 is provided in the resistor portion 404 in FIG. 9C.

A resistor 406 illustrated in FIG. 9E has a structure in which the resistor 401 in FIG. 8 includes the insulating layer 450.

In the case where a film containing much hydrogen, for example, a film containing silicon nitride, or the like is used for the insulating layer 450, the resistance value of the oxide semiconductor layer 416 may be reduced.

The structures and methods described in this embodiment can be combined as appropriate with any of the structures and methods described in the other embodiments.

(Embodiment 3)
In this embodiment, a structural example of a transistor including an oxide semiconductor (also referred to as an OS transistor) that can be used in one embodiment of the present invention will be described. The OS transistor described in this embodiment can be applied to, for example, the transistor 11 in FIG. 1A and the transistor 58 in FIG.

<Configuration example 1>
FIG. 10 shows an example of the structure of the OS transistor. FIG. 10A is a top view illustrating an example of a structure of an OS transistor. 10B is a cross-sectional view taken along the line y1-y2, FIG. 10C is a cross-sectional view taken along the line x1-x2, and FIG. 10D is a cross-sectional view taken along the line x3-x4. Here, the y1-y2 line direction may be referred to as a channel length direction, and the x1-x2 line direction may be referred to as a channel width direction. 10B is a diagram illustrating a cross-sectional structure of the OS transistor in the channel length direction, and FIGS. 10C and 10D are diagrams illustrating a cross-sectional structure of the OS transistor in the channel width direction. Become. Note that some components are omitted in FIG. 10A in order to clarify the device structure.

An OS transistor 501 illustrated in FIG. 10 includes a back gate. The OS transistor 501 is formed on an insulating surface. Here, the insulating layer 511 is formed. The insulating layer 511 is formed on the surface of the substrate 510. The OS transistor 501 is covered with an insulating layer 514 and an insulating layer 515. Note that the insulating layers 514 and 515 can also be regarded as components of the OS transistor 501. The OS transistor 501 includes an insulating layer 512, an insulating layer 513, an oxide semiconductor layer 521, an oxide semiconductor layer 522, an oxide semiconductor layer 523, a conductive layer 530, a conductive layer 531, a conductive layer 541, and a conductive layer 542. Here, the oxide semiconductor layer 521, the oxide semiconductor layer 522, and the oxide semiconductor layer 523 are collectively referred to as an oxide semiconductor layer 520. Although a structure having a back gate is shown here, a structure without a back gate may be used.

The insulating layer 513 includes a region functioning as a gate insulating layer. The conductive layer 530 functions as a gate electrode (first gate electrode). The conductive layer 531 functions as a back gate electrode (second gate electrode). The conductive layer 541 and the conductive layer 542 function as a source electrode or a drain electrode, respectively. Note that the conductive layer 531 is not necessarily provided (the same applies hereinafter).

As illustrated in FIGS. 10B and 10C, the oxide semiconductor layer 520 includes a region in which an oxide semiconductor layer 521, an oxide semiconductor layer 522, and an oxide semiconductor layer 523 are stacked in this order. The insulating layer 513 covers this stacked portion. The conductive layer 531 overlaps with a stacked portion of the oxide semiconductor layer with the insulating layer 513 provided therebetween. The conductive layer 541 and the conductive layer 542 are provided over a stacked film including the oxide semiconductor layer 521 and the oxide semiconductor layer 523, which are in contact with the top surface of the stacked film and the side surface in the channel length direction of the stacked film. ing. In the example of FIG. 10, the conductive layers 541 and 542 are also in contact with the insulating layer 512. The oxide semiconductor layer 523 is formed so as to cover the oxide semiconductor layer 521, the oxide semiconductor layer 522, the conductive layer 541, and the conductive layer 542. The lower surface of the oxide semiconductor layer 523 is in contact with the upper surface of the oxide semiconductor layer 522.

In the oxide semiconductor layer 520, a conductive layer 530 is formed so as to surround the channel width direction of the stacked portion of the oxide semiconductor layers 521 to 523 with the insulating layer 513 provided therebetween (see FIG. 10C). For this reason, in addition to the gate electric field from the vertical direction, a gate electric field from the side surface direction is also applied to the stacked portion. In the OS transistor 501, a gate electric field refers to an electric field formed by a voltage applied to the conductive layer 531 (gate electrode layer). Therefore, since the entire stacked portion of the oxide semiconductor layers 521 to 523 can be electrically surrounded by the gate electric field, a channel may be formed in the entire oxide semiconductor layer 522 (bulk). Therefore, the OS transistor 501 can have high on-state current characteristics.

In this specification, a structure of a transistor in which a semiconductor can be electrically surrounded by a gate electric field is referred to as a “surrounded channel (s-channel)” structure. The OS transistor 501 has an s-channel structure. In the s-channel structure, a large current can flow between the source and the drain of the transistor, and the drain current (on-state current) in the conductive state can be increased.

When the OS transistor 501 has an s-channel structure, the channel formation region can be easily controlled by a gate electric field with respect to the side surface of the oxide semiconductor layer 522. A structure in which the conductive layer 530 extends to the lower side of the oxide semiconductor layer 522 and faces the side surface of the oxide semiconductor layer 521 is preferable because the controllability is further improved. As a result, the subthreshold swing value (also referred to as S value) of the OS transistor 501 can be reduced, and the short channel effect can be suppressed. Therefore, the structure is suitable for miniaturization.

As the OS transistor 501 illustrated in FIG. 10 has a three-dimensional device structure, the channel length can be less than 100 nm. By reducing the size of the OS transistor, the circuit area can be reduced. The channel length of the OS transistor is preferably less than 65 nm, more preferably 30 nm or less or 20 nm or less.

A conductor functioning as the gate of the transistor is a gate electrode, a conductor functioning as the source of the transistor is a source electrode, a conductor functioning as the drain of the transistor is a drain electrode, a region functioning as the source of the transistor is a source region, and a drain of the transistor A region that functions as a drain region is called a drain region. In this specification, the gate electrode may be referred to as a gate, the drain electrode or the drain region may be referred to as a drain, and the source electrode or the source region may be referred to as a source.

The channel length is, for example, a source in a region where a semiconductor (or a portion where a current flows in the semiconductor when the transistor is on) and a gate overlap with each other or a channel is formed in a top view of a transistor The distance between the drain. Note that in one transistor, the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

The channel width is, for example, that a source and a drain face each other in a region where a semiconductor (or a portion where a current flows in the semiconductor when the transistor is on) and a gate overlap, or in a region where a channel is formed. The length of the part. Note that in one transistor, the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

Note that depending on the structure of the transistor, the channel width in a region where a channel is actually formed (hereinafter referred to as an effective channel width) and the channel width shown in a top view of the transistor (hereinafter, apparent channel width). May be different). For example, in a transistor having a three-dimensional structure, the effective channel width is larger than the apparent channel width shown in the top view of the transistor, and the influence may not be negligible. For example, in a transistor having a fine and three-dimensional structure, the ratio of the channel region formed on the side surface of the semiconductor may be large. In that case, the effective channel width in which the channel is actually formed is larger than the apparent channel width shown in the top view.

In this specification, in the case where the term “channel width” is simply used, it may denote an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may denote an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, and the like can be determined by obtaining a cross-sectional TEM image and analyzing the image. it can.

<Configuration example 2>
An OS transistor 502 illustrated in FIG. 11 is a modification example of the OS transistor 501. FIG. 11A is a top view of the OS transistor 502. FIG. 11B is a cross-sectional view taken along a line y1-y2, FIG. 11C is a cross-sectional view taken along a line x1-x2, and FIG. 11D is a cross-sectional view taken along a line x3-x4. Note that some components are not illustrated in FIG. 11A in order to clarify the device structure.

Similarly to the OS transistor 501, the OS transistor 502 illustrated in FIG. 11 has an s-channel structure. The shapes of the conductive layers 541 and 542 are different from those of the OS transistor 501. The conductive layer 541 and the conductive layer 542 of the OS transistor 502 are formed using a hard mask used for forming a stacked film of the oxide semiconductor layer 521 and the oxide semiconductor layer 522. Therefore, the conductive layer 541 and the conductive layer 542 are not in contact with the side surfaces of the oxide semiconductor layer 521 and the oxide semiconductor layer 522 (FIG. 11D).

Through the following steps, the oxide semiconductor layers 521 and 522 and the conductive layers 541 and 542 can be manufactured. Two oxide semiconductor films which form the oxide semiconductor layers 521 and 522 are formed. A single-layer or stacked-layer conductive film is formed over the oxide semiconductor film. This conductive film is etched to form a hard mask. Using this hard mask, the two-layer oxide semiconductor film is etched, so that a stacked film of the oxide semiconductor layer 521 and the oxide semiconductor layer 522 is formed. Next, the hard mask is etched to form a conductive layer 541 and a conductive layer 542.

<Configuration examples 3 and 4>
An OS transistor 503 illustrated in FIG. 12 is a modification example of the OS transistor 501, and an OS transistor 504 illustrated in FIG. 13 is a modification example of the OS transistor 502. In the OS transistor 503 and the OS transistor 504, the oxide semiconductor layer 523 and the insulating layer 513 are etched using the conductive layer 530 as a mask. Therefore, end portions of the oxide semiconductor layer 532 and the insulating layer 513 substantially coincide with end portions of the conductive layer 530.

<Configuration Examples 5 and 6>
An OS transistor 505 illustrated in FIG. 14 is a modification example of the OS transistor 501, and an OS transistor 506 illustrated in FIG. 15 is a modification example of the OS transistor 502. The OS transistor 505 and the OS transistor 506 each include a layer 551 between the oxide semiconductor layer 523 and the conductive layer 541, and a layer 552 between the oxide semiconductor layer 523 and the conductive layer 542.

The layers 551 and 552 can be formed of a layer formed using a transparent conductor, an oxide semiconductor, a nitride semiconductor, or an oxynitride semiconductor, for example. The layers 551 and 552 can be formed using an n-type oxide semiconductor layer or can be formed using a conductor layer having higher resistance than the conductive layers 541 and 542. For example, as the layer 551 and the layer 552, a layer containing indium, tin and oxygen, a layer containing indium and zinc, a layer containing indium, tungsten and zinc, a layer containing tin and zinc, a layer containing zinc and gallium, zinc and A layer containing aluminum, a layer containing zinc and fluorine, a layer containing zinc and boron, a layer containing tin and antimony, a layer containing tin and fluorine, or a layer containing titanium and niobium may be used. The illustrated layers may include one or more of hydrogen, carbon, nitrogen, silicon, germanium, or argon.

The layers 551 and 552 may have a property of transmitting visible light. Alternatively, the layers 551 and 552 may have a property of not transmitting visible light, ultraviolet light, infrared light, or X-rays by reflection or absorption. By having such a property, a change in electrical characteristics of the transistor due to stray light may be suppressed in some cases.

For the layers 551 and 552, a layer that does not form a Schottky barrier with the oxide semiconductor layer 532 is preferably used. Thus, the on characteristics of the OS transistors 505 and 506 can be improved.

The layers 551 and 552 are preferably higher resistance layers than the conductors 516a and 516b. The layers 551 and 552 preferably have lower resistance than the channel resistance of the transistor. For example, the resistivity of the layers 551 and 552 may be 0.1 Ωcm to 100 Ωcm, 0.5 Ωcm to 50 Ωcm, or 1 Ωcm to 10 Ωcm. By setting the resistivity of the layers 551 and 552 within the above range, electric field concentration at the boundary between the channel and the drain can be reduced. Therefore, variation in electrical characteristics of the transistor can be reduced. In addition, the punch-through current due to the electric field generated from the drain can be reduced. Therefore, saturation characteristics can be improved even in a transistor with a short channel length. Note that in a circuit configuration in which the source and the drain are not interchanged, it may be preferable to dispose only one of the layers 551 and 552 (for example, the drain side).

<Configuration example 7>
10 to 15, the conductive layer 530 functioning as the first gate electrode and the conductive layer 531 functioning as the second gate electrode may be connected. As an example, FIG. 16 illustrates a structure in which the conductive layer 530 and the conductive layer 531 in FIG. 10 are connected.

As shown in FIG. 16C, an opening is provided in the insulating layer 512 and the insulating layer 513, and a conductive layer 560 is provided in the opening. The conductive layer 530 is connected to the conductive layer 531 through the conductive layer 560. Accordingly, the first gate electrode and the second gate electrode of the OS transistor 501 can be connected. 11 to 15 similarly, a structure in which the first gate electrode and the second gate electrode are connected can be applied.

Hereinafter, components of the OS transistors 501 to 506 will be described.

<Oxide semiconductor layer>
As a semiconductor material of the oxide semiconductor layers 521 to 523, typically, an In—Ga oxide, an In—Zn oxide, an In—M—Zn oxide (where M is Ga, Sn, Y, Zr, La) , Ce, or Nd). The oxide semiconductor layers 521 to 523 are not limited to oxide layers containing indium. The oxide semiconductor layers 521 to 523 can be formed using, for example, a Zn—Sn oxide layer, a Ga—Sn layer, a Zn—Mg oxide, or the like. The oxide semiconductor layer 522 is preferably formed using an In-M-Zn oxide. The oxide semiconductor layer 521 and the oxide semiconductor layer 523 can each be formed using a Ga oxide.

The case where the oxide semiconductor layers 521 to 523 are formed using an In-M-Zn oxide film formed by a sputtering method is described. An atomic ratio of metal elements of a target for film formation of an In-M-Zn oxide used for forming the oxide semiconductor layer 522 is In: M: Zn = x ₁ : y ₁ : z ₁ , and the oxide semiconductor The atomic ratio of the metal element of the target used for forming the layer 521 and the oxide semiconductor layer 523 is In: M: Zn = x ₂ : y ₂ : z ₂ .

In the formation of the oxide semiconductor layer 522, x ₁ / y ₁ is 1/3 or more and 6 or less, further 1 or more and 6 or less, and z ₁ / y ₁ is 1/3 or more and 6 or less, It is preferable to use a polycrystalline target of 1 to 6 In-M-Zn oxide. When z ₁ / y ₁ is greater than or equal to 1 and less than or equal to 6, a CAAC-OS film is easily formed. Typical examples of the atomic ratio of the target metal element are In: M: Zn = 1: 1: 1, In: M: Zn = 1: 1: 1.2, In: M: Zn = 2: 1: 1. .5, In: M: Zn = 2: 1: 2.3, In: M: Zn = 2: 1: 3, In: M: Zn = 3: 1: 2, In: M: Zn = 4: 2. : 4.1 etc. Note that a CAAC-OS is an oxide semiconductor having a crystal part aligned in the c-axis, which will be described later. The CAAC-OS film preferably does not contain a spinel crystal structure. Accordingly, electrical characteristics and reliability of the transistor including the CAAC-OS film can be improved.

The target used for forming the oxide semiconductor layers 521 and 523 is x ₂ / y ₂ <x ₁ / y ₁ , and z ₂ / y ₂ is 1/3 or more and 6 or less, and further 1 or more and 6 or less. It is preferable that By setting z ₂ / y ₂ to 1 to 6, a CAAC-OS film can be easily formed. Typical examples of the atomic ratio of the target metal element are In: M: Zn = 1: 3: 2, In: M: Zn = 1: 3: 4, In: M: Zn = 1: 3: 6, In : M: Zn = 1: 3: 8, In: M: Zn = 1: 4: 4, In: M: Zn = 1: 4: 5, In: M: Zn = 1: 4: 6, In: M : Zn = 1: 4: 7, In: M: Zn = 1: 4: 8, In: M: Zn = 1: 5: 5, In: M: Zn = 1: 5: 6, In: M: Zn = 1: 5: 7, In: M: Zn = 1: 5: 8, In: M: Zn = 1: 6: 8, and the like.

The atomic ratio of the In-M-Zn oxide film includes a variation of plus or minus 40% of the above atomic ratio as an error. For example, the atomic ratio of metal elements contained in an oxide semiconductor film formed using an oxide target of In: M: Zn = 4: 2: 4.1 is approximately In: M: Zn = 4: 2: 3.

[Energy Band] Next, functions and effects of the oxide semiconductor layer 520 formed by stacking the oxide semiconductor layers 521 to 523 will be described with reference to an energy band structural diagram in FIG. FIG. 17A is an enlarged view of the channel region of the OS transistor 502, and is a partially enlarged view of FIG. FIG. 17B illustrates an energy band structure of a portion (a channel formation region of the OS transistor 502) indicated by a dotted line z1-z2 in FIG. Hereinafter, the OS transistor 502 will be described as an example, but the same applies to the OS transistors 501, 503 to 506.

In FIG. 17B, Ec512, Ec521, Ec522, Ec523, and Ec513 are the conduction band minimums of the insulating layer 512, the oxide semiconductor layer 521, the oxide semiconductor layer 522, the oxide semiconductor layer 523, and the insulating layer 513, respectively. Indicates energy.

Here, the difference between the vacuum level and the energy at the bottom of the conduction band (also referred to as “electron affinity”) is defined as the energy gap based on the difference between the vacuum level and the energy at the top of the valence band (also referred to as ionization potential). Subtracted value. The energy gap can be measured using a spectroscopic ellipsometer (HORIBA JOBIN YVON UT-300). The energy difference between the vacuum level and the upper end of the valence band can be measured using an ultraviolet photoelectron spectroscopy (UPS) apparatus (PHI VersaProbe).

Note that an In—Ga—Zn oxide formed using a sputtering target with an atomic ratio of In: Ga: Zn = 1: 3: 2 has an energy gap of approximately 3.5 eV and an electron affinity of approximately 4.5 eV. . An In—Ga—Zn oxide formed using a sputtering target with an atomic ratio of In: Ga: Zn = 1: 3: 4 has an energy gap of about 3.4 eV and an electron affinity of about 4.5 eV. . An In—Ga—Zn oxide formed using a sputtering target with an atomic ratio of In: Ga: Zn = 1: 3: 6 has an energy gap of about 3.3 eV and an electron affinity of about 4.5 eV. . An In—Ga—Zn oxide formed using a sputtering target with an atomic ratio of In: Ga: Zn = 1: 6: 2 has an energy gap of about 3.9 eV and an electron affinity of about 4.3 eV. . An In—Ga—Zn oxide formed using a sputtering target with an atomic ratio of In: Ga: Zn = 1: 6: 8 has an energy gap of approximately 3.5 eV and an electron affinity of approximately 4.4 eV. . An In—Ga—Zn oxide formed using a sputtering target with an atomic ratio of In: Ga: Zn = 1: 6: 10 has an energy gap of about 3.5 eV and an electron affinity of about 4.5 eV. . An In—Ga—Zn oxide formed using a sputtering target with an atomic ratio of In: Ga: Zn = 1: 1: 1 has an energy gap of about 3.2 eV and an electron affinity of about 4.7 eV. . An In—Ga—Zn oxide formed using a sputtering target with an atomic ratio of In: Ga: Zn = 3: 1: 2 has an energy gap of about 2.8 eV and an electron affinity of about 5.0 eV. .

Since the insulating layers 512 and 513 are insulators, Ec513 and Ec512 are closer to the vacuum level (smaller electron affinity) than Ec521, Ec522, and Ec523.

Ec521 is closer to the vacuum level than Ec522. Specifically, Ec521 is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more or 0.15 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less than Ec522. It is preferable that it is close to.

Ec523 is closer to the vacuum level than Ec522. Specifically, Ec523 is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more or 0.15 eV or more, and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less than Ec522. It is preferable that it is close to.

In addition, a mixed region is formed in the vicinity of the interface between the oxide semiconductor layer 521 and the oxide semiconductor layer 522 and in the vicinity of the interface between the oxide semiconductor layer 522 and the oxide semiconductor layer 523. Changes continuously. That is, there are almost no levels at these interfaces.

Therefore, in the stacked structure having the energy band structure, electrons move mainly in the oxide semiconductor layer 522. Therefore, even when a level exists at the interface between the oxide semiconductor layer 521 and the insulating layer 512 or the interface between the oxide semiconductor layer 523 and the insulating layer 513, the level hardly affects the movement of electrons. In addition, since there are no or almost no levels at the interface between the oxide semiconductor layer 521 and the oxide semiconductor layer 522 and the interface between the oxide semiconductor layer 523 and the oxide semiconductor layer 522, electron migration in this region It does not inhibit. Therefore, the OS transistor 502 having the stacked structure of the oxide semiconductor can have high field effect mobility.

Note that as illustrated in FIG. 17B, trap levels Et502 caused by impurities and defects are formed near the interface between the oxide semiconductor layer 521 and the insulating layer 512 and in the vicinity of the interface between the oxide semiconductor layer 523 and the insulating layer 513. However, the oxide semiconductor layer 521 and the oxide semiconductor layer 523 allow the oxide semiconductor layer 522 and the trap level to be separated from each other.

The OS transistor 502 is formed so that an upper surface and a side surface of the oxide semiconductor layer 522 are in contact with the oxide semiconductor layer 523 and a lower surface of the oxide semiconductor layer 522 is in contact with the oxide semiconductor layer 521 in the channel width direction (see FIG. 11 (C)). In this manner, with the structure in which the oxide semiconductor layer 522 is covered with the oxide semiconductor layer 521 and the oxide semiconductor layer 523, the influence of the trap states can be further reduced.

Note that in the case where the energy difference between Ec521 or Ec523 and Ec522 is small, the electrons in the oxide semiconductor layer 522 may reach the trap level exceeding the energy difference. By trapping electrons in the trap level, negative fixed charges are generated at the interface of the insulating film, and the threshold voltage of the transistor is shifted in the positive direction.

Therefore, when the energy difference between Ec521, Ec523, and Ec522 is 0.1 eV or more, preferably 0.15 eV or more, the threshold voltage fluctuation of the transistor is reduced, and the electrical characteristics of the transistor are good. Therefore, it is preferable.

The band gap of the oxide semiconductor layer 521 and the oxide semiconductor layer 523 is preferably wider than the band gap of the oxide semiconductor layer 522.

For the oxide semiconductor layer 521 and the oxide semiconductor layer 523, for example, a material containing (Ga, Y, Zr, La, Ce, or Nd at a higher atomic ratio than the oxide semiconductor layer 522 can be used. Specifically, the atomic ratio is 1.5 times or more, preferably 2 times or more, and more preferably 3 times or more.The above element is strongly bonded to oxygen, so that oxygen vacancies are generated in the oxide semiconductor. In other words, the oxide semiconductor layer 521 and the oxide semiconductor layer 523 have less oxygen vacancies than the oxide semiconductor layer 522.

The oxide semiconductor layer 521, the oxide semiconductor layer 522, and the oxide semiconductor layer 523 each include at least indium, zinc, and M (M is Ga, Sn, Y, Zr, La, Ce, or Nd). In the case of using a Zn oxide, the oxide semiconductor layer 521 has In: M: Zn = x ₁ : y ₁ : z ₁ [atomic ratio], and the oxide semiconductor layer 522 has In: M: Zn = x ₂ : y _2. : Z ₂ [atomic number ratio] and the oxide semiconductor layer 523 is In: M: Zn = x ₃ : y ₃ : z ₃ [atomic number ratio], y ₁ / x ₁ and y ₃ / x ₃ are y it is preferably larger than ₂ / _{x 2.} y ₁ / x ₁ and y ₃ / x ₃ are 1.5 times or more, preferably 2 times or more, more preferably 3 times or more than y ₂ / x ₂ . At this time, in the oxide semiconductor layer 522, when y ₂ is x ₂ or more, the electrical characteristics of the transistor can be stabilized. However, when y ₂ is 3 times or more of x ₂ , the field-effect mobility of the transistor is lowered. Therefore, y ₂ is preferably less than 3 times x ₂ .

An In-M-Zn oxide film that satisfies these conditions can be formed using an In-M-Zn oxide target that satisfies the above-described atomic ratio of metal elements.

The atomic ratio of In and M excluding Zn and O in the oxide semiconductor layer 521 and the oxide semiconductor layer 523 is preferably that In is less than 50 atomic%, M is higher than 50 atomic%, and more preferably, In is 25 atomic%. %, M is higher than 75 atomic%. The atomic ratio of In and M excluding Zn and O in the oxide semiconductor layer 522 is preferably higher than In at 25 atomic%, lower than 75 atomic%, and more preferably higher than 34 atomic% in In. , M is less than 66 atomic%.

In some cases, at least one of the oxide semiconductor layer 521 and the oxide semiconductor layer 523 does not need to contain indium. For example, the oxide semiconductor layer 521 and / or the oxide semiconductor layer 523 can be formed using a gallium oxide film.

The thicknesses of the oxide semiconductor layer 521 and the oxide semiconductor layer 523 are 3 nm to 100 nm, preferably 3 nm to 50 nm. The thickness of the oxide semiconductor layer 522 is 3 nm to 200 nm, preferably 3 nm to 100 nm, more preferably 3 nm to 50 nm. The oxide semiconductor layer 523 is preferably thinner than the oxide semiconductor layer 521 and the oxide semiconductor layer 523.

Note that in order to impart stable electrical characteristics to an OS transistor including an oxide semiconductor as a channel, it is effective to reduce the impurity concentration in the oxide semiconductor so that the oxide semiconductor is intrinsic or substantially intrinsic. . Here, substantially intrinsic means that the carrier density of the oxide semiconductor is less than 1 × 10 ¹⁷ / cm ³ , preferably less than 1 × 10 ¹⁵ / cm ³ , and more preferably 1 × 10 10. It indicates less than ¹³ / cm ³ .

In the oxide semiconductor, hydrogen, nitrogen, carbon, silicon, and metal elements other than main components are impurities. For example, hydrogen and nitrogen contribute to the formation of donor levels and increase the carrier density. Silicon contributes to the formation of impurity levels in an oxide semiconductor. The impurity level becomes a trap and may deteriorate the electrical characteristics of the transistor. Therefore, it is preferable to reduce the impurity concentration in the oxide semiconductor layer 521, the oxide semiconductor layer 522, and the oxide semiconductor layer 523 or at the respective interfaces.

In order to make an oxide semiconductor intrinsic or substantially intrinsic, in SIMS analysis, for example, at a certain depth of the oxide semiconductor or in a certain region of the oxide semiconductor, the silicon concentration is set to 1 × 10 ¹⁹ atoms / Less than cm ³ , preferably less than 5 × 10 ¹⁸ atoms / cm ³ , more preferably less than 1 × 10 ¹⁸ atoms / cm ³ . The hydrogen concentration is, for example, 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ atoms / cm ³ or less at a certain depth of the oxide semiconductor or in a region where the oxide semiconductor is present. It is preferably 1 × 10 ¹⁹ atoms / cm ³ or less, more preferably 5 × 10 ¹⁸ atoms / cm ³ or less. The nitrogen concentration is, for example, less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less at a certain depth of the oxide semiconductor or in a region where the oxide semiconductor is present. It is preferably 1 × 10 ¹⁸ atoms / cm ³ or less, more preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

In addition, in the case where the oxide semiconductor includes crystals, the crystallinity of the oxide semiconductor may be reduced if silicon or carbon is included at a high concentration. In order not to decrease the crystallinity of the oxide semiconductor, for example, the silicon concentration is less than 1 × 10 ¹⁹ atoms / cm ³ , preferably 5 at a certain depth of the oxide semiconductor or in a certain region of the oxide semiconductor. It suffices to have a portion that is less than × 10 ¹⁸ atoms / cm ³ , more preferably less than 1 × 10 ¹⁸ atoms / cm ³ . In addition, for example, at a certain depth of the oxide semiconductor or in a certain region of the oxide semiconductor, the carbon concentration is less than 1 × 10 ¹⁹ atoms / cm ³ , preferably less than 5 × 10 ¹⁸ atoms / cm ³ , and more preferably May have a portion less than 1 × 10 ¹⁸ atoms / cm ³ .

Further, the off-state current of the transistor in which the oxide semiconductor purified as described above is used for a channel formation region is extremely small. For example, when the voltage between the source and the drain is about 0.1 V, 5 V, or 10 V, the off-current normalized by the channel width of the transistor is reduced from several yA / μm to several zA / μm. It becomes possible.

[Off Current] In this specification, unless otherwise specified, off current refers to drain current when a transistor is off (also referred to as a non-conduction state or a cutoff state). The off state is a state where the voltage Vgs between the gate and the source is lower than the threshold voltage Vth in the n-channel transistor, and the voltage Vgs between the gate and the source in the p-channel transistor unless otherwise specified. Is higher than the threshold voltage Vth. For example, the off-state current of an n-channel transistor sometimes refers to a drain current when the voltage Vgs between the gate and the source is lower than the threshold voltage Vth.

The off-state current of the transistor may depend on Vgs. Therefore, the off-state current of the transistor being I or less sometimes means that there exists a value of Vgs at which the off-state current of the transistor is I or less. The off-state current of a transistor may refer to an off-state current in an off state at a predetermined Vgs, an off state in a Vgs within a predetermined range, or an off state in Vgs at which a sufficiently reduced off current is obtained.

As an example, when the threshold voltage Vth is 0.5 V, the drain current when Vgs is 0.5 V is 1 × 10 ⁻⁹ A, and the drain current when Vgs is 0.1 V is 1 × 10 ⁻¹³ A. Assume that the n-channel transistor has a drain current of 1 × 10 ⁻¹⁹ A when Vgs is −0.5 V and a drain current of 1 × 10 ⁻²² A when Vgs is −0.8 V. Since the drain current of the transistor is 1 × 10 ⁻¹⁹ A or less when Vgs is −0.5 V or Vgs is in the range of −0.5 V to −0.8 V, the off-state current of the transistor is 1 It may be said that it is below ^x10 <^-19> A. Since there is Vgs at which the drain current of the transistor is 1 × 10 ⁻²² A or less, the off-state current of the transistor may be 1 × 10 ⁻²² A or less.

In this specification, the off-state current of a transistor having the channel width W may be represented by a current value flowing around the channel width W. In some cases, the current value flows around a predetermined channel width (for example, 1 μm). In the latter case, the unit of off-current may be represented by a unit having a dimension of current / length (for example, A / μm).

The off-state current of a transistor may depend on temperature. In this specification, off-state current may represent off-state current at room temperature, 60 ° C., 85 ° C., 95 ° C., or 125 ° C. unless otherwise specified. Alternatively, at a temperature at which reliability of the semiconductor device or the like including the transistor is guaranteed, or a temperature at which the semiconductor device or the like including the transistor is used (for example, any one of 5 ° C. to 35 ° C.). May represent off-state current. The off-state current of a transistor is I or less means that room temperature, 60 ° C., 85 ° C., 95 ° C., 125 ° C., a temperature at which the reliability of the semiconductor device including the transistor is guaranteed, or the transistor is included. There may be a case where there is a value of Vgs at which the off-state current of the transistor is equal to or lower than I at a temperature at which the semiconductor device or the like is used (for example, any one temperature of 5 ° C. to 35 ° C.).

The off-state current of the transistor may depend on the voltage Vds between the drain and the source. In this specification, the off-state current is Vds of 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V unless otherwise specified. Or an off-current at 20V. Alternatively, Vds in which reliability of a semiconductor device or the like including the transistor is guaranteed, or an off-current in Vds used in the semiconductor device or the like including the transistor may be represented. The off-state current of the transistor is equal to or less than I. Vds is 0.1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 12V, 16V, 20V There is a value of Vgs at which the off-state current of the transistor is less than or equal to Vds at which Vds guarantees the reliability of the semiconductor device including the transistor or Vds used in the semiconductor device or the like including the transistor. May be pointed to.

In the description of the off-state current, the drain may be read as the source. That is, the off-state current sometimes refers to a current that flows through the source when the transistor is off.

In this specification, the term “leakage current” may be used to mean the same as off-state current.

In this specification, off-state current may refer to current that flows between a source and a drain when a transistor is off, for example.

[Crystal Structure of Oxide Semiconductor Film] The structure of the oxide semiconductor film constituting the oxide semiconductor layer 520 is described below. Note that in this specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

An oxide semiconductor film is roughly classified into a non-single-crystal oxide semiconductor film and a single-crystal oxide semiconductor film. The non-single-crystal oxide semiconductor film refers to a CAAC-OS (C Axis Crystalline Oxide Semiconductor) film, a polycrystalline oxide semiconductor film, a microcrystalline oxide semiconductor film, an amorphous oxide semiconductor film, or the like.

<CAAC-OS Film> The CAAC-OS film is one of oxide semiconductor films having a plurality of c-axis aligned crystal parts.

Confirmation of a plurality of crystal parts by observing a bright field image of a CAAC-OS film and a combined analysis image (also referred to as a high-resolution TEM image) of a CAAC-OS film with a transmission electron microscope (TEM: Transmission Electron Microscope). Can do. On the other hand, a clear boundary between crystal parts, that is, a crystal grain boundary (also referred to as a grain boundary) cannot be confirmed even by a high-resolution TEM image. Therefore, it can be said that the CAAC-OS film is unlikely to decrease in electron mobility due to crystal grain boundaries.

When a high-resolution TEM image of a cross section of the CAAC-OS film is observed from a direction substantially parallel to the sample surface, it can be confirmed that metal atoms are arranged in layers in the crystal part. Each layer of metal atoms has a shape reflecting unevenness of a surface (also referred to as a formation surface) or an upper surface on which the CAAC-OS film is formed, and is arranged in parallel with the formation surface or the upper surface of the CAAC-OS film. .

On the other hand, when a high-resolution TEM image of a plane of the CAAC-OS film is observed from a direction substantially perpendicular to the sample surface, it can be confirmed that metal atoms are arranged in a triangular shape or a hexagonal shape in a crystal part. However, there is no regularity in the arrangement of metal atoms between different crystal parts.

When structural analysis is performed on a CAAC-OS film using an X-ray diffraction (XRD) apparatus, for example, in the analysis of a CAAC-OS film having an InGaZnO ₄ crystal by an out-of-plane method, A peak may appear when the diffraction angle (2θ) is around 31 °. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, the crystal of the CAAC-OS film has c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formation surface or the top surface. Can be confirmed.

In the analysis of a CAAC-OS film having an InGaZnO ₄ crystal by an out-of-plane method, a peak may also appear when 2θ is around 36 ° in addition to a peak where 2θ is around 31 °. A peak at 2θ of around 36 ° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS film. The CAAC-OS film preferably has a peak at 2θ of around 31 ° and no peak at 2θ of around 36 °.

The CAAC-OS film is an oxide semiconductor film with a low impurity concentration. The impurity is an element other than the main component of the oxide semiconductor film, such as hydrogen, carbon, silicon, or a transition metal element. In particular, an element such as silicon, which has a stronger bonding force with oxygen than the metal element included in the oxide semiconductor film, disturbs the atomic arrangement of the oxide semiconductor film by depriving the oxide semiconductor film of oxygen, and has crystallinity. It becomes a factor to reduce. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radii (or molecular radii). Therefore, if they are contained inside an oxide semiconductor film, the atomic arrangement of the oxide semiconductor film is disturbed, resulting in crystallinity. It becomes a factor to reduce. Note that the impurity contained in the oxide semiconductor film might serve as a carrier trap or a carrier generation source.

The CAAC-OS film is an oxide semiconductor film with a low density of defect states. For example, oxygen vacancies in the oxide semiconductor film can serve as carrier traps or can generate carriers by capturing hydrogen.

A low impurity concentration and a low density of defect states (small number of oxygen vacancies) is called high purity intrinsic or substantially high purity intrinsic. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier generation sources, and thus can have a low carrier density. Therefore, a transistor including the oxide semiconductor film is unlikely to have electrical characteristics (also referred to as normally-on) in which the threshold voltage is negative. A highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has few carrier traps. Therefore, a transistor including the oxide semiconductor film has a small change in electrical characteristics and has high reliability. Note that the charge trapped in the carrier trap of the oxide semiconductor film takes a long time to be released, and may behave as if it were a fixed charge. Therefore, a transistor including an oxide semiconductor film with a high impurity concentration and a high density of defect states may have unstable electrical characteristics.

An OS transistor using a CAAC-OS film has little variation in electrical characteristics due to irradiation with visible light or ultraviolet light.

<Microcrystalline Oxide Semiconductor Film> The microcrystalline oxide semiconductor film has a region where a crystal part can be confirmed and a region where a clear crystal part cannot be confirmed in a high-resolution TEM image. In most cases, a crystal part included in the microcrystalline oxide semiconductor film has a size of 1 nm to 100 nm, or 1 nm to 10 nm. In particular, an oxide semiconductor film including a nanocrystal (nc) that is a microcrystal of 1 nm to 10 nm, or 1 nm to 3 nm is referred to as an nc-OS (nanocrystalline Oxide Semiconductor) film. In the nc-OS film, for example, a crystal grain boundary may not be clearly confirmed in a high-resolution TEM image.

The nc-OS film has periodicity in atomic arrangement in a very small region (eg, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS film does not have regularity in crystal orientation between different crystal parts. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS film may not be distinguished from an amorphous oxide semiconductor film depending on an analysis method. For example, when structural analysis is performed on the nc-OS film using an XRD apparatus using X-rays having a diameter larger than that of the crystal part, a peak indicating a crystal plane is not detected in the analysis by the out-of-plane method. Further, when electron diffraction (also referred to as limited-field electron diffraction) using an electron beam with a probe diameter (for example, 50 nm or more) larger than that of the crystal part is performed on the nc-OS film, a diffraction pattern such as a halo pattern is observed. Is done. On the other hand, when nanobeam electron diffraction is performed on the nc-OS film using an electron beam having a probe diameter that is close to or smaller than the size of the crystal part, spots are observed. In addition, when nanobeam electron diffraction is performed on the nc-OS film, a region with high luminance may be observed so as to draw a circle (in a ring shape). Further, when nanobeam electron diffraction is performed on the nc-OS film, a plurality of spots may be observed in the ring-shaped region.

The nc-OS film is an oxide semiconductor film that has higher regularity than an amorphous oxide semiconductor film. Therefore, the nc-OS film has a lower density of defect states than the amorphous oxide semiconductor film. Note that the nc-OS film does not have regularity in crystal orientation between different crystal parts. Therefore, the nc-OS film has a higher density of defect states than the CAAC-OS film.

<Amorphous Oxide Semiconductor Film> The amorphous oxide semiconductor film is an oxide semiconductor film having an irregular atomic arrangement in the film and having no crystal part. An oxide semiconductor film having an amorphous state such as quartz is an example.

In the amorphous oxide semiconductor film, a crystal part cannot be confirmed in a high-resolution TEM image. When structural analysis using an XRD apparatus is performed on an amorphous oxide semiconductor film, a peak indicating a crystal plane is not detected by analysis using an out-of-plane method. Further, when electron diffraction is performed on the amorphous oxide semiconductor film, a halo pattern is observed. Further, when nanobeam electron diffraction is performed on an amorphous oxide semiconductor film, no spot is observed and a halo pattern is observed.

An oxide semiconductor film may have a structure exhibiting physical properties between the nc-OS film and the amorphous oxide semiconductor film. An oxide semiconductor film having such a structure is particularly referred to as an amorphous-like oxide semiconductor (a-like OS) film.

In the a-like OS film, a void (also referred to as a void) may be observed in a high-resolution TEM image. Moreover, in a high-resolution TEM image, it has the area | region which can confirm a crystal part clearly, and the area | region which cannot confirm a crystal part. In some cases, the a-like OS film is crystallized by a small amount of electron irradiation as observed by a TEM, and a crystal part is grown. On the other hand, in the case of a good-quality nc-OS film, crystallization due to a small amount of electron irradiation comparable to that observed by TEM is hardly observed.

The size of the crystal part of the a-like OS film and the nc-OS film can be measured using a high-resolution TEM image. For example, a crystal of InGaZnO ₄ has a layered structure, and two Ga—Zn—O layers are provided between In—O layers. The unit cell of InGaZnO ₄ crystal has a structure in which a total of nine layers including three In—O layers and six Ga—Zn—O layers are stacked in the c-axis direction. Therefore, the distance between these adjacent layers is approximately the same as the lattice spacing (also referred to as d value) of the (009) plane, and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, paying attention to the lattice fringes in the high-resolution TEM image, each lattice fringe corresponds to the ab plane of the InGaZnO ₄ crystal in a portion where the interval between the lattice fringes is 0.28 nm or more and 0.30 nm or less.

An oxide semiconductor film may have a different film density for each structure. For example, when the composition of a certain oxide semiconductor film is known, the structure of the oxide semiconductor film can be estimated by comparing with the film density of a single crystal oxide semiconductor film having the same composition as the composition. For example, the film density of the a-like OS film is 78.6% or more and less than 92.3% with respect to the film density of the single crystal oxide semiconductor film. For example, the film density of the nc-OS film and the film density of the CAAC-OS film are 92.3% or more and less than 100% with respect to the film density of the single crystal oxide semiconductor film. Note that it is difficult to form an oxide semiconductor film with a film density of less than 78% with respect to the single crystal oxide semiconductor film.

The above will be described using a specific example. For example, in an oxide semiconductor film that satisfies In: Ga: Zn = 1: 1: 1 [atomic ratio], the film density of single crystal InGaZnO ₄ having a rhombohedral structure is 6.357 g / cm ³ . Therefore, for example, in an oxide semiconductor film satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the film density of the a-like OS film is 5.0 g / cm ³ or more and 5.9 g / cm ^3. Less than. For example, in the oxide semiconductor film satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the film density of the nc-OS film and the film density of the CAAC-OS film are 5.9 g / cm ^3. The above is less than 6.3 g / cm ³ .

Note that a single crystal oxide semiconductor film having the same composition may not exist. In that case, by combining single crystal oxide semiconductor films having different compositions at an arbitrary ratio, the film density corresponding to the single crystal oxide semiconductor film having a desired composition can be calculated. The film density of the single crystal oxide semiconductor film having a desired composition may be calculated using a weighted average with respect to the ratio of combining single crystal oxide semiconductor films having different compositions. Note that the film density is preferably calculated by combining as few kinds of single crystal oxide semiconductor films as possible.

Note that the oxide semiconductor film may be a stacked film including two or more of an amorphous oxide semiconductor film, an a-like OS film, a microcrystalline oxide semiconductor film, and a CAAC-OS film, for example. .

<Board>
The substrate 510 is not limited to a simple support material, and may be a substrate on which other devices such as transistors are formed. In this case, one of the conductive layer 530, the conductive layer 541, and the conductive layer 542 of the OS transistor 501 may be electrically connected to the other device.

<Insulating layer>
The insulating layer 511 has a role of preventing diffusion of impurities from the substrate 510. The insulating layer 512 preferably has a role of supplying oxygen to the oxide semiconductor layer 520. Can bear. Therefore, the insulating layer 512 is preferably an insulating film containing oxygen, and more preferably an insulating film containing oxygen larger than the stoichiometric composition. For example, in TDS (Thermal Desorption Spectroscopy), the amount of released oxygen molecules is 1.0 × in the range where the surface temperature of the film is 100 ° C. or higher and 700 ° C. or lower, or 100 ° C. or higher and 500 ° C. or lower. The film is 10 ¹⁸ [molecules / cm ³ ] or more. In the case where the substrate 510 is a substrate over which another device is formed, the insulating layer 511 is preferably subjected to planarization treatment by a CMP (Chemical Mechanical Polishing) method or the like so that the surface is planarized.

The insulating layers 511 and 512 include aluminum oxide, aluminum oxynitride, magnesium oxide, silicon oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide and tantalum oxide, silicon nitride Alternatively, an insulating material such as silicon nitride oxide or aluminum nitride oxide, or a mixed material thereof can be used. Note that in this specification, oxynitride is a material having a higher oxygen content than nitrogen, and nitride oxide is a material having a higher nitrogen content than oxygen.

<Gate electrode>
The conductive layer 530 includes copper (Cu), tungsten (W), molybdenum (Mo), gold (Au), aluminum (Al), manganese (Mn), titanium (Ti), tantalum (Ta), nickel (Ni), Made of low resistance material such as chromium (Cr), lead (Pb), tin (Sn), iron (Fe), cobalt (Co), ruthenium (Ru), iridium (Ir), strontium (Sr), platinum (Pt) It is preferably formed of a simple substance, an alloy, or a compound containing these as a main component.

The conductive layer 530 may have a single-layer structure or a stacked structure including two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked on an aluminum film, a two-layer structure in which a titanium film is stacked on a titanium nitride film, and a two-layer structure in which a tungsten film is stacked on a titanium nitride film Layer structure, two-layer structure in which a tungsten film is stacked on a tantalum nitride film or tungsten nitride film, a three-layer structure in which a titanium film and an aluminum film are stacked on the titanium film, and a titanium film is further formed thereon, Cu Single layer structure of -Mn alloy film, two layer structure in which Cu film is laminated on Cu-Mn alloy film, Cu film is laminated on Cu-Mn alloy film, and Cu-Mn alloy film is further laminated thereon There are three-layer structures. In particular, a Cu—Mn alloy film is preferable because it has low electric resistance and can form manganese oxide at an interface with an insulating film containing oxygen to prevent Cu from diffusing.

The conductive layer 530 includes indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, and indium zinc oxide. Alternatively, a light-transmitting conductive material such as an indium tin oxide to which silicon oxide is added can be used. Alternatively, a stacked structure of the above light-transmitting conductive material and the above metal element can be employed.

Here, in the case where a certain transistor T has a pair of gates with a semiconductor film interposed therebetween, like the OS transistors 501 to 506, the signal A is supplied to one gate and the other gate has a signal A. A fixed potential Vb may be applied.

The signal A is a signal for controlling a conduction state or a non-conduction state, for example. The signal A may be a digital signal that takes two kinds of potentials, that is, the potential V1 or the potential V2 (V1> V2). For example, the potential V1 can be a high power supply potential and the potential V2 can be a low power supply potential. The signal A may be an analog signal.

The fixed potential Vb is a potential for controlling the threshold voltage VthA of the transistor T, for example. The fixed potential Vb may be the potential V1 or the potential V2. In this case, there is no need to separately provide a potential generation circuit for generating the fixed potential Vb, which is preferable. The fixed potential Vb may be a potential different from the potential V1 or the potential V2. In some cases, the threshold voltage VthA can be increased by lowering the fixed potential Vb. As a result, the drain current when the gate-source voltage Vgs is 0 V can be reduced, and the leakage current of the circuit including the transistor T can be reduced in some cases. For example, the fixed potential Vb may be set lower than the low power supply potential. In some cases, the threshold voltage VthA can be lowered by increasing the fixed potential Vb. As a result, the drain current when the gate-source voltage Vgs is VDD may be improved, and the operation speed of the circuit including the transistor T may be improved. For example, the fixed potential Vb may be higher than the low power supply potential.

Further, the signal A may be supplied to one gate of the transistor T, and the signal B may be supplied to the other gate. The signal B is a signal for controlling the conduction state or non-conduction state of the transistor T, for example. The signal B may be a digital signal that takes two kinds of potentials, that is, the potential V3 or the potential V4 (V3> V4). For example, the potential V3 can be a high power supply potential and the potential V4 can be a low power supply potential. The signal B may be an analog signal.

When both the signal A and the signal B are digital signals, the signal B may be a signal having the same digital value as the signal A. In this case, the on-state current of the transistor T may be improved and the operation speed of the circuit including the transistor T may be improved. At this time, the potential V1 of the signal A may be different from the potential V3 of the signal B. Further, the potential V2 of the signal A may be different from the potential V4 of the signal B. For example, when the gate insulating film corresponding to the gate to which the signal B is input is thicker than the gate insulating film corresponding to the gate to which the signal A is input, the potential amplitude (V3 to V4) of the signal B is It may be larger than the potential amplitude (V1-V2). By doing so, the influence of the signal A and the influence of the signal B on the conduction state or non-conduction state of the transistor T may be almost the same.

When both the signal A and the signal B are digital signals, the signal B may be a signal having a digital value different from that of the signal A. In this case, the transistor T can be controlled separately by the signal A and the signal B, and a higher function may be realized. For example, when the transistor T is an n-channel transistor, the transistor A is in a conductive state only when the signal A is the potential V1 and the signal B is the potential V3, or the signal A is the potential V2 and the signal B In the case where the transistor is non-conductive only when the potential is V4, the function of a NAND circuit, a NOR circuit, or the like may be realized with one transistor. The signal B may be a signal for controlling the threshold voltage VthA. For example, the signal B may be a signal having a different potential between a period in which a circuit including the transistor T is operating and a period in which the circuit is not operating. The signal B may be a signal having a different potential according to the operation mode of the circuit. In this case, the potential of the signal B may not be switched as frequently as the signal A.

When both the signal A and the signal B are analog signals, the signal B is an analog signal having the same potential as the signal A, an analog signal obtained by multiplying the potential of the signal A by a constant, or the potential of the signal A is added or subtracted by a constant. An analog signal or the like may be used. In this case, the on-state current of the transistor T may be improved and the operation speed of the circuit including the transistor T may be improved. The signal B may be an analog signal different from the signal A. In this case, the transistor T can be controlled separately by the signal A and the signal B, and a higher function may be realized.

The signal A may be a digital signal and the signal B may be an analog signal. The signal A may be an analog signal and the signal B may be a digital signal.

Further, the fixed potential Va may be applied to one gate of the transistor T, and the fixed potential Vb may be applied to the other gate. When a fixed potential is applied to both gates of the transistor T, the transistor T may function as an element equivalent to a resistance element. For example, in the case where the transistor T is an n-channel transistor, the effective resistance of the transistor may be decreased (increased) by increasing (decreasing) the fixed potential Va or the fixed potential Vb. By making both the fixed potential Va and the fixed potential Vb higher (lower), an effective resistance lower (higher) than that obtained by a transistor having only one gate may be obtained.

<Gate insulation layer>
The insulating layer 513 is formed using an insulating film having a single-layer structure or a stacked structure. The insulating layer 513 includes aluminum oxide, magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. One or more insulating films can be used. The insulating layer 513 may be a stack of the above materials. Note that the insulating layer 513 may contain lanthanum (La), nitrogen, zirconium (Zr), or the like as an impurity. The insulating layer 511 can be formed in a manner similar to that of the insulating layer 513. The insulating layer 513 includes, for example, oxygen, nitrogen, silicon, hafnium, or the like. Specifically, it preferably contains hafnium oxide and silicon oxide or silicon oxynitride.

Hafnium oxide has a higher dielectric constant than silicon oxide or silicon oxynitride. Therefore, the thickness of the insulating layer 513 can be increased as compared with the case where silicon oxide is used, and thus leakage current due to tunneling current can be reduced. That is, a transistor with a small off-state current can be realized. Further, hafnium oxide having a crystal structure has a higher dielectric constant than hafnium oxide having an amorphous structure. Therefore, in order to obtain a transistor with low off-state current, it is preferable to use hafnium oxide having a crystal structure. Examples of the crystal structure include a monoclinic system and a cubic system. Note that one embodiment of the present invention is not limited thereto.

<Source electrode, drain electrode, back gate electrode>
The conductive layer 541, the conductive layer 542, and the conductive layer 531 can be formed in a manner similar to that of the conductive layer 530. The Cu—Mn alloy film has low electrical resistance and can form manganese oxide at the interface with the oxide semiconductor layer 520 to prevent Cu from being diffused. Therefore, the Cu—Mn alloy film can be used for the conductive layers 541 and 542. preferable.

<Protective insulation layer>
The insulating layer 514 preferably has a function of blocking oxygen, hydrogen, water, alkali metal, alkaline earth metal, or the like. By providing such an insulating layer 514, diffusion of oxygen from the oxide semiconductor layer 520 to the outside and entry of hydrogen, water, and the like into the oxide semiconductor layer 520 from the outside can be prevented. As the insulating layer 514, for example, a nitride insulating film can be used. Examples of the nitride insulating film include silicon nitride, silicon nitride oxide, aluminum nitride, and aluminum nitride oxide. Note that an oxide insulating film having a blocking effect of oxygen, hydrogen, water, or the like may be provided instead of the nitride insulating film having a blocking effect of oxygen, hydrogen, water, alkali metal, alkaline earth metal, or the like. Examples of the oxide insulating film having a blocking effect of oxygen, hydrogen, water, and the like include aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, and hafnium oxynitride.

An aluminum oxide film is preferable for application to the insulating layer 514 because it has a high blocking effect of preventing both hydrogen, moisture and other impurities, and oxygen from permeating the film. Therefore, the aluminum oxide film forms an oxide semiconductor layer 520 that prevents impurities such as hydrogen and moisture that cause variations in the electrical characteristics of the transistor from entering the oxide semiconductor layer 520 during and after the transistor manufacturing process. It is suitable for use as a protective film having an effect of preventing release of oxygen from the oxide semiconductor, which is a main component material, and preventing unnecessary release of oxygen from the insulating layer 512. In addition, oxygen contained in the aluminum oxide film can be diffused into the oxide semiconductor.

<Interlayer insulation layer>
In addition, an insulating layer 515 is preferably formed over the insulating layer 514. The insulating layer 515 can be formed using an insulating film having a single-layer structure or a stacked structure. The insulating film contains one or more of magnesium oxide, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. An insulating film can be used.

<Film formation method>
As a method for forming an insulating film, a conductive film, a semiconductor film, or the like constituting a semiconductor device, a sputtering method or a plasma CVD method is typical. It can be formed by other methods, for example, a thermal CVD method. As the thermal CVD method, for example, a MOCVD (Metal Organic Chemical Vapor Deposition) method can be used. Moreover, you may use ALD (Atomic Layer Deposition) method.

The thermal CVD method has an advantage that no defect is generated due to plasma damage because it is a film forming method that does not use plasma. In the thermal CVD method, the inside of the chamber may be under atmospheric pressure or reduced pressure, and the source gas and the oxidant may be simultaneously sent into the chamber, reacted in the vicinity of the substrate or on the substrate, and deposited on the substrate. .

Further, in the ALD method, film formation may be performed by setting the inside of the chamber to atmospheric pressure or reduced pressure, sequentially introducing source gases for reaction into the chamber, and repeating the order of introducing the gases. For example, by switching each switching valve (also referred to as a high-speed valve), two or more kinds of source gases are sequentially supplied to the chamber, so that a plurality of kinds of source gases are not mixed with the first source gas at the same time or thereafter. An active gas (such as argon or nitrogen) is introduced, and a second source gas is introduced. When the inert gas is introduced at the same time, the inert gas becomes a carrier gas, and the inert gas may be introduced at the same time when the second raw material gas is introduced. Further, instead of introducing the inert gas, the second raw material gas may be introduced after the first raw material gas is exhausted by evacuation. The first source gas is adsorbed on the surface of the substrate to form a first monoatomic layer, and reacts with a second source gas introduced later, so that the second monoatomic layer becomes the first monoatomic layer. A thin film is formed by being stacked on the atomic layer. By repeating this gas introduction sequence a plurality of times until the desired thickness is achieved, a thin film having excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of times the gas introduction sequence is repeated, precise film thickness adjustment is possible, which is suitable for manufacturing a fine FET.

The conductive film and the semiconductor film disclosed in the above-described embodiments can be formed by a film formation method such as an MOCVD method or an ALD method. For example, when forming an InGaZnO _x (X> 0) film, trimethylindium, trimethylgallium, and dimethylzinc are used. Note that the chemical formula of trimethylindium is (CH ₃ ) ₃ In. The chemical formula of trimethylgallium is (CH ₃ ) ₃ Ga. The chemical formula of dimethylzinc is Zn (CH ₃ ) ₂ . The invention is not limited to these combinations, triethyl gallium instead of trimethylgallium (chemical formula _{(C 2 H 5) 3 Ga} ) can be used, diethylzinc in place of dimethylzinc (chemical formula _Zn (C _{2 H} 5) ₂ ) can also be used.

For example, in the case where a tungsten film is formed by a film forming apparatus using ALD, an initial tungsten film is formed by repeatedly introducing WF ₆ gas and B ₂ H ₆ gas successively, and then WF ₆ gas and H _2. A tungsten film is formed using a gas. Note that SiH ₄ gas may be used instead of B ₂ H ₆ gas.

For example, in the case where an oxide semiconductor film, for example, an InGaZnO _x (X> 0) film is formed by a film formation apparatus using ALD, In (CH ₃ ) ₃ gas and O ₃ gas are sequentially introduced and InO is sequentially introduced. _Two layers are formed, and then Ga (CH ₃ ) ₃ gas and O ₃ gas are sequentially introduced repeatedly to form a GaO layer, and then Zn (CH ₃ ) ₂ gas and O ₃ gas are successively introduced repeatedly. A ZnO layer is formed. Note that the order of these layers is not limited to this example. Alternatively, a mixed compound layer such as an InGaO ₂ layer, an InZnO ₂ layer, a GaInO layer, a ZnInO layer, or a GaZnO layer may be formed by mixing these gases. Incidentally, instead of the O ₃ gas may be used the H _{2 O} gas obtained by bubbling with an inert gas such as Ar, but better to use an O ₃ gas containing no H are preferred. In addition, In (C ₂ H ₅ ) ₃ gas may be used instead of In (CH ₃ ) ₃ gas. Further, Ga (C ₂ H ₅ ) ₃ gas may be used instead of Ga (CH ₃ ) ₃ gas. Alternatively, Zn (CH ₃ ) ₂ gas may be used.

In this embodiment mode, a top-gate transistor structure is described; however, the present invention is not limited to this. For example, a bottom gate transistor or a planar transistor can be used.

The structures and methods described in this embodiment can be combined as appropriate with any of the structures and methods described in the other embodiments.

(Embodiment 4)
In this embodiment, an example of a cross-sectional structure of a semiconductor device according to one embodiment of the present invention will be described.

<Configuration example 1>
FIG. 18 is a cross-sectional view of the transistor 301, the transistor 302, and the resistor portion 303. Note that the transistor 302 can be used as the transistor 11 in FIG. 1A, and the resistor portion 303 can be used as the resistor portion 12 in FIG. The transistor 301 connected to the transistor 302 can be used as a transistor included in the internal circuit 14 in FIG. In FIG. 18, the transistor 301 having a channel formation region in the single crystal semiconductor substrate is located in the first layer, and the transistor 302 and the resistor portion 303 that are OS transistors are located in the second layer on the first layer. In this case, the cross-sectional structure of the semiconductor device is illustrated.

The transistor 301 may have a channel formation region in a semiconductor film or a semiconductor substrate of silicon, germanium, or the like that is amorphous, microcrystalline, polycrystalline, or single crystal. In the case where the transistor 301 is formed using a silicon thin film, amorphous silicon produced by a vapor deposition method such as a plasma CVD method or a sputtering method or amorphous silicon is formed on the thin film by a process such as laser annealing. Crystallized polycrystalline silicon, single crystal silicon in which hydrogen ions or the like are implanted into a single crystal silicon wafer and a surface layer portion is peeled off can be used.

As the semiconductor substrate 310 over which the transistor 301 is formed, for example, a silicon substrate, a germanium substrate, a silicon germanium substrate, or the like can be used. FIG. 18 illustrates the case where a single crystal silicon substrate is used as the semiconductor substrate 310.

The transistor 301 is electrically isolated by an element isolation method. As an element isolation method, a selective oxidation method (LOCOS method: Local Oxidation of Silicon method), a trench isolation method (STI method: Shallow Trench Isolation), or the like can be used. FIG. 18 illustrates the case where the transistor 301 is electrically isolated using a trench isolation method. Specifically, in FIG. 18, after a trench is formed in the semiconductor substrate 310 by etching or the like, the transistor 301 is isolated by an element isolation region 311 formed by embedding an insulator containing silicon oxide or the like in the trench. The case is illustrated.

The transistor 301 includes an impurity region 312a and an impurity region 312b. The impurity region 312a and the impurity region 312b function as a source or a drain of the transistor 301.

An insulating film 321 is provided over the transistor 301, and an opening is formed in the insulating film 321. In the opening, a conductive layer 313a connected to the impurity region 312a and a conductive layer 313b connected to the impurity region 312b are formed. In addition, the conductive layer 313 a is connected to a conductive layer 322 a formed over the insulating film 321, and the conductive layer 313 b is connected to a conductive layer 322 b formed over the insulating film 321.

An insulating film 323 is provided over the conductive layers 322a and 322b, and an opening is formed in the insulating film 323. A conductive layer 324 connected to the conductive layer 322a is formed in the opening. In addition, the conductive layer 324 is connected to a conductive layer 325 formed over the insulating film 323.

An insulating film 326 is provided over the conductive layer 325.

A transistor 302 that is an OS transistor is provided over the insulating film 326. The transistor 302 includes an oxide semiconductor layer 341 over the insulating film 326, a conductive layer 343a and a conductive layer 343b over the oxide semiconductor layer 341, and an insulating film 344 over the oxide semiconductor layer 341, the conductive layer 343a, and the conductive layer 343b. And a conductive layer 345 which is located over the insulating film 344 and has a region overlapping with the oxide semiconductor layer 341. Note that the conductive layer 343 a and the conductive layer 343 b function as a source electrode or a drain electrode of the transistor 302, the insulating film 344 functions as a gate insulating film of the transistor 302, and the conductive layer 345 includes a gate of the transistor 302. It has a function as an electrode.

In addition, a resistor portion 303 is provided over the insulating film 326. The resistor 303 includes the oxide semiconductor layer 342 over the insulating film 326, the conductive layers 343b and 343c over the oxide semiconductor layer 342, the insulating film 344 over the oxide semiconductor layer 342, the conductive layer 343b, and the conductive layer 343c. And having. Note that the oxide semiconductor layer 342 functions as a resistance layer in the resistor portion 303.

An insulating film 346 is provided over the insulating film 344 and the conductive layer 345. In addition, a conductive layer 352 and a conductive layer 353 are provided over the insulating film 346. The conductive layer 352 is connected to the conductive layer 325 through an opening provided in the insulating film 326, the insulating film 344, and the insulating film 346, and the opening provided in the insulating film 344, the insulating film 346, and the insulating film 351 is provided. And is connected to the conductive layer 343c. The conductive layer 353 is connected to the conductive layer 343 a through an opening provided in the insulating film 344 and the insulating film 346.

FIG. 18 illustrates the case where the transistor 302 has a single gate structure having one channel formation region corresponding to one conductive layer 345. However, the transistor 302 may have a multi-gate structure in which the oxide semiconductor layer 341 includes a plurality of channel formation regions by including a plurality of gate electrodes connected to each other. Alternatively, a structure having a back gate may be used.

As described above, the area of the semiconductor device can be reduced by stacking the transistor 301, the transistor 302, and the resistor portion 303. Alternatively, the transistor 302 and the resistor portion 303 may be stacked.

Note that the transistor 302 and the resistor portion 303 may be formed as in the transistor and resistor portion 101 illustrated in FIGS. Further, the transistor 302 may be formed as the transistor illustrated in FIGS.

The structures and methods described in this embodiment can be combined as appropriate with any of the structures and methods described in the other embodiments.

(Embodiment 5)
In this embodiment, an example in which the semiconductor device described in any of the above embodiments is applied to an electronic component and an example in which the semiconductor device is applied to an electronic device including the electronic component will be described with reference to FIGS.

FIG. 19A illustrates an example in which the semiconductor device described in any of the above embodiments is applied to an electronic component. Note that the electronic component is also referred to as a semiconductor package or an IC package. This electronic component has a plurality of standards and names depending on the terminal take-out direction and the shape of the terminal. Therefore, in this embodiment, an example will be described.

A circuit portion including a transistor as described in the above embodiment is completed by combining a plurality of detachable components with a printed circuit board through an assembly process (post-process).

The post-process can be completed through each process shown in FIG. Specifically, after the element substrate obtained in the previous process is completed (step S1), the back surface of the substrate is ground (step S2). This is because by reducing the thickness of the substrate at this stage, it is possible to reduce the warpage of the substrate in the previous process and to reduce the size of the component.

A dicing process is performed in which the back surface of the substrate is ground to separate the substrate into a plurality of chips. Then, a die bonding process is performed in which the separated chips are individually picked up and mounted on the lead frame and bonded (step S3). For the bonding between the chip and the lead frame in this die bonding process, a suitable method is appropriately selected according to the product, such as bonding with a resin or bonding with a tape. The die bonding step may be mounted on the interposer and bonded.

Next, wire bonding is performed in which the lead of the lead frame and the electrode on the chip are electrically connected by a thin metal wire (wire) (step S4). A silver wire or a gold wire can be used as the metal thin wire. For wire bonding, ball bonding or wedge bonding can be used.

The wire-bonded chip is subjected to a molding process that is sealed with an epoxy resin or the like (step S5). By performing the molding process, the inside of the electronic component is filled with resin, which can reduce damage to the built-in circuit part and wires due to mechanical external force, and can reduce deterioration of characteristics due to moisture and dust. it can.

Next, the lead of the lead frame is plated. Then, the lead is cut and molded (step S6). By this plating treatment, rusting of the lead can be prevented, and soldering when mounting on a printed circuit board can be performed more reliably.

Next, a printing process (marking) is performed on the surface of the package (step S7). An electronic component is completed through a final inspection process (step S8) (step S9).

The electronic component described above can include the semiconductor device described in the above embodiment. Therefore, an electronic component with reduced power consumption can be realized.

FIG. 19B is a schematic perspective view of the completed electronic component. FIG. 19C illustrates an electronic component 1700 on the circuit board 1704 illustrated in FIG. FIG. 19B shows a schematic perspective view of a QFP (Quad Flat Package) as an example of an electronic component. An electronic component 1700 shown in FIGS. 19B and 19C shows a lead 1701 and a circuit portion 1703. An electronic component 1700 illustrated in FIG. 19B is mounted on a printed board 1702, for example. A plurality of such electronic components 1700 are combined and each is electrically connected on the printed circuit board 1702 so that it can be mounted inside the electronic device. The completed circuit board 1704 is provided inside an electronic device or the like.

In addition, a semiconductor device or an electronic component according to one embodiment of the present invention reproduces a recording medium such as a display device, a personal computer, and a recording medium (typically, a DVD: Digital Versatile Disc and the like) For a device having a display capable of displaying the In addition, as an electronic device in which the semiconductor device according to one embodiment of the present invention can be used, a mobile phone, a game machine including a portable type, a portable information terminal, an electronic book terminal, a video camera, a digital still camera, or the like, goggles Type display (head-mounted display), navigation system, sound playback device (car audio, digital audio player, etc.), copier, facsimile, printer, printer multifunction device, automatic teller machine (ATM), vending machine, medical equipment Etc. Specific examples of these electronic devices are shown in FIGS.

FIG. 20A illustrates a portable game machine, which includes a housing 5001, a housing 5002, a display portion 5003, a display portion 5004, a microphone 5005, speakers 5006, operation keys 5007, a stylus 5008, and the like. The semiconductor device according to one embodiment of the present invention can be used for various integrated circuits of a portable game machine. Note that although the portable game machine illustrated in FIG. 20A includes two display portions 5003 and 5004, the number of display portions included in the portable game device is not limited thereto.

FIG. 20B illustrates a portable information terminal which includes a first housing 5601, a second housing 5602, a first display portion 5603, a second display portion 5604, a connection portion 5605, operation keys 5606, and the like. The semiconductor device according to one embodiment of the present invention can be used for various integrated circuits of a portable information terminal. The first display portion 5603 is provided in the first housing 5601 and the second display portion 5604 is provided in the second housing 5602. The first housing 5601 and the second housing 5602 are connected by a connection portion 5605, and the angle between the first housing 5601 and the second housing 5602 can be changed by the connection portion 5605. is there. The video on the first display portion 5603 may be switched according to the angle between the first housing 5601 and the second housing 5602 in the connection portion 5605. Further, a display device to which a function as a position input device is added to at least one of the first display portion 5603 and the second display portion 5604 may be used. Note that the function as a position input device can be added by providing a touch panel on the display device. Alternatively, the function as a position input device can be added by providing a photoelectric conversion element called a photosensor in a pixel portion of a display device.

FIG. 20C illustrates a laptop personal computer, which includes a housing 5401, a display portion 5402, a keyboard 5403, a pointing device 5404, and the like. The semiconductor device according to one embodiment of the present invention can be used for various integrated circuits of a notebook personal computer.

FIG. 20D illustrates an electric refrigerator-freezer, which includes a housing 5301, a refrigerator door 5302, a refrigerator door 5303, and the like. The semiconductor device according to one embodiment of the present invention can be used for various integrated circuits of an electric refrigerator-freezer.

FIG. 20E illustrates a video camera, which includes a first housing 5801, a second housing 5802, a display portion 5803, operation keys 5804, a lens 5805, a connection portion 5806, and the like. The semiconductor device according to one embodiment of the present invention can be used for various integrated circuits of a video camera. The operation key 5804 and the lens 5805 are provided in the first housing 5801, and the display portion 5803 is provided in the second housing 5802. The first housing 5801 and the second housing 5802 are connected by a connection portion 5806, and the angle between the first housing 5801 and the second housing 5802 can be changed by the connection portion 5806. is there. The video on the display portion 5803 may be switched in accordance with the angle between the first housing 5801 and the second housing 5802 in the connection portion 5806.

FIG. 20F illustrates an automobile, which includes a car body 5101, wheels 5102, a dashboard 5103, lights 5104, and the like. The semiconductor device according to one embodiment of the present invention can be used for various integrated circuits of an automobile.

The structures and methods described in this embodiment can be combined as appropriate with any of the structures and methods described in the other embodiments.

DESCRIPTION OF SYMBOLS 10 Semiconductor device 11 Transistor 12 Resistance part 13 Input / output terminal 14 Internal circuit 15 Power supply line 16 Signal line 17 Control signal generation circuit 20 Semiconductor device 21 Transistor 22 Resistance part 23 Input / output terminal 24 Internal circuit 25 Power supply line 26 Signal line 27 Control signal Generation circuit 30 Semiconductor device 31 Transistor 33 Input / output terminal 34 Internal circuit 35 Power supply line 36 Signal line 37 Control signal generation circuit 40 Semiconductor device 42 Resistor 43 Input / output terminal 44 Internal circuit 45 Power supply line 46 Signal line 50 Semiconductor device 51 Transistor 52 Resistor 53 Input / output terminal 54 Internal circuit 55 Power supply line 56 Signal line 57 Control signal generating circuit 58 Transistor 60 Semiconductor device 61 Transistor 62 Resistor 63 Input / output terminal 64 Internal circuit 65 Power supply line 66 Signal line 67 Control signal generating circuit 68 Transistor 69 Capacitance element 0 Semiconductor device 80 Semiconductor device 100 Transistor 101 Resistor 110 Substrate 112 Insulating layer 113 Insulating layer 114 Insulating layer 115 Insulating layer 120 Oxide semiconductor layer 121 Oxide semiconductor layer 122 Oxide semiconductor layer 130 Conductive layer 131 Conductive layer 141 Conductive layer 142 Conductive layer 143 Conductive layer 200 Resistor 301 Transistor 302 Transistor 303 Resistor 310 Semiconductor substrate 311 Element isolation region 312a Impurity region 312b Impurity region 313a Conductive layer 313b Conductive layer 321 Insulating film 322a Conductive layer 322b Conductive layer 323 Insulating film 324 Conductive layer 325 Conductive layer 326 Insulating film 341 Oxide semiconductor layer 342 Oxide semiconductor layer 343a Conductive layer 343b Conductive layer 343c Conductive layer 344 Insulating film 345 Conductive layer 346 Insulating film 351 Insulating film 352 Conductive layer 353 Conductive layer 00 transistor 401 resistor 402 transistor 403 transistor 404 resistor 405 resistor 406 resistor 410 conductive layer 411 conductive layer 412 insulating layer 414 oxide semiconductor layer 416 oxide semiconductor layer 418 conductive layer 420 conductive layer 422 conductive layer 424 insulating layer 428 Insulating layer 430 conductive layer 432 conductive layer 434 insulating layer 435 conductive layer 438 insulating layer 440 conductive layer 442 conductive layer 444 oxide semiconductor layer 446 insulating layer 448 conductive layer 450 insulating layer 501 OS transistor 502 OS transistor 503 OS transistor 504 OS transistor 505 OS transistor 506 OS transistor 510 substrate 511 insulating layer 512 insulating layer 513 insulating layer 514 insulating layer 515 insulating layer 516a conductor 516b conductor 520 oxide semiconductor layer 521 oxidation Semiconductor layer 522 Oxide semiconductor layer 523 Oxide semiconductor layer 530 Conductive layer 531 Conductive layer 532 Oxide semiconductor layer 541 Conductive layer 542 Conductive layer 551 Layer 552 Layer 560 Conductive layer 1700 Electronic component 1701 Lead 1702 Printed circuit board 1703 Circuit portion 1704 Circuit board 5001 Case 5002 Case 5003 Display unit 5004 Display unit 5005 Microphone 5006 Speaker 5007 Operation key 5008 Stylus 5101 Car body 5102 Wheel 5103 Dashboard 5104 Light 5301 Case 5302 Refrigeration room door 5303 Freezer compartment door 5401 Case 5402 Display unit 5403 Keyboard 5404 Pointing device 5601 Case 5602 Case 5603 Display unit 5604 Display unit 5605 Connection unit 5606 Operation key 5801 Case 5802 Case 803 display unit 5804 operation key 5805 lens 5806 connection section

Claims (9)

Internal circuitry,
Input and output terminals;
A signal line;
A power line;
A resistance section;
A first transistor;
A control signal generation circuit,
The internal circuit is electrically connected to the input / output terminal via the signal line,
A first terminal of the first transistor is electrically connected to the power line;
A second terminal of the first transistor is electrically connected to a first terminal of the resistor;
A second terminal of the resistor portion is electrically connected to the signal line;
The control signal generation circuit is electrically connected to a gate of the first transistor;
The resistor section and the first transistor each include an oxide semiconductor. Internal circuitry,
Input and output terminals;
A signal line;
A power line;
A resistance section;
A first transistor;
A control signal generation circuit,
The internal circuit is electrically connected to the input / output terminal via the signal line,
A first terminal of the first transistor is electrically connected to a second terminal of the resistor;
A second terminal of the first transistor is electrically connected to the signal line;
A first terminal of the resistor is electrically connected to the power line;
The control signal generation circuit is electrically connected to a gate of the first transistor;
The resistance portion and the first transistor are semiconductor devices each including an oxide semiconductor. Internal circuitry,
Input and output terminals;
A signal line;
A power line;
A first transistor;
A control signal generation circuit,
The internal circuit is electrically connected to the input / output terminal via the signal line,
A first terminal of the first transistor is electrically connected to the power line;
A second terminal of the first transistor is electrically connected to the signal line;
The control signal generation circuit is electrically connected to a gate of the first transistor;
The first transistor is a semiconductor device including an oxide semiconductor. A semiconductor device according to any one of claims 1 to 3 and a second transistor,
The control signal generation circuit is electrically connected to a first terminal of the second transistor;
A second terminal of the second transistor is electrically connected to a gate of the first transistor;
The second transistor is a semiconductor device including an oxide semiconductor. A semiconductor device according to claim 4 and a capacitive element,
The capacitor element is a semiconductor device electrically connected to a second terminal of the second transistor and a gate of the first transistor. In claim 4,
The semiconductor device, wherein the control signal generation circuit is electrically connected to a gate of the second transistor. A semiconductor device according to any one of claims 1 to 3,
And a printed circuit board. A semiconductor device according to any one of claims 1 to 3,
An electronic device having a display portion, a microphone, a speaker, or operation keys. A circuit board according to claim 7;
An electronic device having a display portion, a microphone, a speaker, or operation keys.

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