JPWO2015045272A1 - Intra prediction circuit - Google Patents

Abstract

The intra prediction circuit includes a first prediction pixel calculation unit 12A, a first prediction error calculation unit 13A, and a first reference pixel that supplies reference pixels used by the first prediction pixel calculation unit 12A to another adjacent prediction core. A plurality of first prediction cores 10A1 to 10An including a propagation unit 14A are provided, and reference pixels used by the second prediction pixel calculation unit 12B, the second prediction error calculation unit 13B, and the second prediction pixel calculation unit 12B are adjacent to each other. Second prediction cores 10B1 to 10Bn including the second reference pixel propagation unit 14B supplied to the other prediction cores corresponding to the predetermined number of first prediction cores among the plurality of first prediction cores 10A1 to 10An. Is provided.

Description

  The present invention relates to an intra prediction circuit that performs intra prediction without increasing the circuit scale.

  Non-Patent Document 1 describes HEVC (High Efficiency Video Coding), which is a video encoding system based on the ITU-T recommendation H.265 standard.

  In HEVC, each frame of a digitized video is divided into coding tree units (CTUs), and each CTU is coded in raster scan order. Each CTU has a quad-tree structure and is encoded by being divided into coding units (CU: Coding Unit). Each CU is predicted by being divided into prediction units (PUs). Further, the prediction error of each CU is divided into transform units (TU: Transform Unit) in a quad-tree structure, and is subjected to frequency conversion.

  The CU is predictively encoded by intra prediction or interframe prediction. Hereinafter, intra prediction will be described.

  Intra prediction is prediction in which a prediction image is generated from a reference image of an encoding target frame. In Non-Patent Document 1, 33 types of angle intra prediction shown in FIG. 14 are defined. In the angle intra prediction, reference pixels around the encoding target block are extrapolated in any of the 33 types of directions shown in FIG. 14 to generate an intra prediction signal (predicted pixel). In Non-Patent Document 1, in addition to 33 types of angular intra prediction, DC intra prediction that averages reference pixels around the encoding target block and Planar intra prediction that linearly interpolates reference pixels around the encoding target block are defined. Has been.

  In FIG. 14, each rectangle in the uppermost row and each rectangle in the leftmost column indicate a reference pixel. Numbers in the rectangle indicate coordinates. The arrow indicates the prediction direction. A number attached in the vicinity of the arrow indicates a prediction mode (hereinafter also referred to as a mode).

  With reference to FIG. 15, the configuration and operation of a general video encoding apparatus that outputs a bitstream using each CU of each frame of a digitized video as an input image will be described.

  FIG. 15 is a block diagram illustrating an example of a general video encoding device. The video encoding apparatus illustrated in FIG. 15 includes a transform unit 301, a quantization unit 302, an entropy coding unit 303, an inverse quantization / inverse transform unit 304, a buffer 305, a prediction unit 306, and an optimal prediction mode determination unit 307. .

  The optimal prediction mode determination unit 307 determines a combination of a prediction mode and a prediction block that minimizes the coding cost for each CTU.

  The prediction unit 306 generates a prediction signal for the input image signal of the CU based on the prediction mode and the prediction block determined by the optimal prediction mode determination unit 307. The prediction signal is generated based on intra prediction or inter prediction.

  Based on the TU quadtree structure determined by the optimal prediction mode determination unit 307, the conversion unit 301 performs frequency conversion on a prediction error image (prediction error signal) obtained by subtracting the prediction signal from the input image signal. The transform unit 301 uses orthogonal transform of 4 × 4, 8 × 8, 16 × 16, or 32 × 32 block size based on frequency transform in transform coding of the prediction error signal. Specifically, DST (Discrete Sine Transform) (integer precision) approximated by integer arithmetic is used for 4 × 4 TU of the luminance component of the intra CU. For other TUs, use DCT (Discrete Cosine Transform) (integer precision) approximated by integer operations corresponding to the block size.

  The quantization unit 302 quantizes the orthogonal transform coefficient supplied from the transform unit 301. Hereinafter, the quantized orthogonal transform coefficient may be referred to as a transform quantization value. The inverse quantization / inverse transform unit 304 inversely quantizes the transform quantization value. Further, the inverse quantization / inverse transform unit 304 inversely transforms the inversely quantized orthogonal transform coefficient. A prediction signal is added to the inversely transformed prediction error image, and the prediction error image is supplied to the buffer 305. The buffer 305 stores the image as a reference image.

ITU-T recommendation H.265 High efficiency video coding, April 2013

  The predicted pixel [x] [y] is calculated by the following equation. In the following equation, r [i] and r [j] indicate reference pixels. i and j indicate the coordinates of the reference pixel. >> indicates a bit shift to the right.

  Predicted pixel [x] [y] = (iFact x r [i] + (32-iFact) x r [j] + 16) >> 5 (1)

  iFact is a coefficient, but a fixed value for each row.

  FIG. 16 is an explanatory diagram illustrating an example of prediction. FIG. 16 shows an example in which the block size is 8 × 8 and the mode 21 (see the thick arrow in FIG. 16). Each number in the prediction block indicates the coordinates of the reference pixel. For example, 1: 2 indicates that r [1] is used as r [i] and r [2] is used as r [j]. FIG. 16 also shows iFact values in each row. Furthermore, the calculation of the prediction pixel corresponding to the column of r [4] in the row of r [-4] and the row of r [-5] is illustrated.

  When performing intra prediction, the prediction unit 306 performs N × N operations when the block size is N × N (N: 4, 8, 16, or 32). An intra prediction circuit corresponding to the value of N is prepared. Therefore, when the prediction unit 306 is realized by a hardware circuit, there is a problem that the circuit scale increases.

  An object of the present invention is to provide an intra prediction circuit that solves the problem that the circuit scale increases.

  The intra prediction circuit according to the present invention includes a first prediction pixel calculation unit that calculates a prediction pixel using a reference pixel set in advance or a reference pixel input from another adjacent prediction core, and a first prediction pixel calculation unit. A first prediction error calculation unit that calculates a prediction error by subtracting the calculated prediction pixel from the input image, and a first reference pixel propagation that supplies a reference pixel used by the first prediction pixel calculation unit to another adjacent prediction core A second prediction for calculating a prediction pixel using a reference pixel set in advance, a reference pixel input from another adjacent prediction core, or a reference pixel sequentially input A pixel calculation unit, a second prediction error calculation unit that calculates a prediction error by subtracting the prediction pixel calculated by the second prediction pixel calculation unit from the input image, and a reference pixel used by the second prediction pixel calculation unit A second prediction core including a second reference pixel propagation unit that supplies to another prediction core that is in contact is provided corresponding to a predetermined number of first prediction cores among the plurality of first prediction cores. And

  According to the present invention, the circuit scale of the intra prediction circuit can be prevented from increasing.

It is explanatory drawing which shows an example of prediction. It is explanatory drawing for demonstrating the symmetry of the reference pixel of a row direction, and the reference pixel of a column direction. It is a conceptual diagram which shows the concept of a structure of an intra prediction circuit. It is explanatory drawing which shows the example of the reference pixel used when producing | generating a prediction pixel. It is explanatory drawing for demonstrating in detail the prediction process of the prediction unit of a prediction block. It is a block diagram which shows the prediction pixel production | generation circuit which performs a prediction pixel production | generation process. It is a block diagram which shows the specific structural example of an intra prediction circuit. It is a block diagram which shows the structural example of the intra prediction circuit containing 8 prediction cores. It is explanatory drawing which shows the relationship between the size of a prediction block (prediction object block), and a reference pixel. It is a block diagram which shows the structural example of the intra prediction circuit containing 32 prediction cores. It is a block diagram which shows the structural example of the intra prediction circuit which can respond | correspond to the prediction block of multiple types of size. It is a block diagram which shows the principal part of the intra prediction circuit by this invention. It is a block diagram which shows the principal part of the other intra prediction circuit by this invention. It is explanatory drawing which shows the example of 33 types of angle intra prediction. It is explanatory drawing which shows the structure of a general video coding apparatus. It is explanatory drawing which shows an example of prediction.

  FIG. 1 is an explanatory diagram illustrating an example of prediction. FIG. 1 is an explanatory diagram showing prediction directions and reference pixels in the case of mode 33. In mode 33, the reference pixels r [-16] to r [0] are not used. In addition, the reference pixels r [-16] to r [-9] are not used in common with the modes 18 to 34 (vertical direction mode having an angle of 45 ° or more with respect to the horizontal line).

  Similarly, the reference pixels r [9] to r [16] are not used in common with modes 2 to 17 (horizontal mode having an angle of 45 ° or less with respect to the horizontal line).

  FIG. 1 illustrates a case where the block size is 8 × 8. Hereinafter, the case where the block size is 8 × 8 will be described as an example.

  FIG. 2 is an explanatory diagram for explaining the symmetry between the reference pixels in the row direction and the reference pixels in the column direction. In FIG. 2, the hatched portion indicates a reference pixel. As described above, in the modes 2 to 17, the reference pixels r [9] to r [16] are not used (see FIG. 2A). In the modes 18 to 34, the reference pixels r [-16] to r [-9] are not used (see FIG. 2B). That is, the modes 18 to 34 and the modes 2 to 17 have symmetry as shown in FIG. Note that FIG. 2 also shows the angle of each mode.

  In the present invention, the circuit scale of the intra prediction circuit is reduced by paying attention to such symmetry. FIG. 3 is a conceptual diagram illustrating the concept of the configuration of the intra prediction circuit.

  As shown in FIG. 3, the intra prediction circuit includes an intra prediction unit 1 that performs intra prediction, a distributor 2, a transposition circuit 3, a transposition circuit 4, and a selector 5.

  The intra prediction circuit is applicable to the video encoding circuit shown in FIG. When applied to the video encoding circuit shown in FIG. 15, it is applied as a circuit that performs angle intra prediction in the prediction unit 306.

  The distributor 2 inputs and holds the reference pixel. The distributor 2 supplies the reference pixel to the transposing circuit 3 when the prediction mode is any of modes 2 to 17. When the prediction mode is any of modes 18 to 34, the distributor 2 supplies the input reference pixels to the intra prediction unit 1. The transposition circuit 3 transposes the array of reference pixels and supplies the reference pixels after the transposition to the intra prediction unit 1.

  Note that transposition means exchanging rows and columns.

  The intra prediction unit 1 performs intra prediction and outputs a prediction pixel. At this time, the intra prediction unit 1 outputs the prediction pixel to the transposition circuit 4 when the prediction mode is any of modes 2 to 17. When the prediction mode is any of modes 18 to 34, the prediction pixel is output to the selector 5. The transposition circuit 4 transposes the array of prediction pixels and supplies the reference pixel after the transposition to the intra prediction unit 1.

  The selector 5 outputs the prediction pixel from the transposition circuit 4 or the prediction pixel from the intra prediction unit 1 as a prediction block. The intra prediction unit 1 outputs a prediction pixel in units of rows in the prediction block. Therefore, the selector 5 temporarily stores the prediction pixel from the transposition circuit 4 or the prediction pixel from the intra prediction unit 1, and outputs the prediction pixel constituting the prediction block when the input of the prediction pixel for one block is completed. .

  Note that since the reference pixel array is transposed when the prediction mode is any one of modes 2 to 17, the intra prediction unit 1 performs mode 18 when the prediction mode is any one of modes 2 to 17. ~ 34 can be regarded as any one of the prediction processes. That is, the intra prediction unit 1 only needs to execute the prediction process in the vertical direction mode. That is, the intra prediction unit 1 includes reference pixels adjacent to the upper side of the prediction block (reference pixels r [1] to r [8]) and reference pixels adjacent to the left side (reference pixels r [-8] to r [0]. ) And the reference pixels located on the upper right side (reference pixels r [9] to r [16]) are used, and only the prediction process in the vertical mode is executed.

  FIG. 4 is an explanatory diagram illustrating an example of reference pixels used when generating predicted pixels. FIG. 4 illustrates a case where the predicted block size is 8 × 8. FIG. 4A illustrates the case of mode 21, and FIG. 4B illustrates the case of mode 33.

  In the present embodiment, the intra prediction unit 1 executes the prediction process in units of rows of the prediction block. As shown in FIG. 4, when attention is paid to a certain row (excluding the uppermost row), the reference pixels used in the upper row are used in any of the left, the same column, and the right in the lower row. That is, it is referred to in any of the lower left, the lower right, and the lower right (except for the case of the leftmost column and the rightmost column).

  Therefore, as can be seen from the example illustrated in FIG. 4, when the prediction process is executed in units of rows of the prediction block, after the prediction process is performed for a certain row, when the prediction process for the next row is executed, A reference pixel used in any of left, same column, and right in a row can be used.

  FIG. 5 is an explanatory diagram for explaining the prediction processing (calculation processing) in units of rows of the prediction block in more detail. Note that FIG. 5 also includes a description of “iFact” that is a coefficient for prediction processing and a description of “control” for propagation of reference pixels. Further, the propagation of the reference pixel specifically means that the value of the reference pixel is output.

  5 is a processing example in the case where the prediction process is executed with respect to the prediction block of 3 rows and 8 columns shown in the upper right in FIG. In FIG. 5, the column of the prediction pixel generation process # 2 surrounded by a rectangle corresponds to the second column from the left in the prediction block of 3 rows and 8 columns. A solid arrow indicates that the reference pixel is actually propagated. The broken arrow indicates that the reference pixel does not propagate in the example shown in the upper right in FIG. 5, but the reference pixel may propagate in another example.

  As shown in FIG. 5, the intra prediction unit 1 has eight processing functions in order to process eight elements included in one row at a time. These functions are assumed to be prediction pixel generation processing # 1 to prediction pixel generation processing # 8.

  For the first row, when the prediction pixel generation process # 1 to the prediction pixel generation process # 8 execute the prediction process, the reference pixels used in each of the prediction pixel generation process # 1 to the prediction pixel generation process # 8 are Control is performed so as to be propagated to the prediction pixel generation process # 1 to the prediction pixel generation process # 8 for the second row.

  Furthermore, for the second row, when the prediction pixel generation process # 1 to the prediction pixel generation process # 8 execute the prediction process, the reference used in each prediction pixel generation process # 1 to prediction pixel generation process # 8 The pixels are controlled to be propagated to the prediction pixel generation process # 1 to the prediction pixel generation process # 8 for the third row. However, in this case, the reference pixels used in the prediction pixel generation processing #n (n: 2 to 8) for the second row are used for the prediction pixel generation processing # (n−1) for the third row. Propagated against.

  FIG. 6 is a block diagram illustrating a predicted pixel generation circuit that executes the predicted pixel generation process illustrated in FIG. 5. FIG. 5 shows two prediction pixel generation circuits 111 and 112 and peripheral circuits (specifically, reference pixel registers 122, 123, and 124). Each prediction pixel generation circuit 111 and 112 performs prediction pixel generation processing. In other words, the prediction pixel generation circuit 111 and the prediction pixel generation circuit 112 perform the prediction pixel generation processing adjacent to any two of the prediction pixel generation processing # 1 to prediction pixel generation processing # 8 (adjacent prediction pixel generation in FIG. 5). Processing). Hereinafter, the description will be given focusing on the prediction pixel generation circuit 111, but the configuration and operation of the prediction pixel generation circuit 112 are the same as the configuration and operation of the prediction pixel generation circuit 111.

  After the reference pixels are set in the reference pixel registers 122, 123, and 124, the prediction pixel generation circuit 111 takes in the reference pixels used in the prediction process from two of the reference pixel registers 122, 123, and 124. Then, the predicted pixel generation circuit 111 generates a predicted pixel from the two reference pixels. Note that, as will be described later, the prediction pixel generation circuit may fetch a reference pixel from one reference pixel register.

  Next, specifically, in response to the next rising or falling of the clock signal supplied to the intra prediction circuit, the prediction pixel generation circuit 111 generates a prediction pixel located on the left according to the control signal. It propagates to one or two of the circuit 112, the prediction pixel generation circuit (not shown in FIG. 6) located on the right, and its own circuit (prediction pixel generation circuit 111). That is, the value of the reference pixel is output. Outputting the value of the reference pixel to the own circuit is shown as a “self reference loop” in FIG.

  Note that the propagation of the reference pixel to the prediction pixel generation circuit 112 located on the left corresponds to the propagation from the prediction pixel generation process #n to the prediction pixel generation process # (n−1) in FIG. The self-referencing loop corresponds to propagation to the process immediately below in FIG. The propagation of the reference pixel to the prediction pixel generation circuit located on the right corresponds to the propagation from the prediction pixel generation process #n to the prediction pixel generation process # (n + 1).

  FIG. 7 is a block diagram illustrating a specific configuration example of the prediction pixel generation circuit illustrated in FIG. 6. FIG. 7 also shows peripheral circuits (specifically, reference pixel registers 122, 123, and 124).

  The prediction core 100 illustrated in FIG. 7 corresponds to a specific implementation example of the prediction pixel generation circuit illustrated in FIG. In the prediction core 100, reference pixels from a prediction core (not shown) located on the left are input to the selector 102 via the register 101. Reference pixels from a prediction core (not shown) located on the right are input to the selector 104 via the register 103.

  Further, the reference pixels from the reference pixel registers 122, 123, and 124 are also input to the selectors 102 and 104.

  The outputs of the selectors 102 and 104 are input to the prediction pixel calculation unit 107 and also output to the left and right prediction cores. The reference pixel output from the selector 102 is fed back to the selector 102 via the register 105. The reference pixel output from the selector 104 is fed back to the selector 104 via the register 106. The feedback path corresponds to the self-referencing loop in FIG.

  The predicted pixel calculation unit 107 generates a predicted pixel. The predicted pixel is input to the subtractor 110. The subtractor 110 generates a prediction error signal by subtracting the value of the prediction pixel from the input image value.

  FIG. 8 is a block diagram illustrating a configuration example of a one-dimensional systolic array type intra prediction circuit including eight prediction cores.

  The intra prediction circuit includes reference pixel registers 121 to 128, eight prediction cores 1001 to 1008, a coefficient supply circuit 230, a control circuit 240, and selectors 161 and 162.

  Each of the reference pixel registers 121 to 128 holds one reference pixel. The configuration of the prediction cores 1001 to 1008 is the same as the configuration of the prediction core 100 shown in FIG. The coefficient supply circuit 230 supplies iFact corresponding to the row in which the prediction cores 1001 to 1008 execute the prediction process in the prediction block to the prediction cores 1001 to 1008. The coefficient supply circuit 230 switches the value of iFact when the prediction cores 1001 to 1008 start calculating the prediction pixel of the next row. In the configuration illustrated in FIG. 8, the feedback path of the reference pixel is provided outside the prediction cores 1001 to 1008, but the feedback path is provided inside the prediction cores 1001 to 1008 as illustrated in FIG. 7. It may be done.

  The control circuit 240 provides control signals to the prediction cores 1001 to 1008 and the selectors 161 and 162.

  Among the reference pixels r [-8] to r [0], the reference pixel used by the prediction core 1001 is input to the selector 161 (see FIG. 2B). Among the reference pixels r [1] to r [16], the reference pixel used by the prediction core 1008 is input to the selector 162 (see FIG. 2B). Note that a reference pixel is also input from the selector 161 to the register 101 (see FIG. 7) of the prediction core 1001. A reference pixel is also input from the selector 162 to the register 103 (see FIG. 7) of the prediction core 1008.

  Next, the operation of the intra prediction circuit shown in FIG. 8 will be described.

  Before starting the prediction process in each prediction mode, reference pixels used for generating a prediction pixel in the first row in the prediction block are set in the reference pixel registers 121 to 128. Taking the case of mode 21 shown in FIG. 4A as an example, reference pixels r [1] to r [8] are set in reference pixel registers 121 to 128, respectively.

  First, the prediction cores 1002 to 1007 use the two reference pixels held in the reference pixel registers 121 to 128 to generate the prediction pixels in the first row. Note that the prediction core 1001 inputs one reference pixel from the reference pixel register 121 and inputs one reference pixel from the selector 161. Further, the prediction core 1008 inputs one reference pixel from the reference pixel register 128 and inputs one reference pixel from the selector 162.

  Taking the case of mode 21 shown in FIG. 4A as an example, the prediction core 1001 inputs the reference pixel r [1] from the reference pixel register 121 and inputs the reference pixel r [0] from the selector 161. To do. Taking the case of mode 33 shown in FIG. 4B as an example, the prediction core 1008 inputs the reference pixel r [8] from the reference pixel register 128 and inputs the reference pixel r [9] from the selector 162. To do.

  In the prediction cores 1001 to 1008, the prediction pixel calculation unit 107 generates a prediction pixel from the two reference pixels by the calculation according to the above equation (1). IFact in the equation (1) is supplied from the coefficient supply circuit 230. As an example, the coefficient supply circuit 230 stores in advance each iFact corresponding to a block size that can be used, a prediction mode that can be used, and a row of the prediction block, and a signal that can specify a prediction pixel generation row from the control circuit 240 Output iFact corresponding to the line specified in. The coefficient supply circuit 230 may be configured to calculate and output iFact corresponding to the block size, prediction mode, and row used at that time.

  When the prediction pixel is calculated (generated) by the prediction pixel calculation unit 107, the selectors 102 and 104 output reference pixels used for calculation by the prediction pixel calculation unit 107, and these reference pixels are output to adjacent prediction cores. May also be output, and may be fed back to the prediction pixel calculation unit 107 (see FIG. 7).

  Taking the case where the prediction core 1001 performs the calculation in the mode 21 shown in FIG. 4A as an example, the prediction core 1001 (the process related to the leftmost column is executed for the processing of the second row of the prediction block. )) Is transmitted to the prediction core 1002 (the process relating to the second column from the leftmost) is propagated, and the reference pixel r [0] is fed back in the prediction core 1001. Is done.

  In addition, the reference pixel necessary for the next row processing in a certain prediction core can be obtained from other adjacent prediction cores, and can also be obtained by feedback in the own core. For example, priority is given to obtaining feedback.

  Thereafter, the prediction cores 1001 to 1008 generate prediction pixels for the second and subsequent rows, and perform reference pixel propagation to adjacent prediction cores or reference pixel feedback.

  As described above, in the present embodiment, the intra prediction circuit calculates a prediction pixel using a reference pixel set in advance or a reference pixel input from another adjacent intra prediction circuit, and calculates the prediction pixel. Since the reference pixel used for the calculation is supplied to another adjacent intra prediction circuit or fed back to its own circuit, it is possible to generate prediction pixels collectively in units of prediction blocks without fetching the reference pixels one by one, The circuit scale of the intra prediction circuit can be reduced.

  In addition, the intra prediction circuit includes a transposition circuit that transposes the arrangement of reference pixels in the reference block when performing prediction in the horizontal direction mode, so that the circuit scale of the intra prediction circuit is smaller than when no transposition circuit is provided. Can be reduced.

  The above example is an example when the block size is 8 × 8, but when the block size is N × N (N: 4, 8, 16, or 32), the size of the prediction block (prediction target block) 9 and the reference pixel are generalized as shown in FIG. In FIG. 9, hatched portions indicate reference pixels.

  Since the block size may be not only 8 × 8 but also 4 × 4, 16 × 16, and 32 × 32, in order to support all the block sizes, the intra prediction circuit performs each of those block sizes. It is comprised so that the intra prediction corresponding to can be performed.

  As an example, FIG. 10 is a block diagram showing a configuration example of a one-dimensional systolic array type intra prediction circuit including 32 prediction cores corresponding to a block size of 32 × 32.

  The intra prediction circuit shown in FIG. 10 includes reference pixel registers 121 to 152, 32 prediction cores 1001 to 1032, a coefficient supply circuit 230, a control circuit 240, and selectors 161 and 162.

  Each of the reference pixel registers 121 to 152 holds one reference pixel. The configuration of the prediction cores 1001 to 1032 is the same as the configuration of the prediction core 100 shown in FIG. The coefficient supply circuit 230 supplies iFact corresponding to the row in which the prediction cores 1001 to 1032 execute the prediction process in the prediction block to the prediction cores 1001 to 1032. The coefficient supply circuit 230 switches the value of iFact when the prediction cores 1001 to 1032 start calculating the prediction pixels of the next row. In the configuration illustrated in FIG. 10, the feedback path of the reference pixel is provided outside the prediction cores 1001 to 1032, but the feedback path is provided inside the prediction cores 1001 to 1032 as illustrated in FIG. 7. It may be done.

  The control circuit 240 gives control signals to the prediction cores 1001 to 1032 and the selectors 161 and 162.

  A reference pixel used by the prediction core 1001 among the reference pixels r [−32] to r [0] is input to the selector 161 (see FIG. 9). Of the reference pixels r [1] to r [64], the reference pixel used by the prediction core 1032 is input to the selector 162 (see FIG. 9). Note that a reference pixel is also input from the selector 161 to the register 101 (see FIG. 7) of the prediction core 1001. A reference pixel is also input from the selector 162 to the register 103 (see FIG. 7) of the prediction core 1032.

  The intra prediction circuit shown in FIG. 10 can generate prediction pixels in a batch for each row of the prediction block, similarly to the intra prediction circuit shown in FIG.

  As described above, the leftmost prediction core 1001 and the rightmost prediction core 1032 are different from the configurations of the intermediate prediction cores 1002 to 1031. This is because the prediction cores 1001 and 1032 also receive the reference pixels from the selectors 161 and 162.

  The intra prediction circuit corresponds to a circuit corresponding to a block size of 4 × 4, a circuit corresponding to a block size of 8 × 8, a circuit corresponding to a block size of 16 × 16, and a block size of 32 × 32. Must be configured to include circuitry.

  However, the circuit scale of the intra prediction circuit configured as such is large.

  Therefore, as will be described below, an intra prediction circuit that can deal with a plurality of types of prediction blocks and that can execute parallel processing on a small size prediction block among the plurality of types is proposed.

  FIG. 11 is a block diagram illustrating a configuration example of an intra prediction circuit that can support prediction blocks of a plurality of types of sizes.

  The intra prediction circuit illustrated in FIG. 11 includes a register 1051, an end core 1041, prediction cores 1002 and 1003, and a switch 1061. Also included is an end core 1042 connected to the register 1052 and the switch 1061. Furthermore, a prediction core 1004 connected to the switch 1061 and a prediction core 1005 connected to the switch 1062 are included. In addition, an end core 1043 connected to the register 1053 and the switch 1062 is included.

  The intra prediction circuit includes a prediction core 1006 connected to the switch 1062 and a prediction core 1007 connected to the switch 1063. Furthermore, an end core 1044 connected to the register 1054 and the switch 1063 is included. Moreover, the prediction core 1009 connected to the switch 1063 and the prediction core 1010 connected to the switch 1064 are included. Also included is an end core 1045 connected to the register 1055 and the switch 1064.

  The control circuit 240 gives a control signal to the switchers 1061 to 1064. Note that the control circuit 240 also gives control signals to the end cores 1041 to 1045 and the prediction cores 1002 to 1010, but connection for that purpose is omitted in FIG. Reference pixel registers each holding one reference pixel are also provided, but their description is also omitted in FIG. Further, a coefficient supply circuit that supplies iFact corresponding to the row on which the prediction process is executed to the prediction cores 1002 to 1010 and the end cores 1041 to 1045 is also provided, but is not shown in FIG.

  In the configuration shown in FIG. 11, when the prediction block size is 4 × 4, intra prediction is executed by the end core 1041, the prediction core 1002, the prediction core 1003, and the end core 1042 (“4 × 4 in FIG. 11). (See Process # 1). When the prediction block size is 4 × 4, intra prediction can also be performed by the end core 1043, the prediction core 1006, the prediction core 1007, and the end core 1044 (see “4 × 4 processing # 2” in FIG. 11). ).

  Further, when the prediction block size is 8 × 8, intra prediction is executed by the end core 1041, the prediction cores 1002, 1003, 1004, 1005, 1006, 1007, and the end core 1044 (“8” in FIG. 11). X8 treatment ").

  The configurations of the end cores 1041 to 1045 and the prediction cores 1002 to 1010 are the same as the configuration of the prediction core 100 illustrated in FIG.

  In contrast to the configuration shown in FIG. 8, the end cores 1041 and 1043 operate in the same manner as the prediction core 1001. That is, reference pixels are also input from the registers 1051 and 1053 to the register 101 (see FIG. 7) of the end cores 1041 and 1043. Further, the end cores 1042, 1044 and 1045 operate in the same manner as the prediction core 1008. That is, reference pixels are also input from the registers 1052, 1054, and 1055 to the register 103 (see FIG. 7) of the end cores 1042, 1044, and 1045.

  When the predicted block size is 4 × 4 and the 4 × 4 process # 1 is used, the control circuit 240 controls the switch 1061 so that the predicted core 1003 and the end core 1042 are connected. give. As a result, a configuration for intra prediction of 4 × 4 process # 1 is formed.

  When the predicted block size is 4 × 4 and the 4 × 4 processing # 2 is used, the control circuit 240 controls the switch 1062 so that the end core 1043 and the predicted core 1006 are connected. And a control signal is supplied to the switch 1063 so as to connect the prediction core 1007 and the end core 1044. As a result, a configuration for intra prediction of 4 × 4 processing # 2 is formed.

  When the prediction block size is 8 × 8, the control circuit 240 gives a control signal to the switch 1061 so as to connect the prediction core 1003 and the prediction core 1004. Further, the control circuit 240 gives a control signal to the switch 1062 so as to connect the prediction core 1005 and the prediction core 1006. Further, the control circuit 240 gives a control signal to the switch 1063 so as to connect the prediction core 1007 and the end core 1044. As a result, a configuration for intra prediction of 8 × 8 processing is formed.

  When the prediction block size is 8 × 8, intra prediction may be executed by the end core 1041, the prediction cores 1002, 1003, 1006, 1007, 1009, and 1010, and the end core 1045.

  In that case, the control circuit 240 gives a control signal to the switchers 1061 and 1062 so as to connect the prediction core 1003 and the prediction core 1006.

  In addition, the control circuit 240 gives a control signal to the switch 1063 so as to connect the prediction core 1007 and the prediction core 1009. Further, the control circuit 240 gives a control signal to the switch 1064 so as to connect the prediction core 1010 and the end core 1045. As a result, a configuration for intra prediction of 8 × 8 processing is formed.

  In this case, the prediction cores 1004 and 1005 are not used, and a route for directly connecting the switch 1061 and the switch 1062 is necessary, but the route is omitted in FIG. Moreover, although the switch and path | route for switching the connection of the prediction core 1010 and the end core 1044 are newly required, the switch and path | route are abbreviate | omitting description in FIG.

  The configuration for intra prediction of 8 × 8 processing is substantially the same as the configuration shown in FIG. Therefore, prediction pixels are generated in a batch for each row of the prediction block.

  In the configuration for intra prediction of 4 × 4 processing # 1 or the configuration for intra prediction of 4 × 4 processing # 2, as in the configuration shown in FIG. Thus, a prediction pixel is generated. However, unlike the configuration shown in FIG. 8, the number of rows and the number of columns are four.

  The intra prediction circuit shown in FIG. 11 can cope with prediction blocks of a plurality of types (specifically, 8 × 8 and 4 × 4), and a small size (specifically, a plurality of types). 4 × 4) prediction blocks can be executed in parallel. This is because there is no overlapping element between the configuration for intra prediction of 4 × 4 processing # 1 and the configuration for intra prediction of 4 × 4 processing # 2.

  Therefore, when the configuration illustrated in FIG. 11 is adopted, the circuit scale of the intra prediction circuit can be prevented from increasing, and the processing speed of intra prediction can be increased by parallel processing.

  FIG. 11 illustrates an example in which the processable prediction block size is 8 × 8 (the maximum size of the prediction block in this case), and at least 6 prediction cores 1002 to 1010 correspond to 8 × 8. (= 8-2 (number of end cores): Specifically, prediction cores 1002 to 1007) are provided, and the size of the prediction block that can be processed is smaller than the maximum size of the prediction block (in this case, 4). 2 end cores are provided so as to be able to correspond to 2 prediction cores, which is a small number, but when the processable prediction block size is 16 × 16, at least 14 prediction cores are provided. If the size of a prediction block that can be processed smaller than the maximum size of the prediction block is 8, two end cores are provided so as to correspond to six prediction cores.

  Further, in such a configuration, a configuration in which prediction processing is performed on a 4 × 4 prediction block in a configuration in which prediction processing is performed on an 8 × 8 prediction block (2 end cores + 6 prediction cores) is included. Can be made. In other words, as illustrated in FIG. 11, the configuration for intra prediction of “8 × 8 processing” can include the configuration for intra prediction of “4 × 4 processing”.

  Further, when the processable prediction block size is 32 × 32, if at least 30 prediction cores are provided and the size of the processable prediction block smaller than the maximum size of the prediction block is 16, 14 Two end cores are provided corresponding to one prediction core.

FIG. 12 is a block diagram showing a main part of the intra prediction circuit according to the present invention. As illustrated in FIG. 12, the intra prediction circuit includes a first prediction pixel calculation unit 12 </ b> A that calculates a prediction pixel using a reference pixel set in advance or a reference pixel input from another adjacent prediction core (for example, 7) and a first prediction error calculation unit 13A that calculates a prediction error by subtracting the prediction pixel calculated by the first prediction pixel calculation unit 12A from the input image (for example, the prediction pixel calculation unit 107 shown in FIG. 7). , And a first reference pixel propagation unit 14A that supplies a reference pixel used by the first prediction pixel calculation unit 12A to another adjacent prediction core (for example, FIG. 7). And a plurality of first prediction cores 10A _{1 to} 10A _n (for example, realized by the prediction cores 1002 to 1010 shown in FIG. 11). A second prediction pixel calculation unit 12B (for example, the prediction shown in FIG. 7) that calculates a prediction pixel using a reference pixel that has been set first, a reference pixel that is input from another adjacent prediction core, or a reference pixel that is sequentially input. And a second prediction error calculation unit 13B that calculates a prediction error by subtracting the prediction pixel calculated by the second prediction pixel calculation unit 12B from the input image (for example, as shown in FIG. 7). And a second reference pixel propagation unit 14B (for example, the selector 102 shown in FIG. 7) that supplies the reference pixel used by the second prediction pixel calculation unit 12B to another adjacent prediction core. is achieved at 104.) 1 second prediction core _10B and a ~10B _m (e.g.,. realized at the end core 1041-1045 shown in FIG. 11) is a plurality of first prediction core _10A 1 10 a _n Are provided corresponding to a predetermined number of first prediction cores.

  The first prediction pixel calculation unit 12A and the second prediction pixel calculation unit 12B have the same function except that the input source of the reference pixel is different. The first prediction error calculation unit 13A and the second prediction error calculation unit 13B have the same function. The first reference pixel propagation unit 14A and the second reference pixel propagation unit 14B have the same function.

Further, in the above embodiment, the first prediction cores 10A _{1 to} 10A _n are, for example, the number (for example, 6 (= 8) corresponding to the maximum size of the prediction block that can be processed (for example, 8: see FIG. 10)) -2)) provided, and two second prediction cores are allocated to the number of first prediction cores that are smaller than the size of the prediction block that can be processed smaller than the maximum size of the prediction block (for example, 4). An intra prediction circuit provided as described above is disclosed.

  Moreover, in said embodiment, the switch part which connects one 1st prediction core to another 1st prediction core or a 2nd prediction core (For example, it implement | achieves with the switchers 1061-1064 shown in FIG. 11). An intra prediction circuit is disclosed.

  Moreover, in said embodiment, an intra prediction circuit provided with the control part (for example, implement | achieved by the control circuit 240 shown in FIG. 11) which gives a switching signal to a switching part according to the size of the prediction block of prediction object is disclosed. Has been.

  FIG. 13 is a block diagram showing a main part of another intra prediction circuit according to the present invention. As shown in FIG. 13, the intra prediction circuit includes transposition circuits 20A and 20B in addition to the first prediction core 10A and the second prediction core 10B. Transposition circuits 20A and 20B (corresponding to transposition circuit 3 shown in FIG. 3) transpose the arrangement of reference pixels in the reference block.

  While the present invention has been described with reference to the embodiments and examples, the present invention is not limited to the above embodiments and examples. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention.

  This application claims the priority on the basis of the JP Patent application 2013-203278 for which it applied on September 30, 2013, and takes in those the indications of all here.

1 intra prediction unit 2 distributor 3 transposition circuit 4 transposition circuit 5 selector 10A ₁ 10 A _n first predicted core 10B ₁ ~10B _m first prediction pixel calculation unit 12B second prediction cores 12A second prediction pixel calculation unit 13A first 1 prediction error calculation unit 13B second prediction error calculation unit 14A first reference pixel propagation unit 14B second reference pixel propagation unit 20A, 20B transpose circuit 100 prediction core 101, 103, 105, 106 register 102, 104 selector 107 prediction pixel Calculation unit 110 Subtractor 111, 112 Predicted pixel generation circuit 121-152 Reference pixel register 161, 162 Selector 230 Coefficient supply circuit 240 Control circuit 301 Conversion unit 302 Quantization unit 303 Entropy encoding unit 304 Inverse quantization / inverse conversion unit 305 Buffer 306 Prediction unit 307 Optimal prediction mode determination unit 001-1032 prediction core

Claims (7)

An intra prediction circuit that performs angle intra prediction,
A first prediction pixel calculation unit that calculates a prediction pixel using a reference pixel set in advance or a reference pixel input from another adjacent prediction core, and a prediction pixel calculated by the first prediction pixel calculation unit as an input image A first prediction error calculation unit that calculates a prediction error by subtracting from the first prediction pixel calculation unit, and a first reference pixel propagation unit that supplies a reference pixel used by the first prediction pixel calculation unit to another adjacent prediction core There are multiple prediction cores,
A second prediction pixel calculation unit that calculates a prediction pixel using a reference pixel set in advance, a reference pixel input from another adjacent prediction core, or a reference pixel sequentially input; and the second prediction pixel calculation unit includes: A second prediction error calculation unit that calculates a prediction error by subtracting the calculated prediction pixel from the input image, and a second reference pixel that supplies a reference pixel used by the second prediction pixel calculation unit to another adjacent prediction core An intra prediction circuit, wherein a second prediction core including a propagation unit is provided corresponding to a predetermined number of first prediction cores among the plurality of first prediction cores. The number of the first prediction cores is provided according to the maximum size of the prediction block that can be processed,
2. The second prediction core is provided so that two second prediction cores are allocated to a number of the first prediction cores that are two smaller than a processable prediction block size smaller than the maximum size of the prediction block. The intra prediction circuit described. The intra prediction circuit according to claim 1, further comprising a switching unit that connects one first prediction core to the other first prediction core or the second prediction core. The intra prediction circuit according to claim 3, further comprising a control unit that provides a switching signal to the switching unit according to a size of a prediction block to be predicted. The first reference pixel propagation unit includes a circuit that feeds back a reference pixel to the first prediction error calculation unit,
The intra prediction circuit according to any one of claims 1 to 4, wherein the second reference pixel propagation unit includes a circuit that feeds back a reference pixel to the second prediction error calculation unit. A coefficient supply circuit that supplies a coefficient in calculation corresponding to a row when calculating prediction pixels for one row to each of the plurality of first prediction cores and the plurality of second prediction cores. The intra prediction circuit according to any one of claims 1 to 5. Using reference pixels adjacent to the upper and left sides of the prediction block and a reference pixel located on the upper right side,
The intra prediction circuit according to any one of claims 1 to 6, further comprising a transposition circuit that transposes an array of reference pixels in the reference block when performing prediction in the horizontal mode.

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