JPWO2013132644A1 - Semiconductor module - Google Patents

Semiconductor module Download PDF

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JPWO2013132644A1
JPWO2013132644A1 JP2014503390A JP2014503390A JPWO2013132644A1 JP WO2013132644 A1 JPWO2013132644 A1 JP WO2013132644A1 JP 2014503390 A JP2014503390 A JP 2014503390A JP 2014503390 A JP2014503390 A JP 2014503390A JP WO2013132644 A1 JPWO2013132644 A1 JP WO2013132644A1
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plate
insulating member
chip
heat sink
facing
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憲司 羽鳥
憲司 羽鳥
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Mitsubishi Electric Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1305Bipolar Junction Transistor [BJT]
    • H01L2924/13055Insulated gate bipolar transistor [IGBT]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • H01L2924/15155Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
    • H01L2924/15156Side view

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  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

パワー半導体チップ(10a,20b)と、パワー半導体チップ(10a)に比べて消費電力が低い低電力部(90c)とが、導電性を有するヒートシンク(60)の所定面(61)の側に設けられている。パワー半導体チップ(10a,20b)とヒートシンク(60)との間に第1の板状絶縁部材(30ab)が延在している。低電力部(90c)とヒートシンク(60)との間に第2の板状絶縁部材(30c)が延在している。第2の板状絶縁部材(30c)のうちで低電力部(90c)に面する部分(33c)は、第1の板状絶縁部材(30ab)のうちでパワー半導体チップ(10a,20b)に面する部分(33ab)に比べて厚い。The power semiconductor chip (10a, 20b) and the low power portion (90c), which consumes less power than the power semiconductor chip (10a), are provided on the predetermined surface (61) side of the conductive heat sink (60). It has been. A first plate-like insulating member (30ab) extends between the power semiconductor chip (10a, 20b) and the heat sink (60). A second plate-like insulating member (30c) extends between the low power part (90c) and the heat sink (60). Of the second plate-like insulating member (30c), the portion (33c) facing the low power portion (90c) is connected to the power semiconductor chip (10a, 20b) of the first plate-like insulating member (30ab). It is thicker than the facing part (33ab).

Description

本発明は半導体モジュールに関する。   The present invention relates to a semiconductor module.

従来のパワー半導体モジュールでは、パワー半導体チップと絶縁基板とヒートシンクとが積層されている。具体的には、絶縁基板は両主面に金属層を有した板状絶縁部材で構成されており、一方の金属層にパワー半導体チップが接合され、他方の金属層にヒートシンクが接合されている。上記一方の金属層は、パワー半導体チップが接合される部分の他に配線を提供する部分も有した所定パターンに形成されている。   In a conventional power semiconductor module, a power semiconductor chip, an insulating substrate, and a heat sink are stacked. Specifically, the insulating substrate is composed of plate-like insulating members having metal layers on both main surfaces, a power semiconductor chip is bonded to one metal layer, and a heat sink is bonded to the other metal layer. . The one metal layer is formed in a predetermined pattern having a portion for providing wiring in addition to the portion to which the power semiconductor chip is bonded.

上記ヒートシンクは例えば銅等の金属で構成される。このため、ヒートシンクは、板状絶縁部材を介してパワー半導体チップと容量性の電気的結合を形成すると共に、板状絶縁部材を介して上記配線(上記のように板状絶縁部材上の一方の金属層によって提供される)とも容量性の電気的結合を形成する。したがって、パワー半導体チップと配線とが、板状絶縁部材およびヒートシンクを介して、容量的に結合することになる。   The heat sink is made of a metal such as copper. For this reason, the heat sink forms a capacitive electrical coupling with the power semiconductor chip via the plate-like insulating member, and the wiring (one of the plates on the plate-like insulating member as described above) via the plate-like insulating member. It also forms a capacitive electrical coupling (provided by the metal layer). Therefore, the power semiconductor chip and the wiring are capacitively coupled via the plate-like insulating member and the heat sink.

そのような容量性結合は、例えば、パワー半導体チップのスイッチングに伴うノイズを配線へ伝える経路になる場合がある。配線に伝わったノイズが当該配線からパワー半導体チップに印加されると、パワー半導体モジュールが誤作動を起こす懸念がある。   Such capacitive coupling may be, for example, a path for transmitting noise accompanying the switching of the power semiconductor chip to the wiring. When noise transmitted to the wiring is applied from the wiring to the power semiconductor chip, there is a concern that the power semiconductor module may malfunction.

パワー半導体チップと配線との間の上記容量性結合は、板状絶縁部材を厚くすれば、低減可能である。すなわち、パワー半導体チップと配線との間の絶縁性を向上可能である。しかし、板状絶縁部材を厚くすると熱抵抗が増加し、そのためパワー半導体チップについての放熱性が低下してしまう。   The capacitive coupling between the power semiconductor chip and the wiring can be reduced by increasing the thickness of the plate-like insulating member. That is, the insulation between the power semiconductor chip and the wiring can be improved. However, when the plate-like insulating member is thickened, the thermal resistance increases, so that the heat dissipation of the power semiconductor chip is lowered.

なお、板状絶縁部材およびヒートシンクを介した容量性結合は複数のパワー半導体チップ間においても形成される場合があり、その場合も上記と同様の問題が生じうる。   Note that the capacitive coupling through the plate-like insulating member and the heat sink may be formed between a plurality of power semiconductor chips, and in this case, the same problem as described above may occur.

かかる点に鑑み、本発明は絶縁性と放熱性の両方を確保可能な技術を提供することを目的とする。   In view of this point, an object of the present invention is to provide a technique capable of ensuring both insulation and heat dissipation.

本発明の一態様に係る半導体モジュールは、導電性を有するヒートシンクと、前記ヒートシンクの所定面の側に設けられたパワー半導体チップと、前記ヒートシンクの前記所定面の側に設けられており前記パワー半導体チップに比べて消費電力が低い低電力部と、前記パワー半導体チップと前記ヒートシンクとの間に延在した第1の板状絶縁部材と、前記低電力部と前記ヒートシンクとの間に延在した第2の板状絶縁部材とを含む。前記第2の板状絶縁部材のうちで前記低電力部に面する部分は、前記第1の板状絶縁部材のうちで前記パワー半導体チップに面する部分に比べて厚い。   A semiconductor module according to an aspect of the present invention includes a conductive heat sink, a power semiconductor chip provided on a predetermined surface side of the heat sink, and the power semiconductor provided on the predetermined surface side of the heat sink. A low power portion having lower power consumption than the chip, a first plate-like insulating member extending between the power semiconductor chip and the heat sink, and extending between the low power portion and the heat sink. And a second plate-like insulating member. The portion of the second plate-like insulating member that faces the low power portion is thicker than the portion of the first plate-like insulating member that faces the power semiconductor chip.

上記一態様によれば、第1の板状絶縁部材によって、パワー半導体チップ下の熱抵抗を低減でき、放熱性を確保できる。それと共に、第2の板状絶縁部材によって、第1および第2の板状絶縁部材ならびにヒートシンクを介したパワー半導体チップと低電力部との間の容量性結合を低減でき、パワー半導体チップと低電力部との間の絶縁性を確保できる。   According to the above aspect, the first plate-like insulating member can reduce the thermal resistance under the power semiconductor chip and ensure heat dissipation. At the same time, the second plate-like insulating member can reduce the capacitive coupling between the power semiconductor chip and the low power part via the first and second plate-like insulating members and the heat sink, and the power semiconductor chip and the low Insulation with the power section can be ensured.

本発明の目的、特徴、局面、および利点は、以下の詳細な説明と添付図面とによって、より明白となる。   The objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description and the accompanying drawings.

実施の形態1に係る半導体モジュールを例示する断面図である。2 is a cross-sectional view illustrating the semiconductor module according to the first embodiment. FIG. 実施の形態1に係る半導体モジュールを例示する上面図である。4 is a top view illustrating the semiconductor module according to the first embodiment; FIG. 実施の形態2に係る半導体モジュールを例示する断面図である。FIG. 4 is a cross-sectional view illustrating a semiconductor module according to a second embodiment. 実施の形態2の変形例に係る半導体モジュールを例示する断面図である。FIG. 10 is a cross-sectional view illustrating a semiconductor module according to a modification of the second embodiment. 実施の形態1の変形例に係る半導体モジュールを例示する断面図である。FIG. 10 is a cross-sectional view illustrating a semiconductor module according to a modification of the first embodiment. 実施の形態3に係る半導体モジュールを例示する断面図である。FIG. 6 is a cross-sectional view illustrating a semiconductor module according to a third embodiment. 実施の形態4に係る半導体モジュールを例示する断面図である。FIG. 6 is a cross-sectional view illustrating a semiconductor module according to a fourth embodiment. 実施の形態5に係る半導体モジュールを例示する断面図である。FIG. 10 is a cross-sectional view illustrating a semiconductor module according to a fifth embodiment. 実施の形態6に係る半導体モジュールを例示する断面図である。FIG. 10 is a cross-sectional view illustrating a semiconductor module according to a sixth embodiment. 実施の形態7に係る半導体モジュールを例示する断面図である。FIG. 10 is a cross-sectional view illustrating a semiconductor module according to a seventh embodiment. 実施の形態8に係る半導体モジュールを例示する断面図である。FIG. 10 is a cross-sectional view illustrating a semiconductor module according to an eighth embodiment.

<実施の形態1>
図1に、実施の形態1に係るパワー半導体モジュール(以下、半導体モジュールとも称する)1の断面図を例示する。図1の例によれば、半導体モジュール1は、パワー半導体チップ(以下、半導体チップとも称する)10a,20bと、板状絶縁部材30ab,30cと、金属層40ab,50ab,40c,50cと、ヒートシンク60と、接合部材72a,72b,74ab,74cと、接続部材82,84,86とを含んでいる。
<Embodiment 1>
FIG. 1 illustrates a cross-sectional view of a power semiconductor module (hereinafter also referred to as a semiconductor module) 1 according to the first embodiment. 1, the semiconductor module 1 includes power semiconductor chips (hereinafter also referred to as semiconductor chips) 10a and 20b, plate-like insulating members 30ab and 30c, metal layers 40ab, 50ab, 40c and 50c, a heat sink. 60, joining members 72a, 72b, 74ab, 74c, and connecting members 82, 84, 86 are included.

パワー半導体チップ10aは互いに表裏の関係にある(換言すればチップ内部を介して対向する)チップ主面11,12を有し、同様にパワー半導体チップ20bもチップ主面21,22を有している。図1の図示に合わせて、チップ主面11,21をチップ上面(または上面)11,21とも称し、チップ主面12,22をチップ下面(または下面)12,22とも称する。半導体チップ10a,20bの材料は例えば珪素(Si)であるが、半導体チップ10a,20bの一方または両方が他の材料、例えば炭化珪素(SiC)、窒化ガリウム(GaN)等のいわゆるワイドバンドギャップ材料で構成されてもよい。   The power semiconductor chip 10a has chip main surfaces 11 and 12 that are opposite to each other (in other words, face each other through the inside of the chip). Similarly, the power semiconductor chip 20b also has chip main surfaces 21 and 22. Yes. 1, the chip main surfaces 11 and 21 are also referred to as chip upper surfaces (or upper surfaces) 11 and 21, and the chip main surfaces 12 and 22 are also referred to as chip lower surfaces (or lower surfaces) 12 and 22, respectively. The material of the semiconductor chips 10a and 20b is, for example, silicon (Si), but one or both of the semiconductor chips 10a and 20b are other materials, for example, so-called wide band gap materials such as silicon carbide (SiC) and gallium nitride (GaN). It may be constituted by.

半導体チップ10a,20bには、例えばIGBT(Insulated Gate Bipolar Transistor)、MOSFET(Metal Oxide Semiconductor Field Effect Transistor)、ダイオード等のパワー半導体素子が作り込まれている。半導体チップ10a,20bは同じ種類の素子であってもよいし、異なる種類の素子であってもよい。IGBTの場合、例えば、チップ上面11にIGBTのエミッタ電極およびゲート電極が設けられ、チップ下面12にIGBTのコレクタ電極が設けられる。   For example, power semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors), MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and diodes are built in the semiconductor chips 10a and 20b. The semiconductor chips 10a and 20b may be the same type of elements or different types of elements. In the case of an IGBT, for example, an IGBT emitter electrode and a gate electrode are provided on the chip upper surface 11, and an IGBT collector electrode is provided on the chip lower surface 12.

チップ上面11,21の所定の電極が、接続部材82によって、互いに接続されている。接続部材82は図1の例ではボンディングワイヤであるが、導電性の板材等を用いてもよい。チップ下面12,22は、半田等の接合部材72a,72bによって、板状絶縁部材30ab上に設けられた金属層40abに接合されている。   Predetermined electrodes on the chip upper surfaces 11 and 21 are connected to each other by a connection member 82. The connecting member 82 is a bonding wire in the example of FIG. 1, but a conductive plate material or the like may be used. The chip lower surfaces 12 and 22 are bonded to a metal layer 40ab provided on the plate-like insulating member 30ab by bonding members 72a and 72b such as solder.

板状絶縁部材30abは、互いに表裏の関係にある主面31ab,32abを有している。図1の図示に合わせて、主面31abを上面31abとも称し、主面32abを下面32abとも称する。ここでは主面31ab,32abが平坦面であり平行をなしている場合を例示し、その場合、板状絶縁部材30abの厚さは部材全体に渡って均一である。板状絶縁部材30abは例えばフィラーが充填されたエポキシ樹脂、セラミック等の絶縁性材料で構成されている。   The plate-like insulating member 30ab has main surfaces 31ab and 32ab that are in a relationship of front and back. In conformity with the illustration in FIG. 1, the main surface 31ab is also referred to as an upper surface 31ab, and the main surface 32ab is also referred to as a lower surface 32ab. Here, a case where the main surfaces 31ab and 32ab are flat surfaces and parallel to each other is illustrated, and in this case, the thickness of the plate-like insulating member 30ab is uniform over the entire member. The plate-like insulating member 30ab is made of an insulating material such as an epoxy resin or ceramic filled with a filler, for example.

板状絶縁部材30abの上面31abに金属層40abが接合されており、板状絶縁部材30abの下面32abに金属層50abが接合されている。金属層40ab,50abは例えば銅等で構成されている。金属層40ab,50abは、半田等の接合部材72a,72b,74abによる接合の下地として機能する。また、図1の例では、金属層40abは、チップ下面12,22の電極を互いに接続する配線としても機能する。これらの機能が実現可能であれば、金属以外の材料を採用してもよい。   The metal layer 40ab is joined to the upper surface 31ab of the plate-like insulating member 30ab, and the metal layer 50ab is joined to the lower surface 32ab of the plate-like insulating member 30ab. The metal layers 40ab and 50ab are made of, for example, copper. The metal layers 40ab and 50ab function as a base for joining by joining members 72a, 72b, and 74ab such as solder. In the example of FIG. 1, the metal layer 40ab also functions as a wiring that connects the electrodes of the chip lower surfaces 12 and 22 to each other. If these functions are realizable, materials other than metal may be adopted.

なお、板状絶縁部材30abと金属層40ab,50abとの積層体が、絶縁基板と称される場合もある。   In addition, the laminated body of plate-shaped insulating member 30ab and metal layer 40ab, 50ab may be called an insulated substrate.

板状絶縁部材30cは、互いに表裏の関係にある主面31c,32cを有している。図1の図示に合わせて、主面31cを上面31cとも称し、主面32cを下面32cとも称する。ここでは主面31c,32cが平坦面であり平行をなしている場合を例示し、その場合、板状絶縁部材30cの厚さは部材全体に渡って均一である。板状絶縁部材30cは例えば板状絶縁部材30abと同様の材料で構成されている。   The plate-like insulating member 30c has main surfaces 31c and 32c that are in a front-back relationship. In conformity with the illustration in FIG. 1, the main surface 31c is also referred to as an upper surface 31c, and the main surface 32c is also referred to as a lower surface 32c. Here, a case where the main surfaces 31c and 32c are flat surfaces and are parallel to each other is illustrated, and in this case, the thickness of the plate-like insulating member 30c is uniform over the entire member. The plate-like insulating member 30c is made of the same material as the plate-like insulating member 30ab, for example.

板状絶縁部材30cの上面31cに金属層40cが接合されており、板状絶縁部材30cの下面32cに金属層50cが接合されている。金属層40c,50cは例えば金属層40ab,50abと同じ材料で構成されている。   The metal layer 40c is joined to the upper surface 31c of the plate-like insulating member 30c, and the metal layer 50c is joined to the lower surface 32c of the plate-like insulating member 30c. The metal layers 40c and 50c are made of the same material as the metal layers 40ab and 50ab, for example.

金属層40cは所定の配線パターンに形成されており、このため金属層40cを配線層40c、配線パターン40c等と称してもよい。かかる点に鑑みると、配線層40cは金属以外の導電材料で構成されてもよい。図1の例では、金属層40cによる配線パターンが3つの配線部分41,42,43を有し、配線部分42,43が接続部材84,86によって半導体チップ10aの上面11に接続されている。接続部材84,86は、図1の例ではボンディングワイヤであるが、導電性の板材等を用いてもよい。   The metal layer 40c is formed in a predetermined wiring pattern. Therefore, the metal layer 40c may be referred to as a wiring layer 40c, a wiring pattern 40c, or the like. In view of this point, the wiring layer 40c may be made of a conductive material other than metal. In the example of FIG. 1, the wiring pattern of the metal layer 40 c has three wiring portions 41, 42, and 43, and the wiring portions 42 and 43 are connected to the upper surface 11 of the semiconductor chip 10 a by connection members 84 and 86. The connection members 84 and 86 are bonding wires in the example of FIG. 1, but conductive plate materials or the like may be used.

金属層50cは半田等の接合部材74cによる接合の下地として機能し、かかる機能が実現可能であれば金属以外の材料を採用してもよい。   The metal layer 50c functions as a base for bonding by a bonding member 74c such as solder, and a material other than metal may be adopted as long as such a function can be realized.

なお、板状絶縁部材30cと金属層40c,50cとの積層体が、絶縁基板と称される場合もある。   In addition, the laminated body of the plate-shaped insulating member 30c and the metal layers 40c and 50c may be called an insulating substrate.

ヒートシンク60は、例えば銅等の導電性材料で構成されている。ヒートシンク60は、図1の例では板状をしており、互いに表裏の関係にある主面61,62を有している。図1の図示に合わせて、主面61を上面61とも称し、主面62を下面62とも称する。ここでは主面61,62が平坦面である場合を例示するが、例えば下面62はフィン形状であってもよい。   The heat sink 60 is made of a conductive material such as copper, for example. The heat sink 60 has a plate shape in the example of FIG. 1 and has main surfaces 61 and 62 that are in a relationship of front and back. In conformity with the illustration of FIG. 1, the main surface 61 is also referred to as an upper surface 61, and the main surface 62 is also referred to as a lower surface 62. Here, the case where the main surfaces 61 and 62 are flat surfaces is illustrated, but the lower surface 62 may have a fin shape, for example.

ヒートシンク60の上面61上には、板状絶縁部材30ab,30cが搭載されている。具体的には、板状絶縁部材30abの下面32abに設けられた金属層50abが接合部材74abによってヒートシンク60の上面61に接合されており、板状絶縁部材30cの下面32cに設けられた金属層50cが接合部材74cによってヒートシンク60の上面61に接合されている。接合部材74ab,74cは例えば半田である。これによれば、ヒートシンク60の上面61と板状絶縁部材30ab,30cの下面32ab,32cとが対面している。   On the upper surface 61 of the heat sink 60, plate-like insulating members 30ab and 30c are mounted. Specifically, the metal layer 50ab provided on the lower surface 32ab of the plate-like insulating member 30ab is joined to the upper surface 61 of the heat sink 60 by the joining member 74ab, and the metal layer provided on the lower surface 32c of the plate-like insulating member 30c. 50c is joined to the upper surface 61 of the heat sink 60 by the joining member 74c. The joining members 74ab and 74c are, for example, solder. According to this, the upper surface 61 of the heat sink 60 and the lower surfaces 32ab and 32c of the plate-like insulating members 30ab and 30c face each other.

ヒートシンク60の上面61上の構成は不図示のケース、封止樹脂等の封止部材内に収容される。但し、ヒートシンク60の下面62は当該封止部材から露出される。なお、封止部材から不図示の外部端子が引き出される。   The configuration on the upper surface 61 of the heat sink 60 is accommodated in a sealing member such as a case (not shown) or a sealing resin. However, the lower surface 62 of the heat sink 60 is exposed from the sealing member. An external terminal (not shown) is pulled out from the sealing member.

なお、図1には2つの半導体チップ10a,20bが例示されているが、半導体モジュール1は半導体チップを1個だけ含んでもよいし、あるいは、3個以上の半導体チップを含んでもよい。例えば半導体チップ10aだけが設けられる場合、図1の例から半導体チップ20bと接合部材72bと接続部材82とが省略される。また、図2に例示する上面図では半導体チップ10a,20bの組み合わせが3組図示されている。なお、図2の例では、板状絶縁部材30c上に3つの配線部分42が設けられ、各配線部分42と配線部分41との間にバランス抵抗44が接続されている。   1 illustrates two semiconductor chips 10a and 20b, the semiconductor module 1 may include only one semiconductor chip, or may include three or more semiconductor chips. For example, when only the semiconductor chip 10a is provided, the semiconductor chip 20b, the joining member 72b, and the connecting member 82 are omitted from the example of FIG. Further, in the top view illustrated in FIG. 2, three combinations of the semiconductor chips 10a and 20b are illustrated. In the example of FIG. 2, three wiring portions 42 are provided on the plate-like insulating member 30 c, and a balance resistor 44 is connected between each wiring portion 42 and the wiring portion 41.

ここで、半導体モジュール1に搭載された回路のうちで板状絶縁部材30cの上面31c上に配置された構成部分90c(図1の例では配線層40cが含まれ、図2の例では更にバランス抵抗44が含まれる)は、半導体チップ10a,20bに比べて消費電力(換言すれば、扱う電力)が低い。このため、当該構成部分90cを低電力部90cとも称することにする。   Here, among the circuits mounted on the semiconductor module 1, the component 90c (including the wiring layer 40c in the example of FIG. 1 and disposed on the upper surface 31c of the plate-like insulating member 30c is included. In the example of FIG. The resistor 44 is low in power consumption (in other words, handled power) compared to the semiconductor chips 10a and 20b. For this reason, the component 90c is also referred to as a low power unit 90c.

低電力部90cは、図1および図2の例では、半導体チップ10aに所定信号(例えばゲート信号等の制御信号)を供給する部分である。かかる信号供給部は例えば各種回路(例えば外部入力信号から半導体チップ10a用の制御信号を生成する回路)を含んでもよい。また、低電力部90cは、上記信号供給部に加えてあるいは替えて、例えば半導体チップ10a,20bの一方または両方から所定信号(例えばチップ温度に関する信号)を取得する信号取得部分を含んでもよい。また、低電力部90cは、例えば、外部端子が接続されるパッド部(金属層40cによって形成可能である)を更に含んでもよく、あるいは、そのようなパッド部だけを含んでもよい。   In the example of FIGS. 1 and 2, the low power unit 90c is a part that supplies a predetermined signal (for example, a control signal such as a gate signal) to the semiconductor chip 10a. The signal supply unit may include, for example, various circuits (for example, a circuit that generates a control signal for the semiconductor chip 10a from an external input signal). In addition to or instead of the signal supply unit, the low power unit 90c may include a signal acquisition unit that acquires a predetermined signal (for example, a signal related to the chip temperature) from one or both of the semiconductor chips 10a and 20b, for example. In addition, the low power portion 90c may further include, for example, a pad portion (which can be formed by the metal layer 40c) to which an external terminal is connected, or may include only such a pad portion.

なお、外部端子と半導体チップ10a,20bとの接続は、低電力部90c内の上記パッド部を利用せずに、直接的な接合またはボンディングワイヤ等を介した間接的な接続によっても、実現可能である。   The connection between the external terminal and the semiconductor chips 10a and 20b can be realized by direct bonding or indirect connection through a bonding wire or the like without using the pad portion in the low power portion 90c. It is.

このように低電力部90cは種々の構成を採用可能であるが、上記のように半導体チップ10a,20bに比べて消費電力が低く、よって半導体チップ10a,20bに比べて発熱が小さい。   As described above, the low power unit 90c can employ various configurations, but as described above, the power consumption is lower than that of the semiconductor chips 10a and 20b, and thus the heat generation is lower than that of the semiconductor chips 10a and 20b.

半導体モジュール1の上記構成によれば、半導体チップ10a,20bと低電力部90cの両方がヒートシンク60の上面61の側に設けられており、半導体チップ10a,20bとヒートシンク60との間に板状絶縁部材30abが延在しており、低電力部90cとヒートシンク60との間に板状絶縁部材30cが延在している。また、板状絶縁部材30cのうちで低電力部90cに面する部分33cの厚さtcは、板状絶縁部材30abのうちで半導体チップ10a,20bに面する部分33abの厚さtabに比べて大きい(tc>tab)。   According to the above configuration of the semiconductor module 1, both the semiconductor chips 10 a and 20 b and the low power portion 90 c are provided on the upper surface 61 side of the heat sink 60, and a plate shape is provided between the semiconductor chips 10 a and 20 b and the heat sink 60. The insulating member 30ab extends, and the plate-like insulating member 30c extends between the low power portion 90c and the heat sink 60. Further, the thickness tc of the portion 33c of the plate-like insulating member 30c facing the low power portion 90c is larger than the thickness tab of the portion 33ab of the plate-like insulating member 30ab facing the semiconductor chips 10a and 20b. Large (tc> tab).

したがって、半導体チップ10a,20b用の薄い板状絶縁部材30abによって、半導体チップ10a,20b下の熱抵抗を低減できる。よって、半導体チップ10a,20bについての放熱性を確保できる。更に、低電力部90cは半導体チップ10a,20bに比べて発熱が小さいことに鑑み、低電力部90c用に厚い板状絶縁部材30cを採用することによって、板状絶縁部材30ab,30cおよびヒートシンク60を介した半導体チップ10a,20bと低電力部90cとの間の容量性結合を低減できる。よって、半導体チップ10a,20bと低電力部90cとの間の絶縁性を確保できる。このように、半導体モジュール1によれば、放熱性と絶縁性の両方を確保できる。   Accordingly, the thin plate-like insulating member 30ab for the semiconductor chips 10a and 20b can reduce the thermal resistance under the semiconductor chips 10a and 20b. Therefore, the heat dissipation of the semiconductor chips 10a and 20b can be ensured. Further, in view of the fact that the low power portion 90c generates less heat than the semiconductor chips 10a and 20b, by adopting the thick plate insulating member 30c for the low power portion 90c, the plate insulating members 30ab and 30c and the heat sink 60 are used. Capacitive coupling between the semiconductor chips 10a and 20b and the low power unit 90c via the semiconductor device can be reduced. Therefore, insulation between the semiconductor chips 10a and 20b and the low power part 90c can be ensured. Thus, according to the semiconductor module 1, both heat dissipation and insulation can be ensured.

なお、図1の例では板状絶縁部材30ab,30cが離間しているが、これらの板状絶縁部材30ab,30cは接触していても構わない。かかる変形は後述の各種の半導体モジュールにも適用可能である。   In the example of FIG. 1, the plate-like insulating members 30ab and 30c are separated from each other, but these plate-like insulating members 30ab and 30c may be in contact with each other. Such modifications can also be applied to various semiconductor modules described later.

<実施の形態2>
図3に、実施の形態2に係る半導体モジュール1Bの断面図を例示する。半導体モジュール1Bは、実施の形態1で例示した半導体モジュール1(図1参照)において板状絶縁部材30ab,30cを板状絶縁部材30abcに変更した構成を有している。半導体モジュール1Bのその他の構成は基本的に上記半導体モジュール1と同様である。
<Embodiment 2>
FIG. 3 illustrates a cross-sectional view of the semiconductor module 1B according to the second embodiment. The semiconductor module 1B has a configuration in which the plate-like insulating members 30ab and 30c are changed to the plate-like insulating member 30abc in the semiconductor module 1 (see FIG. 1) exemplified in the first embodiment. The other configuration of the semiconductor module 1B is basically the same as that of the semiconductor module 1.

板状絶縁部材30abcは、概略的には、実施の形態1で例示した板状絶縁部材30ab,30c(図1参照)を一体化した部材に相当する。すなわち、板状絶縁部材30abcは、半導体チップ10a,20bとヒートシンク60との間に延在すると共に、低電力部90cとヒートシンク60との間にも延在している。板状絶縁部材30abcは、互いに表裏の関係にある主面31abc,32abcを有している。図3の図示に合わせて、主面31abcを上面31abcとも称し、主面32abcを下面32abcとも称する。   The plate-like insulating member 30abc roughly corresponds to a member obtained by integrating the plate-like insulating members 30ab and 30c (see FIG. 1) exemplified in the first embodiment. That is, the plate-like insulating member 30abc extends between the semiconductor chips 10a and 20b and the heat sink 60, and also extends between the low power portion 90c and the heat sink 60. The plate-like insulating member 30abc has main surfaces 31abc and 32abc that are in a relationship of front and back. In conformity with the illustration of FIG. 3, the main surface 31abc is also referred to as an upper surface 31abc, and the main surface 32abc is also referred to as a lower surface 32abc.

かかる共通の板状絶縁部材30abcにおいて、低電力部90cに面する部分33cの厚さtcが、半導体チップ10a,20bに面する部分33abの厚さtabに比べて大きい(tc>tab)。図3の例では、板状絶縁部材30abcの上面31abcにおいて、半導体チップ10a,20bに面する領域が、低電力部90cに面する領域に比べて、下面32abc寄りに位置している。図3の例では、いずれの領域も平坦である。他方、板状絶縁部材30abcの下面32abcは図3の例では平坦である。上面31abcおよび下面32abcのかかる形状によって、共通の板状絶縁部材30abc中に異なる厚さが形成されている。   In the common plate-like insulating member 30abc, the thickness tc of the portion 33c facing the low power portion 90c is larger than the thickness tab of the portion 33ab facing the semiconductor chips 10a and 20b (tc> tab). In the example of FIG. 3, in the upper surface 31abc of the plate-like insulating member 30abc, the region facing the semiconductor chips 10a and 20b is located closer to the lower surface 32abc than the region facing the low power part 90c. In the example of FIG. 3, all the regions are flat. On the other hand, the lower surface 32abc of the plate-like insulating member 30abc is flat in the example of FIG. Due to the shapes of the upper surface 31abc and the lower surface 32abc, different thicknesses are formed in the common plate-like insulating member 30abc.

かかる厚さの違いは、例えば、硬化前の板状絶縁部材を2段階で圧延することによって形成可能である。具体的には、硬化前の板状絶縁部材を、まず上記厚い部分33cの厚さに合わせて圧延し、その後、所定部分を上記薄い部分33abの厚さに合わせて再度圧延する。   Such a difference in thickness can be formed, for example, by rolling the plate-like insulating member before curing in two stages. Specifically, the plate-like insulating member before curing is first rolled according to the thickness of the thick portion 33c, and then the predetermined portion is rolled again according to the thickness of the thin portion 33ab.

半導体モジュール1Bによれば、上記半導体モジュール1と同様に、放熱性と絶縁性の両方を確保できる。具体的には、板状絶縁部材30abcのうちで半導体チップ10a,20bに面する薄い部分33abによって、半導体チップ10a,20b下の熱抵抗を低減できる。よって、半導体チップ10a,20bについての放熱性を確保できる。更に、板状絶縁部材30abcのうちで低電力部90cに面する厚い部分33cによって、板状絶縁部材30abcおよびヒートシンク60を介した半導体チップ10a,20bと低電力部90cとの間の容量性結合を低減できる。よって、半導体チップ10a,20bと低電力部90cとの間の絶縁性を確保できる。   According to the semiconductor module 1 </ b> B, both heat dissipation and insulation can be secured in the same manner as the semiconductor module 1. Specifically, the thermal resistance under the semiconductor chips 10a and 20b can be reduced by the thin portion 33ab facing the semiconductor chips 10a and 20b in the plate-like insulating member 30abc. Therefore, the heat dissipation of the semiconductor chips 10a and 20b can be ensured. Further, capacitive coupling between the semiconductor chips 10a, 20b and the low power portion 90c via the plate-like insulating member 30abc and the heat sink 60 is performed by the thick portion 33c of the plate-like insulating member 30abc facing the low power portion 90c. Can be reduced. Therefore, insulation between the semiconductor chips 10a and 20b and the low power part 90c can be ensured.

なお、板状絶縁部材30abcの下面32abc側の金属層50ab,50cは一続きの金属層に変更可能である。その場合、接合部材74ab,74cも一続きの接合部材に変更可能である。かかる変形は後述の各種の半導体モジュールにも適用可能である。   The metal layers 50ab and 50c on the lower surface 32abc side of the plate-like insulating member 30abc can be changed to a continuous metal layer. In that case, the joining members 74ab and 74c can be changed to a continuous joining member. Such modifications can also be applied to various semiconductor modules described later.

<実施の形態1,2の変形例>
図3に例示した半導体モジュール1Bは、板状絶縁部材30abcの上面31abcの端部に、突出部分34を有している。かかる突出部分34は、半導体チップ10a,20bに面する薄い部分33abを囲むように設けられている。なお、突出部分34の厚さは、図3の例ではtcに設定されているが、かかる例に限定されるものではない。
<Modification of Embodiments 1 and 2>
The semiconductor module 1B illustrated in FIG. 3 has a protruding portion 34 at the end of the upper surface 31abc of the plate-like insulating member 30abc. The protruding portion 34 is provided so as to surround the thin portion 33ab facing the semiconductor chips 10a and 20b. In addition, although the thickness of the protrusion part 34 is set to tc in the example of FIG. 3, it is not limited to this example.

これに対し、図4に例示する実施の形態2の変形例に係る半導体モジュール1Cのように、上記突出部分34を省略することも可能である。   On the other hand, the protruding portion 34 can be omitted as in the semiconductor module 1C according to the modification of the second embodiment illustrated in FIG.

突出部分34によれば、薄い部分33abの上面31abc側と下面32abc側との沿面距離(板状絶縁部材30abcの端面を介した距離)を長くすることが可能である。このため、上面31abc側の電位と下面32abc側の電位との間で沿面の絶縁性を確保することが可能である。   According to the protruding portion 34, it is possible to increase the creepage distance between the upper surface 31abc side and the lower surface 32abc side of the thin portion 33ab (distance through the end surface of the plate-like insulating member 30abc). Therefore, it is possible to ensure creeping insulation between the potential on the upper surface 31abc side and the potential on the lower surface 32abc side.

一方、突出部分34を有さない場合には、板状絶縁部材30abcの形状が単純化され、板状絶縁部材30abcの製造が容易になる。   On the other hand, when the protruding portion 34 is not provided, the shape of the plate-like insulating member 30abc is simplified, and the plate-like insulating member 30abc can be easily manufactured.

突出部分34は、実施の形態1で例示した半導体モジュール1にも採用可能である。図5に、そのような変形を加えた半導体モジュール1Dを例示する。図5の例では、半導体チップ10a,20b用の板状絶縁部材30abの上面31abの端部に、突出部分34が設けられている。   The protruding portion 34 can also be employed in the semiconductor module 1 exemplified in the first embodiment. FIG. 5 illustrates a semiconductor module 1D with such a modification. In the example of FIG. 5, the protruding portion 34 is provided at the end of the upper surface 31ab of the plate-like insulating member 30ab for the semiconductor chips 10a and 20b.

<実施の形態3>
さて、炭化珪素(SiC)、窒化ガリウム(GaN)等のいわゆるワイドバンドギャップ材料で構成された半導体チップは、珪素(Si)で構成された半導体チップに比べて、高温動作が可能である。換言すれば、ワイドバンドギャップ半導体によれば、耐熱性の高いチップが提供される。実施の形態3では、耐熱性の異なる半導体チップが混在した半導体モジュールを説明する。以下では、耐熱性がより高い方の半導体チップを高耐熱性チップとも称し、耐熱性がより低い方の半導体チップを便宜上、低耐熱性チップとも称する。
<Embodiment 3>
A semiconductor chip made of a so-called wide band gap material such as silicon carbide (SiC) or gallium nitride (GaN) can operate at a higher temperature than a semiconductor chip made of silicon (Si). In other words, the wide band gap semiconductor provides a chip with high heat resistance. In the third embodiment, a semiconductor module in which semiconductor chips having different heat resistance are mixed will be described. Hereinafter, the semiconductor chip having higher heat resistance is also referred to as a high heat resistance chip, and the semiconductor chip having lower heat resistance is also referred to as a low heat resistance chip for convenience.

図6に、実施の形態3に係る半導体モジュール1Eの断面図を例示する。半導体モジュール1Eは、実施の形態1で例示した半導体モジュール1(図1参照)において半導体チップ20bを半導体チップ10aに比べて耐熱性の高い高耐熱性チップ25bに変更した構成を有している。この例では、以下、半導体チップ10aを低耐熱性チップ10aとも称する。更に、半導体モジュール1Eでは、実施の形態1で例示した板状絶縁部材30ab等が低耐熱性チップ10a用と高耐熱性チップ25b用とに分割されている。半導体モジュール1Eのその他の構成は基本的に上記半導体モジュール1と同様である。   FIG. 6 illustrates a cross-sectional view of a semiconductor module 1E according to the third embodiment. The semiconductor module 1E has a configuration in which the semiconductor chip 20b in the semiconductor module 1 (see FIG. 1) exemplified in the first embodiment is changed to a high heat resistant chip 25b having higher heat resistance than the semiconductor chip 10a. In this example, hereinafter, the semiconductor chip 10a is also referred to as a low heat resistant chip 10a. Further, in the semiconductor module 1E, the plate-like insulating member 30ab and the like exemplified in the first embodiment are divided for the low heat resistant chip 10a and the high heat resistant chip 25b. The other configuration of the semiconductor module 1E is basically the same as that of the semiconductor module 1.

詳細には、低耐熱性チップ10a用の板状絶縁部材30aは、互いに表裏の関係にある主面31a,32aを有している。図6の図示に合わせて、主面31aを上面31aとも称し、主面32aを下面32aとも称する。ここでは主面31a,32aが平坦面であり平行をなしている場合を例示し、その場合、板状絶縁部材30aの厚さは部材全体に渡って均一である。   Specifically, the plate-like insulating member 30a for the low heat-resistant chip 10a has main surfaces 31a and 32a that are in a front-back relationship. In conformity with the illustration of FIG. 6, the main surface 31a is also referred to as an upper surface 31a, and the main surface 32a is also referred to as a lower surface 32a. Here, the case where the main surfaces 31a and 32a are flat surfaces and are parallel to each other is illustrated, and in this case, the thickness of the plate-like insulating member 30a is uniform over the entire member.

板状絶縁部材30aの上面31aに金属層40aが接合されており、当該金属層40aは接合部材72aによって低耐熱性チップ10aの下面12と接合されている。また、板状絶縁部材30aの下面32aに金属層50aが接合されており、当該金属層50aは接合部材74aによってヒートシンク60の上面61と接合されている。   A metal layer 40a is bonded to the upper surface 31a of the plate-like insulating member 30a, and the metal layer 40a is bonded to the lower surface 12 of the low heat resistant chip 10a by the bonding member 72a. Further, the metal layer 50a is bonded to the lower surface 32a of the plate-like insulating member 30a, and the metal layer 50a is bonded to the upper surface 61 of the heat sink 60 by the bonding member 74a.

また、高耐熱性チップ25b用の板状絶縁部材35bは、互いに表裏の関係にある主面36b,37bを有している。図6の図示に合わせて、主面36bを上面36bとも称し、主面37bを下面37bとも称する。ここでは主面36b,37bが平坦面であり平行をなしている場合を例示し、その場合、板状絶縁部材35bの厚さは部材全体に渡って均一である。   Further, the plate-like insulating member 35b for the high heat-resistant chip 25b has main surfaces 36b and 37b which are in a relationship of front and back. In conformity with the illustration of FIG. 6, the main surface 36b is also referred to as an upper surface 36b, and the main surface 37b is also referred to as a lower surface 37b. Here, a case where the main surfaces 36b and 37b are flat surfaces and parallel to each other is illustrated, and in this case, the thickness of the plate-like insulating member 35b is uniform over the entire member.

板状絶縁部材35bの上面36bに金属層40bが接合されており、当該金属層40bは接合部材72bによって高耐熱性チップ25bの下面22と接合されている。また、板状絶縁部材35bの下面37aに金属層50bが接合されており、当該金属層50bは接合部材74bによってヒートシンク60の上面61と接合されている。   A metal layer 40b is bonded to the upper surface 36b of the plate-like insulating member 35b, and the metal layer 40b is bonded to the lower surface 22 of the high heat resistant chip 25b by the bonding member 72b. The metal layer 50b is bonded to the lower surface 37a of the plate-like insulating member 35b, and the metal layer 50b is bonded to the upper surface 61 of the heat sink 60 by the bonding member 74b.

なお、板状絶縁部材30aと金属層40a,50aとの積層体と、板状絶縁部材35bと金属層40b,50bとの積層体とはそれぞれ、絶縁基板と称される場合もある。   In addition, the laminated body of the plate-shaped insulating member 30a and the metal layers 40a and 50a and the laminated body of the plate-shaped insulating member 35b and the metal layers 40b and 50b may be respectively referred to as an insulating substrate.

半導体モジュール1Eの上記構成によれば、低耐熱性チップ10aとヒートシンク60との間に板状絶縁部材30aが延在しており、高耐熱性チップ25bとヒートシンク60との間に板状絶縁部材35bが延在しており、低電力部90cとヒートシンク60との間に板状絶縁部材30cが延在している。   According to the above configuration of the semiconductor module 1E, the plate-like insulating member 30a extends between the low heat-resistant chip 10a and the heat sink 60, and the plate-like insulating member between the high heat-resistant chip 25b and the heat sink 60. 35 b extends, and the plate-like insulating member 30 c extends between the low power portion 90 c and the heat sink 60.

また、板状絶縁部材30cのうちで低電力部90cに面する部分33cの厚さtcは、板状絶縁部材30aのうちで低耐熱性チップ10aに面する部分33aの厚さtaに比べて大きい(tc>ta)。また、板状絶縁部材35bのうちで高耐熱性チップ25bに面する部分38bの厚さtbは、板状絶縁部材30aのうちで低耐熱性チップ10aに面する部分33aの厚さtaに比べて大きい(tb>ta)。なお、図6の例ではtb=tcであるが、この例に限定されるものではない。   In addition, the thickness tc of the portion 33c of the plate-like insulating member 30c facing the low power portion 90c is larger than the thickness ta of the portion 33a of the plate-like insulating member 30a facing the low heat resistant chip 10a. Large (tc> ta). Further, the thickness tb of the portion 38b of the plate-like insulating member 35b facing the high heat-resistant chip 25b is compared with the thickness ta of the portion 33a of the plate-like insulating member 30a facing the low heat-resistant chip 10a. Large (tb> ta). In the example of FIG. 6, tb = tc, but is not limited to this example.

半導体モジュール1Eによれば、低耐熱性チップ10aと低電力部90cと板状絶縁部材30a,30cとヒートシンク60との関係は実施の形態1と同様であるので、半導体モジュール1Eは実施の形態1と同様の効果を奏する。   According to the semiconductor module 1E, the relationship between the low heat resistance chip 10a, the low power portion 90c, the plate-like insulating members 30a and 30c, and the heat sink 60 is the same as that in the first embodiment. Has the same effect as.

特に高耐熱性チップ25b用の板状絶縁部材35bは低耐熱性チップ10a用の板状絶縁部材30aに比べて厚いので、板状絶縁部材35bを介した高耐熱性チップ25bとヒートシンク60との間の容量性結合を、板状絶縁部材30aを介した低耐熱性チップ20aとヒートシンク60との間の容量性結合に比べて低減可能である。よって、高耐熱性チップ25bと低電力部90cとの間の絶縁性、更には高耐熱性チップ25bと低耐熱性チップ10aとの間の絶縁性を確保できる。   In particular, the plate-like insulating member 35b for the high heat-resistant chip 25b is thicker than the plate-like insulating member 30a for the low heat-resistant chip 10a, so that the high-heat-resistant chip 25b and the heat sink 60 are interposed via the plate-like insulating member 35b. The capacitive coupling can be reduced as compared with the capacitive coupling between the low heat resistant chip 20a and the heat sink 60 via the plate-like insulating member 30a. Therefore, it is possible to ensure insulation between the high heat resistance chip 25b and the low power portion 90c, and further insulation between the high heat resistance chip 25b and the low heat resistance chip 10a.

ここで、厚い板状絶縁部材35bによれば熱抵抗が大きくなるが、高耐熱性チップ25bは低耐熱性チップ10aに比べて高温動作が可能であるので、高耐熱性チップ25bの正常動作を確保可能である。   Here, the thick plate-like insulating member 35b increases the thermal resistance, but the high heat-resistant chip 25b can operate at a higher temperature than the low heat-resistant chip 10a. It can be secured.

<実施の形態4>
図7に、実施の形態4に係る半導体モジュール1Fの断面図を例示する。半導体モジュール1Fは、実施の形態3で例示した半導体モジュール1E(図6参照)において板状絶縁部材30a,35b,30cを板状絶縁部材35abcに変更した構成を有している。半導体モジュール1Fのその他の構成は基本的に上記半導体モジュール1Eと同様である。
<Embodiment 4>
FIG. 7 illustrates a cross-sectional view of a semiconductor module 1F according to the fourth embodiment. The semiconductor module 1F has a configuration in which the plate-like insulating members 30a, 35b, and 30c are changed to the plate-like insulating member 35abc in the semiconductor module 1E exemplified in the third embodiment (see FIG. 6). The other configuration of the semiconductor module 1F is basically the same as that of the semiconductor module 1E.

板状絶縁部材35abcは、概略的には、実施の形態3で例示した板状絶縁部材30a,35b,30c(図6参照)を一体化した部材に相当する。すなわち、板状絶縁部材35abcは、低耐熱性チップ10aとヒートシンク60との間に延在し、更に低電力部90cとヒートシンク60との間にも延在し、更に高耐熱性チップ25bとヒートシンク60との間にも延在している。板状絶縁部材35abcは、互いに表裏の関係にある主面36abc,37abcを有している。図7の図示に合わせて、主面36abcを上面36abcとも称し、主面37abcを下面37abcとも称する。   The plate-like insulating member 35abc roughly corresponds to a member obtained by integrating the plate-like insulating members 30a, 35b, and 30c (see FIG. 6) exemplified in the third embodiment. That is, the plate-like insulating member 35abc extends between the low heat resistant chip 10a and the heat sink 60, further extends between the low power portion 90c and the heat sink 60, and further, the high heat resistant chip 25b and the heat sink. 60 also extends. The plate-like insulating member 35abc has main surfaces 36abc and 37abc that are in a front-back relationship. In conformity with the illustration in FIG. 7, the main surface 36abc is also referred to as an upper surface 36abc, and the main surface 37abc is also referred to as a lower surface 37abc.

板状絶縁部材35abcのうちで低電力部90cに面する部分33cの厚さtcは、板状絶縁部材35abcのうちで低耐熱性チップ10aに面する部分33aの厚さtaに比べて大きい(tc>ta)。また、板状絶縁部材35abcのうちで高耐熱性チップ25bに面する部分38bの厚さtbは、板状絶縁部材35abcのうちで低耐熱性チップ10aに面する部分33aの厚さtaに比べて大きい(tb>ta)。なお、図7の例ではtb=tcであるが、この例に限定されるものではない。   The thickness tc of the portion 33c of the plate-like insulating member 35abc facing the low power portion 90c is larger than the thickness ta of the portion 33a of the plate-like insulating member 35abc facing the low heat resistant chip 10a ( tc> ta). Further, the thickness tb of the portion 38b of the plate-like insulating member 35abc facing the high heat-resistant chip 25b is compared with the thickness ta of the portion 33a of the plate-like insulating member 35abc facing the low heat-resistant chip 10a. Large (tb> ta). In the example of FIG. 7, tb = tc, but is not limited to this example.

図7の例では、板状絶縁部材35abcの上面36abcにおいて、低耐熱性チップ10aに面する領域が、低電力部90cに面する領域および高耐熱性チップ25bに面する領域に比べて、下面37bac寄りに位置している。図7の例では、いずれの領域も平坦である。他方、板状絶縁部材35abcの下面37abcは図7の例では平坦である。上面36abcおよび下面37abcのかかる形状によって、共通の板状絶縁部材35abc中に異なる厚さが形成されている。かかる厚さの違いは、例えば、実施の形態2で例示した板状絶縁部材30abc(図3参照)と同様に形成可能である。   In the example of FIG. 7, in the upper surface 36abc of the plate-like insulating member 35abc, the region facing the low heat resistant chip 10a is lower than the region facing the low power portion 90c and the region facing the high heat resistant chip 25b. It is located near 37bac. In the example of FIG. 7, all the regions are flat. On the other hand, the lower surface 37abc of the plate-like insulating member 35abc is flat in the example of FIG. Depending on the shape of the upper surface 36abc and the lower surface 37abc, different thicknesses are formed in the common plate-like insulating member 35abc. Such a difference in thickness can be formed, for example, in the same manner as the plate-like insulating member 30abc (see FIG. 3) exemplified in the second embodiment.

半導体モジュール1Fによれば、低耐熱性チップ10aと高耐熱性チップ25bと低電力部90cと板状絶縁部材35abcとヒートシンク60との関係は実施の形態3と同様であるので、半導体モジュール1Fは実施の形態3と同様の効果を奏する。   According to the semiconductor module 1F, the relationship between the low heat resistance chip 10a, the high heat resistance chip 25b, the low power portion 90c, the plate-like insulating member 35abc, and the heat sink 60 is the same as that in the third embodiment. The same effect as in the third embodiment is obtained.

<実施の形態5>
図8に、実施の形態5に係る半導体モジュール1Gの断面図を例示する。半導体モジュール1Gは、実施の形態3で例示した半導体モジュール1E(図6参照)において板状絶縁部材30a,30cを板状絶縁部材30acに変更した構成を有している。半導体モジュール1Gのその他の構成は基本的に上記半導体モジュール1Eと同様である。
<Embodiment 5>
FIG. 8 illustrates a cross-sectional view of a semiconductor module 1G according to the fifth embodiment. The semiconductor module 1G has a configuration in which the plate-like insulating members 30a and 30c are changed to plate-like insulating members 30ac in the semiconductor module 1E exemplified in the third embodiment (see FIG. 6). The other configuration of the semiconductor module 1G is basically the same as that of the semiconductor module 1E.

板状絶縁部材30acは、概略的には、実施の形態3で例示した板状絶縁部材30a,30c(図6参照)を一体化した部材に相当する。すなわち、板状絶縁部材30acは、低耐熱性チップ10aとヒートシンク60との間に延在すると共に、低電力部90cとヒートシンク60との間にも延在している。板状絶縁部材30acは、互いに表裏の関係にある主面31ac,32acを有している。図8の図示に合わせて、主面31acを上面31acとも称し、主面32acを下面32acとも称する。   The plate-like insulating member 30ac schematically corresponds to a member obtained by integrating the plate-like insulating members 30a and 30c (see FIG. 6) exemplified in the third embodiment. That is, the plate-like insulating member 30ac extends between the low heat resistant chip 10a and the heat sink 60 and also extends between the low power portion 90c and the heat sink 60. The plate-like insulating member 30ac has main surfaces 31ac and 32ac that are in a front-back relationship. In conformity with the illustration of FIG. 8, the main surface 31ac is also referred to as an upper surface 31ac, and the main surface 32ac is also referred to as a lower surface 32ac.

板状絶縁部材30acのうちで低電力部90cに面する部分33cの厚さtcは、板状絶縁部材30acのうちで低耐熱性チップ10aに面する部分33aの厚さtaに比べて大きい(tc>ta)。図8の例では、板状絶縁部材30acの上面31acにおいて、低耐熱性チップ10aに面する領域が、低電力部90cに面する領域に比べて、下面32ac寄りに位置している。図8の例では、いずれの領域も平坦である。他方、板状絶縁部材30acの下面32acは図8の例では平坦である。上面31acおよび下面32acのかかる形状によって、共通の板状絶縁部材30ac中に異なる厚さが形成されている。かかる厚さの違いは、例えば、実施の形態2で例示した板状絶縁部材30abc(図3参照)と同様に形成可能である。   The thickness tc of the portion 33c of the plate-like insulating member 30ac facing the low power portion 90c is larger than the thickness ta of the portion 33a of the plate-like insulating member 30ac facing the low heat resistant chip 10a ( tc> ta). In the example of FIG. 8, in the upper surface 31ac of the plate-like insulating member 30ac, the region facing the low heat resistant chip 10a is located closer to the lower surface 32ac than the region facing the low power portion 90c. In the example of FIG. 8, all the regions are flat. On the other hand, the lower surface 32ac of the plate-like insulating member 30ac is flat in the example of FIG. Depending on the shape of the upper surface 31ac and the lower surface 32ac, different thicknesses are formed in the common plate-like insulating member 30ac. Such a difference in thickness can be formed, for example, in the same manner as the plate-like insulating member 30abc (see FIG. 3) exemplified in the second embodiment.

半導体モジュール1Gによれば、低耐熱性チップ10aと高耐熱性チップ25bと低電力部90cと板状絶縁部材30ac,35bとヒートシンク60との関係は実施の形態3と同様であるので、半導体モジュール1Gは実施の形態3と同様の効果を奏する。   According to the semiconductor module 1G, the relationship between the low heat resistance chip 10a, the high heat resistance chip 25b, the low power portion 90c, the plate-like insulating members 30ac and 35b, and the heat sink 60 is the same as that in the third embodiment. 1G has the same effect as the third embodiment.

<実施の形態6>
図9に、実施の形態6に係る半導体モジュール1Hの断面図を例示する。半導体モジュール1Hは、実施の形態3で例示した半導体モジュール1E(図6参照)において板状絶縁部材30a,35bを板状絶縁部材35abに変更した構成を有している。半導体モジュール1Hのその他の構成は基本的に上記半導体モジュール1Eと同様である。
<Embodiment 6>
FIG. 9 illustrates a cross-sectional view of a semiconductor module 1H according to the sixth embodiment. The semiconductor module 1H has a configuration in which the plate-like insulating members 30a and 35b are changed to plate-like insulating members 35ab in the semiconductor module 1E exemplified in the third embodiment (see FIG. 6). The other configuration of the semiconductor module 1H is basically the same as that of the semiconductor module 1E.

板状絶縁部材35abは、概略的には、実施の形態3で例示した板状絶縁部材30a,35b(図6参照)を一体化した部材に相当する。すなわち、板状絶縁部材35abは、低耐熱性チップ10aとヒートシンク60との間に延在すると共に、高耐熱性チップ25bとヒートシンク60との間にも延在している。板状絶縁部材35abは、互いに表裏の関係にある主面36ab,37abを有している。図9の図示に合わせて、主面36abを上面36abとも称し、主面37abを下面37abとも称する。   The plate-like insulating member 35ab roughly corresponds to a member obtained by integrating the plate-like insulating members 30a and 35b (see FIG. 6) exemplified in the third embodiment. That is, the plate-like insulating member 35ab extends between the low heat resistant chip 10a and the heat sink 60 and also extends between the high heat resistant chip 25b and the heat sink 60. The plate-like insulating member 35ab has main surfaces 36ab and 37ab that are in a relationship of front and back. In conformity with the illustration of FIG. 9, the main surface 36ab is also referred to as an upper surface 36ab, and the main surface 37ab is also referred to as a lower surface 37ab.

板状絶縁部材35abのうちで高耐熱性チップ25bに面する部分38bの厚さtbは、板状絶縁部材35abのうちで低耐熱性チップ10aに面する部分33aの厚さtaに比べて大きい(tb>ta)。図9の例では、板状絶縁部材35abの上面36abにおいて、低耐熱性チップ10aに面する領域が、高耐熱性チップ25bに面する領域に比べて、下面37ab寄りに位置している。図9の例では、いずれの領域も平坦である。他方、板状絶縁部材35abの下面37abは図9の例では平坦である。上面36abおよび下面37abのかかる形状によって、共通の板状絶縁部材35ab中に異なる厚さが形成されている。かかる厚さの違いは、例えば、実施の形態2で例示した板状絶縁部材30abc(図3参照)と同様に形成可能である。   The thickness tb of the portion 38b of the plate-like insulating member 35ab facing the high heat resistant chip 25b is larger than the thickness ta of the portion 33a of the plate-like insulating member 35ab facing the low heat resistant chip 10a. (Tb> ta). In the example of FIG. 9, in the upper surface 36ab of the plate-like insulating member 35ab, the region facing the low heat resistant chip 10a is located closer to the lower surface 37ab than the region facing the high heat resistant chip 25b. In the example of FIG. 9, all the regions are flat. On the other hand, the lower surface 37ab of the plate-like insulating member 35ab is flat in the example of FIG. Due to such shapes of the upper surface 36ab and the lower surface 37ab, different thicknesses are formed in the common plate-like insulating member 35ab. Such a difference in thickness can be formed, for example, in the same manner as the plate-like insulating member 30abc (see FIG. 3) exemplified in the second embodiment.

半導体モジュール1Hによれば、低耐熱性チップ10aと高耐熱性チップ25bと低電力部90cと板状絶縁部材35ab,30cとヒートシンク60との関係は実施の形態3と同様であるので、半導体モジュール1Hは実施の形態3と同様の効果を奏する。   According to the semiconductor module 1H, the relationship between the low heat resistance chip 10a, the high heat resistance chip 25b, the low power portion 90c, the plate-like insulating members 35ab and 30c, and the heat sink 60 is the same as that in the third embodiment. 1H has the same effect as the third embodiment.

<実施の形態7>
図10に、実施の形態7に係る半導体モジュール1Iの断面図を例示する。半導体モジュール1Iは、実施の形態3で例示した半導体モジュール1E(図6参照)から、低電力部90cと板状絶縁部材30cと金属層50cと接合部材74cと接続部材84,86とを省略した構成を有している。半導体モジュール1Iのその他の構成は基本的に上記半導体モジュール1Eと同様である。
<Embodiment 7>
FIG. 10 illustrates a cross-sectional view of a semiconductor module 1I according to the seventh embodiment. In the semiconductor module 1I, the low power portion 90c, the plate-like insulating member 30c, the metal layer 50c, the joining member 74c, and the connecting members 84 and 86 are omitted from the semiconductor module 1E illustrated in the third embodiment (see FIG. 6). It has a configuration. The other configuration of the semiconductor module 1I is basically the same as that of the semiconductor module 1E.

なお、半導体モジュール1Iの構成は、実施の形態5で例示した半導体モジュール1G(図8参照)から、低電力部90cと金属層50cと接合部材74cと接続部材84,86とを省略すると共に、板状絶縁部材30acのうちで低電力部90c用の上記厚い部分33cを省略した構成と捉えることも可能である。   The configuration of the semiconductor module 1I omits the low power portion 90c, the metal layer 50c, the joining member 74c, and the connecting members 84 and 86 from the semiconductor module 1G illustrated in the fifth embodiment (see FIG. 8). It can also be understood that the thick portion 33c for the low power portion 90c is omitted from the plate-like insulating member 30ac.

半導体モジュール1Iによれば、低耐熱性チップ10aと高耐熱性チップ25bと板状絶縁部材30a,35bとヒートシンク60との関係は実施の形態3と同様であるので、半導体モジュール1Iは実施の形態3と同様の効果を奏する。   According to the semiconductor module 1I, the relationship between the low heat resistant chip 10a, the high heat resistant chip 25b, the plate-like insulating members 30a and 35b, and the heat sink 60 is the same as that in the third embodiment. 3 has the same effect.

<実施の形態8>
図11に、実施の形態8に係る半導体モジュール1Jの断面図を例示する。半導体モジュール1Jは、実施の形態6で例示した半導体モジュール1H(図9参照)から、低電力部90cと板状絶縁部材30cと金属層50cと接合部材74cと接続部材84,86とを省略した構成を有している。半導体モジュール1Jのその他の構成は基本的に上記半導体モジュール1Hと同様である。
<Eighth embodiment>
FIG. 11 illustrates a cross-sectional view of a semiconductor module 1J according to the eighth embodiment. The semiconductor module 1J omits the low power portion 90c, the plate-like insulating member 30c, the metal layer 50c, the joining member 74c, and the connecting members 84 and 86 from the semiconductor module 1H illustrated in the sixth embodiment (see FIG. 9). It has a configuration. The other configuration of the semiconductor module 1J is basically the same as that of the semiconductor module 1H.

なお、半導体モジュール1Jの構成は、実施の形態4で例示した半導体モジュール1F(図7参照)から、低電力部90cと金属層50cと接合部材74cと接続部材84,86とを省略すると共に、板状絶縁部材35abcのうちで低電力部90c用の上記厚い部分33cを省略した構成と捉えることも可能である。   The configuration of the semiconductor module 1J omits the low power portion 90c, the metal layer 50c, the joining member 74c, and the connection members 84 and 86 from the semiconductor module 1F illustrated in the fourth embodiment (see FIG. 7). It can also be understood that the thick portion 33c for the low power portion 90c is omitted from the plate-like insulating member 35abc.

半導体モジュール1Jによれば、低耐熱性チップ10aと高耐熱性チップ25bと板状絶縁部材35abとヒートシンク60との関係は実施の形態3と同様であるので、半導体モジュール1Jは実施の形態3と同様の効果を奏する。   According to the semiconductor module 1J, the relationship between the low heat resistant chip 10a, the high heat resistant chip 25b, the plate-like insulating member 35ab, and the heat sink 60 is the same as that in the third embodiment. The same effect is produced.

<実施の形態3〜8の変形例>
実施の形態1,2の変形例で例示した突出部分34(図3および図5参照)は、実施の形態3〜8にも採用可能である。
<Modifications of Embodiments 3 to 8>
The protruding portion 34 (see FIGS. 3 and 5) exemplified in the modification of the first and second embodiments can also be adopted in the third to eighth embodiments.

<実施の形態1〜8の変形例>
本発明は、その発明の範囲内において、各実施の形態を自由に組み合わせたり、各実施の形態を適宜、変形、省略することが可能である。
<Modification of Embodiments 1-8>
The present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

1,1B〜1J 半導体モジュール、10a,20b パワー半導体チップ、25b 高耐熱性チップ、30ab,30c,30abc,30a,35b,35abc,30ac,35ab 板状絶縁部材、60 ヒートシンク、61 主面(所定面)、90c 低電力部、33ab,33a パワー半導体チップに面する部分、33c 低電力部に面する部分、38b 高耐熱性チップに面する部分、tab,tc,ta,tb 厚さ。   1,1B-1J Semiconductor module, 10a, 20b Power semiconductor chip, 25b High heat resistance chip, 30ab, 30c, 30abc, 30a, 35b, 35abc, 30ac, 35ab Plate-shaped insulating member, 60 Heat sink, 61 Main surface (predetermined surface ), 90c Low power portion, 33ab, 33a The portion facing the power semiconductor chip, 33c The portion facing the low power portion, 38b The portion facing the high heat resistant chip, tab, tc, ta, tb thickness.

Claims (8)

導電性を有するヒートシンク(60)と、
前記ヒートシンク(60)の所定面(61)の側に設けられたパワー半導体チップ(10a,20b)と、
前記ヒートシンク(60)の前記所定面(61)の側に設けられており前記パワー半導体チップ(10a,20b)に比べて消費電力が低い低電力部(90c)と、
前記パワー半導体チップ(10a,20b)と前記ヒートシンク(60)との間に延在した第1の板状絶縁部材(30ab,30a,35ab)と、
前記低電力部(90c)と前記ヒートシンク(60)との間に延在した第2の板状絶縁部材(30c)と
を備え、
前記第2の板状絶縁部材(30c)のうちで前記低電力部(90c)に面する部分(33c)は、前記第1の板状絶縁部材(30ab,30a,35ab)のうちで前記パワー半導体チップ(10a,20b)に面する部分(33ab,33a)に比べて厚い、半導体モジュール(1,1D,1E,1H)。
A conductive heat sink (60);
Power semiconductor chips (10a, 20b) provided on the predetermined surface (61) side of the heat sink (60);
A low power portion (90c) provided on the predetermined surface (61) side of the heat sink (60) and having lower power consumption than the power semiconductor chips (10a, 20b);
A first plate-like insulating member (30ab, 30a, 35ab) extending between the power semiconductor chip (10a, 20b) and the heat sink (60);
A second plate-like insulating member (30c) extending between the low power part (90c) and the heat sink (60),
Of the second plate-like insulating member (30c), the portion (33c) facing the low power portion (90c) is the power of the first plate-like insulating member (30ab, 30a, 35ab). The semiconductor module (1, 1D, 1E, 1H) is thicker than the portions (33ab, 33a) facing the semiconductor chip (10a, 20b).
前記ヒートシンク(60)の前記所定面(61)の側に設けられており前記パワー半導体チップ(10a)に比べて耐熱性が高い高耐熱性チップ(25b)と、
前記高耐熱性チップ(25b)と前記ヒートシンク(60)との間に延在した第3の板状絶縁部材(35b)と
を更に備え、
前記第3の板状絶縁部材(35b)のうちで前記高耐熱性チップ(25b)に面する部分(38b)は、前記第1の板状絶縁部材(30a)のうちで前記パワー半導体チップ(10a)に面する前記部分(33a)に比べて厚い、請求項1に記載の半導体モジュール(1E)。
A high heat resistant chip (25b) which is provided on the predetermined surface (61) side of the heat sink (60) and has higher heat resistance than the power semiconductor chip (10a);
A third plate-like insulating member (35b) extending between the high heat-resistant chip (25b) and the heat sink (60);
Of the third plate-like insulating member (35b), the portion (38b) facing the high heat-resistant chip (25b) is the power semiconductor chip (30b) of the first plate-like insulating member (30a). The semiconductor module (1E) according to claim 1, which is thicker than said part (33a) facing 10a).
前記ヒートシンク(60)の前記所定面(61)の側に設けられており前記パワー半導体チップ(10a)に比べて耐熱性が高い高耐熱性チップ(25b)を更に備え、
前記第1の板状絶縁部材(35ab)は前記高耐熱性チップ(25b)と前記ヒートシンク(60)との間にも延在しており、
前記第1の板状絶縁部材(35ab)のうちで前記高耐熱性チップ(25b)に面する部分(38b)は、前記第1の板状絶縁部材(35ab)のうちで前記パワー半導体チップ(10a)に面する前記部分(33a)に比べて厚い、請求項1に記載の半導体モジュール(1H)。
A heat-resistant chip (25b) which is provided on the predetermined surface (61) side of the heat sink (60) and has higher heat resistance than the power semiconductor chip (10a);
The first plate-like insulating member (35ab) also extends between the high heat resistant chip (25b) and the heat sink (60),
Of the first plate-like insulating member (35ab), the portion (38b) facing the high heat-resistant chip (25b) is the power semiconductor chip (35ab) of the first plate-like insulating member (35ab). The semiconductor module (1H) according to claim 1, which is thicker than said part (33a) facing 10a).
導電性を有するヒートシンク(60)と、
前記ヒートシンク(60)の所定面(61)の側に設けられたパワー半導体チップ(10a,20b)と、
前記ヒートシンク(60)の前記所定面(61)の側に設けられており前記パワー半導体チップ(10a,20b)に比べて消費電力が低い低電力部(90c)と、
前記パワー半導体チップ(10a,20b)と前記ヒートシンク(60)との間に延在すると共に前記低電力部(90c)と前記ヒートシンク(60)との間にも延在した共通の板状絶縁部材(30abc,35abc,30ac)と
を備え、
前記共通の板状絶縁部材(30abc,35abc,30ac)のうちで前記低電力部(90c)に面する部分(33c)は、前記共通の板状絶縁部材(30abc,35abc,30ac)のうちで前記パワー半導体チップ(10a,20b)に面する部分(33ab,33a)に比べて厚い、半導体モジュール(1B,1C,1F,1G)。
A conductive heat sink (60);
Power semiconductor chips (10a, 20b) provided on the predetermined surface (61) side of the heat sink (60);
A low power portion (90c) provided on the predetermined surface (61) side of the heat sink (60) and having lower power consumption than the power semiconductor chips (10a, 20b);
A common plate-like insulating member extending between the power semiconductor chip (10a, 20b) and the heat sink (60) and extending between the low power portion (90c) and the heat sink (60). (30abc, 35abc, 30ac)
Of the common plate-like insulating members (30abc, 35abc, 30ac), a portion (33c) facing the low power portion (90c) is formed of the common plate-like insulating members (30abc, 35abc, 30ac). Semiconductor modules (1B, 1C, 1F, 1G) which are thicker than the portions (33ab, 33a) facing the power semiconductor chips (10a, 20b).
前記ヒートシンク(60)の前記所定面(61)の側に設けられており前記パワー半導体チップ(10a)に比べて耐熱性が高い高耐熱性チップ(25b)を更に備え、
前記共通の板状絶縁部材(35abc)は前記高耐熱性チップ(25b)と前記ヒートシンク(60)との間にも延在しており、
前記共通の板状絶縁部材(35abc)のうちで前記高耐熱性チップ(25b)に面する部分(38b)は、前記共通の板状絶縁部材(35abc)のうちで前記パワー半導体チップ(10a)に面する前記部分(33a)に比べて厚い、請求項4に記載の半導体モジュール(1F)。
A heat-resistant chip (25b) which is provided on the predetermined surface (61) side of the heat sink (60) and has higher heat resistance than the power semiconductor chip (10a);
The common plate-like insulating member (35abc) also extends between the high heat resistant chip (25b) and the heat sink (60),
Of the common plate-like insulating member (35abc), the portion (38b) facing the high heat-resistant chip (25b) is formed of the power semiconductor chip (10a) among the common plate-like insulating member (35abc). The semiconductor module (1 F) according to claim 4, which is thicker than the portion (33 a) facing the substrate.
前記ヒートシンク(60)の前記所定面(61)の側に設けられており前記パワー半導体チップ(10a)に比べて耐熱性が高い高耐熱性チップ(25b)と、
前記高耐熱性チップ(25b)と前記ヒートシンク(60)との間に延在した別の板状絶縁部材(35b)と
を更に備え、
前記別の板状絶縁部材(35b)のうちで前記高耐熱性チップ(25b)に面する部分(38b)は、前記共通の板状絶縁部材(30ac)のうちで前記パワー半導体チップ(10a)に面する前記部分(33a)に比べて厚い、請求項4に記載の半導体モジュール(1G)。
A high heat resistant chip (25b) which is provided on the predetermined surface (61) side of the heat sink (60) and has higher heat resistance than the power semiconductor chip (10a);
And further comprising another plate-like insulating member (35b) extending between the high heat-resistant chip (25b) and the heat sink (60),
Of the other plate-like insulating member (35b), the portion (38b) facing the high heat-resistant chip (25b) is the power semiconductor chip (10a) of the common plate-like insulating member (30ac). The semiconductor module (1G) according to claim 4, wherein the semiconductor module (1G) is thicker than the portion (33a) facing the surface.
導電性を有するヒートシンク(60)と、
前記ヒートシンク(60)の所定面(61)の側に設けられたパワー半導体チップ(10a)と、
前記ヒートシンク(60)の前記所定面(61)の側に設けられており前記パワー半導体チップ(10a)に比べて耐熱性が高い高耐熱性チップ(25b)と、
前記パワー半導体チップ(10a)と前記ヒートシンク(60)との間に延在した板状絶縁部材(30a,30ac)と、
前記高耐熱性チップ(25b)と前記ヒートシンク(60)との間に延在した別の板状絶縁部材(35b)と
を備え、
前記別の板状絶縁部材(35b)のうちで前記高耐熱性チップ(25b)に面する部分(38b)は、前記板状絶縁部材(30a,30ac)のうちで前記パワー半導体チップ(10a)に面する部分(33a)に比べて厚い、半導体モジュール(1E,1G,1I)。
A conductive heat sink (60);
A power semiconductor chip (10a) provided on the predetermined surface (61) side of the heat sink (60);
A high heat resistant chip (25b) which is provided on the predetermined surface (61) side of the heat sink (60) and has higher heat resistance than the power semiconductor chip (10a);
Plate-like insulating members (30a, 30ac) extending between the power semiconductor chip (10a) and the heat sink (60);
Another plate-like insulating member (35b) extending between the high heat-resistant chip (25b) and the heat sink (60);
Of the another plate-like insulating member (35b), the portion (38b) facing the high heat-resistant chip (25b) is the power semiconductor chip (10a) of the plate-like insulating members (30a, 30ac). The semiconductor module (1E, 1G, 1I) is thicker than the portion (33a) facing the surface.
導電性を有するヒートシンク(60)と、
前記ヒートシンク(60)の所定面(61)の側に設けられたパワー半導体チップ(10a)と、
前記ヒートシンク(60)の前記所定面(61)の側に設けられており前記パワー半導体チップ(10a)に比べて耐熱性が高い高耐熱性チップ(25b)と、
前記パワー半導体チップ(10a)と前記ヒートシンク(60)との間に延在すると共に前記高耐熱性チップ(25b)と前記ヒートシンク(60)との間にも延在した共通の板状絶縁部材(35abc,35ab)と
を備え、
前記共通の板状絶縁部材(35abc,35ab)のうちで前記高耐熱性チップ(25b)に面する部分(38b)は、前記共通の板状絶縁部材(35abc,35ab)のうちで前記パワー半導体チップ(10a)に面する部分(33a)に比べて厚い、半導体モジュール(1F,1H,1J)。
A conductive heat sink (60);
A power semiconductor chip (10a) provided on the predetermined surface (61) side of the heat sink (60);
A high heat resistant chip (25b) which is provided on the predetermined surface (61) side of the heat sink (60) and has higher heat resistance than the power semiconductor chip (10a);
A common plate-like insulating member extending between the power semiconductor chip (10a) and the heat sink (60) and extending between the high heat resistant chip (25b) and the heat sink (60). 35abc, 35ab),
Of the common plate-like insulating members (35abc, 35ab), the portion (38b) facing the high heat-resistant chip (25b) is the power semiconductor among the common plate-like insulating members (35abc, 35ab). A semiconductor module (1F, 1H, 1J) thicker than the part (33a) facing the chip (10a).
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