JPWO2013084329A1 - Multiplexed communication system, transmitter, and receiver - Google Patents

Abstract

Provided are a multiplexed communication system, a transmission device, and a reception device that can reduce power consumption in signal transmission by a data transmission method at the time of transmission. When the state transition detection unit on the transmission side detects that the logical level is inverted from the logical level held in the transmission side state holding unit for each of a plurality of data, the detection result is multiplexed. Sent. On the receiving side, the logic level held in the receiving side state holding unit is inverted according to the received detection result. Data to be transmitted is limited to the detection result of logic level inversion. The amount of data to be transmitted can be limited, and power consumption during transmission can be reduced.

Description

  The present invention relates to a multiplexed communication system, a transmission apparatus, and a reception apparatus, and more particularly to a multiplexed communication system, a transmission apparatus, and a reception apparatus that reduce power consumption during data transmission.

  Conventionally, techniques for performing data communication have been disclosed. For example, when digital data is transmitted as a symbol with an arbitrary number of bits collected, a signal level representing the symbol at a certain symbol transmission timing is assigned to a signal level other than the signal level at the immediately preceding symbol transmission timing and encoded. Have been disclosed (Patent Document 1, etc.).

  Further, in the digital signal receiving device, reception is performed based on the difference between the absolute value of the difference between the current value and the previous value of the detected signal level and the predetermined value, and the level of the signal level between the current value and the previous value. What determines the rising and falling of a digital signal is disclosed (Patent Document 2 and the like).

JP 2004-80827 A JP-A-6-326566

  However, the technique exemplified in the above-mentioned Patent Document 1 provides a signal whose signal level always changes at adjacent symbol transmission timings in order to provide a transmission path encoding method and decoding method that do not continuously take the same signal level. To be transmitted. In order to change the signal level for each transmission, it is necessary to drive the transmission line with a different signal level, and the current consumption cannot be reduced.

  The technique exemplified in Patent Document 2 relates to waveform shaping of a dull signal that has propagated through a transmission path, and shapes the waveform by capturing the direction of transition of the signal level of the received signal. This is related to shaping a dull signal waveform, and there is no disclosure or suggestion about reducing the power consumption related to driving the transmission line during signal transmission, and there is a problem of reducing power consumption during signal transmission. It does not provide any solution.

  The present invention has been made in view of the above problems, and a multiplexing communication system, a transmission device, and a reception device that can reduce power consumption in signal transmission by a data transmission method at the time of transmission. The purpose is to provide.

  The multiplexed communication system according to claim 1 of the present application made in view of the above problems is a system that performs optical communication by multiplexing a plurality of data. On the transmission side, from each of a plurality of data, a transmission side state holding unit that holds a logical level for each synchronization cycle, and for each of a plurality of data, a logical level is held from the transmission side state holding unit A state transition detection unit that detects inversion and a multiplexing unit that multiplexes detection signals from the state transition detection unit are provided. On the receiving side, for each of a plurality of data, a receiving side state holding unit that holds a logic level, a restoring unit that restores a multiplexed signal, and a plurality of data corresponding to the restored detection signal And a control unit for inverting the logic level held in the state holding unit.

  Further, the multiplexed communication system according to claim 2 is the multiplexed communication system according to claim 1, wherein the light source of the optical communication is in a light emitting state at the time of transmitting a detection signal indicating that the multiplexed logic level is inverted. It is said.

  In addition, the multiplexed communication system according to claim 3 is the multiplexed communication system according to claim 1 or 2, wherein a timing unit that counts a predetermined number of synchronization cycles, a transmission-side state holding unit, and a state transition detection And a selection unit that selects one of the units. Each time the timing unit counts the predetermined number of cycles, the selection unit selects the transmission side state holding unit. The control unit holds the plurality of data restored by the restoration unit in the reception state holding unit.

  According to a fourth aspect of the present invention, there is provided a multiplex communication system that performs optical communication by multiplexing a plurality of data. For each of a plurality of data, a transmission side state holding unit that holds a logic level for each synchronization cycle, and for each of a plurality of data, the logic level is inverted from the logical level held in the transmission side state holding unit. A state transition detection unit to detect and a multiplexing unit to multiplex detection signals from the state transition detection unit are provided. On the receiving side, the logical levels of a plurality of stored data are inverted corresponding to the restored detection signal.

  The receiving apparatus according to claim 5 is provided in a multiplexed communication system that performs optical communication by multiplexing a plurality of data. A reception-side state holding unit that holds a logic level for each of a plurality of data, and a detection signal that detects an inversion of the logic level for each of the plurality of data, and restores the multiplexed and transmitted signal A restoration unit and a control unit that inverts the logic level held in the reception state holding unit for each of a plurality of data corresponding to the restored detection signal are provided.

  In the multiplexed communication system according to claim 1, the state transition detection unit on the transmission side detects that the logic level of each of a plurality of data is inverted from the logical level held in the transmission state holding unit. Then, the detection result is multiplexed and transmitted. On the receiving side, the logic level held in the receiving side state holding unit is inverted according to the received detection result.

  Thereby, instead of transmitting data for each synchronization cycle, a signal for informing the detection result of inversion is transmitted for the data whose logic level is inverted. When there is no logic level inversion, no data is transmitted, and the transmitted data is limited to only the detection result of the logic level inversion. For this reason, the amount of data to be transmitted can be limited, and power consumption during transmission can be reduced.

  In this case, the transmission of the signal indicating the detection result of the logic level inversion is set as the light emission state of the light source in the optical communication. As a result, the light source is in a light emitting state only when the logic level is inverted. Since the current flows in the light emitting state and power is consumed, the power consumption of the light source can be reduced. By reducing power consumption, heat generation of the light source is suppressed, and light emission characteristics and product life can be improved.

  In the multiplex communication system according to the third aspect of the present invention, a time counting unit is provided to time a predetermined number of synchronization cycles. When the predetermined number of cycles is counted, the selection unit on the transmission side selects the transmission side state holding unit instead of the state transition detection unit and transmits the logical level of each data, and the reception side state holding unit on the reception side Retained. As a result, the logical level of each data held in the receiving side state holding unit on the receiving side can be updated periodically. When the inversion of the logic level is detected on the transmitting side and the inversion of the logic level held in the receiving state holding unit is performed, the logic level cannot be detected even if the logic level is reversed. Is updated, the correct logic level can be held in the receiving-side state holding unit.

  Further, the transmission device according to claim 4 and the reception device according to claim 5 can constitute the multiplexed communication system described in the present application. The amount of data to be transmitted can be limited by transmitting only the detection result of the inversion of the logic level without transmitting the data without the inversion of the logic level, and the power consumption at the time of transmission can be reduced.

1 is a perspective view showing an electronic component mounting apparatus configured by arranging two electronic component mounting machines to which an electronic component supply apparatus is attached, and is an apparatus to which the multiplexed communication system of the present invention can be applied. . It is a top view which shows a part of tape feeder of the electronic component supply apparatus shown in FIG. 1, and the tape-ized components sent out by the tape feeder. It is a perspective view which shows the electronic component supply apparatus shown in FIG. It is sectional drawing which shows the tape feeder shown in FIG. It is a block diagram which shows the control apparatus with which the electronic component mounting machine shown in FIG. 1 is provided. It is a figure which shows the characteristic of the light emitting element used for optical communication. It is a block diagram which shows the apparatus with which a transmission side is equipped. It is a block diagram which shows the apparatus with which a receiving side is equipped. It is a circuit diagram which shows the specific example of counter B3. 10 is a timing chart showing the operation of the counter of FIG. 9. It is a circuit diagram which shows the specific example of state holding & transition extraction circuit B1 with which a transmission side is equipped. It is a figure which shows the selection result of selector B5 according to the mode signal MODE. It is a figure which shows the content of the packet produced | generated by the packet production | generation circuit B7 according to the mode signal MODE and transmission data D1, D2, ..., Dn. It is a circuit diagram which shows the specific example of frame synchronous circuit B23 with which a receiving side is equipped. It is a figure which shows the content of receiving data DR1, DR2, ..., DRn hold | maintained in state holding circuit B27 according to mode signal MODE and transmission data D1, D2, ..., Dn. It is a figure which illustrates the structure of the multiplexed data sequence transmitted by this embodiment.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. First, as an example to which the multiplexed communication system of the present application can be applied, the configuration of an electronic component mounting apparatus will be described with reference to FIGS. 1 to 5.

  FIG. 1 shows an electronic component mounting apparatus (hereinafter sometimes abbreviated as “mounting apparatus”) 10. The figure is a perspective view in which a part of the exterior component of the mounting apparatus 10 has been removed. The mounting apparatus 10 includes one system base 12 and two electronic component mounting machines (hereinafter, may be abbreviated as “mounting machines”) 16 arranged side by side adjacent to each other on the system base 12. In other words, the electronic component is mounted on the circuit board. In the following description, the direction in which the mounting machines 16 are arranged is referred to as an X-axis direction, and a horizontal direction perpendicular to the direction is referred to as a Y-axis direction.

  Each of the mounting machines 16 included in the mounting apparatus 10 mainly includes a mounting machine main body 24 configured to include a frame unit 20 and a beam unit 22 overlaid on the frame unit 20, and a circuit board in the X-axis direction. A transport device 26 that transports and fixes the set position at a set position, a mounting head 28 that mounts an electronic component on a circuit board fixed by the transport device 26, and an X-axis mounted head 28 disposed on the beam unit 22. A moving device 30 that moves in the direction and the Y-axis direction, and an electronic component supply device 32 that is disposed in front of the frame portion 20 and supplies electronic components to the mounting head 28 (hereinafter, may be abbreviated as “supply device”) 32 It has.

  The transport device 26 includes two conveyor devices 40 and 42, and the two conveyor devices 40 and 42 are parallel to each other and extend in the X-axis direction so that the central portion in the Y-axis direction of the frame portion 20. It is arranged. Each of the two conveyor devices 40 and 42 has a structure in which a circuit board supported by each conveyor device 40 and 42 is conveyed in the X-axis direction by an electromagnetic motor 44 (see FIG. 5). Furthermore, each of the conveyor devices 40 and 42 has a substrate holding device 46 (see FIG. 5), and is configured to hold the circuit board in a fixed position.

  The mounting head 28 mounts electronic components on the circuit board held by the transport device 26, and has a suction nozzle 50 that sucks the electronic components on the lower surface. The suction nozzle 50 communicates with negative pressure air and a positive pressure air passage via a positive / negative pressure supply device 52 (see FIG. 5), sucks and holds the electronic component with negative pressure, and is supplied with a slight positive pressure. In this way, the held electronic component is detached. Furthermore, the mounting head 28 includes a nozzle lifting device (see FIG. 5) 54 that lifts and lowers the suction nozzle 50 and a nozzle rotation device (see FIG. 5) 56 that rotates the suction nozzle 50 about its axis. It is possible to change the vertical position of the electronic component to be held and the holding posture of the electronic component. The suction nozzle 50 is attachable to and detachable from the mounting head 28, and can be changed according to the size and shape of the electronic component.

  The moving device 30 moves the mounting head 28 to an arbitrary position on the frame unit 20, an X-axis direction slide mechanism (not shown) for moving the mounting head 28 in the X-axis direction, and the mounting head. And a Y-axis direction slide mechanism (not shown) for moving 28 in the Y-axis direction. The Y-axis direction slide mechanism has a Y-axis slider (not shown) provided in the beam portion 22 so as to be movable in the Y-axis direction, and an electromagnetic motor (see FIG. 5) 64 as a drive source. The Y-axis slider can be moved to an arbitrary position in the Y-axis direction by the electromagnetic motor 64. The X-axis direction slide mechanism has an X-axis slider 66 provided on the Y-axis slider so as to be movable in the X-axis direction, and an electromagnetic motor (see FIG. 5) 68 as a drive source. The motor 68 enables the X-axis slider 66 to move to an arbitrary position in the X-axis direction. The mounting head 28 is attached to the X-axis slider 66, so that the mounting head 28 can be moved to an arbitrary position on the frame unit 20 by the moving device 30. The mounting head 28 can be attached to and detached from the X-axis slider 66 with a single touch, and can be changed to a different type of work head, such as a dispenser head.

  The supply device 32 is disposed at the front end of the frame portion 20 as a base, and is a feeder-type supply device. The supply device 32 accommodates a taped part 70 (see FIG. 2) in which electronic parts are taped and accommodated in a state where the taped part 70 is wound around a reel 72, and is accommodated in each of the plurality of tape feeders 74. And a plurality of delivery devices (see FIG. 5) 75 for feeding out the taped component 70, and the electronic components are sequentially supplied from the taped component 70 to the supply position to the mounting head 28. .

  As shown in FIG. 2, the taped component 70 includes a carrier tape 82 in which a large number of receiving recesses 78 and feed holes 80 are formed at an equal pitch, an electronic component 84 received in the receiving recess 78, and a carrier tape 82. The top cover tape 86 covers the housing recess 78 in which the electronic component 84 is housed. On the other hand, as shown in FIG. 3, the tape feeder 74 has a reel holding portion 88 for holding a reel 72 around which the taped component 70 is wound, and a taped component 70 drawn out from the reel 72 on the upper end surface. It is composed of a feeder main body 90 that is extended.

  As shown in FIG. 4, a sprocket 92 that engages with a feed hole 80 formed in the carrier tape 82 of the taped component 70 is built in the feeder main body 90, and the sprocket 92 is rotated. The taped component 70 with the top cover tape 86 attached to the carrier tape 82 is sent out in the direction away from the reel 72 on the upper end surface of the feeder main body 90. Then, when the top cover tape 86 is peeled off from the carrier tape 82 by a peeling device (not shown), the accommodation recesses 78 in which the electronic components 84 are accommodated are sequentially released at the tip of the upper end surface of the feeder main body 90. The electronic component 84 is taken out by the suction nozzle 50 from the opened accommodation recess 78.

  The tape feeder 74 is detachably attached to a tape feeder mounting base (hereinafter, may be abbreviated as “mounting base”) 100 fixedly provided at the front end of the frame portion 20. The mounting base 100 includes a slide portion 102 provided on the upper surface of the frame portion 20 and a standing surface portion 106 erected on an end portion of the slide portion 102 on the side close to the conveying device 26. A plurality of slide grooves 108 are formed in the slide portion 102 so as to extend in the Y-axis direction, and the lower edge portion of the feeder main body 90 of the tape feeder 74 is fitted into each of the plurality of slide grooves 108. It is possible to slide in the state. And the side wall surface by the side of the sending direction which is the sending direction of the taped component 70 of the feeder main body 90 is made to slide in the direction which approaches the standing surface part 106 in the state which fitted the lower edge part of the feeder main body 90. 110 is attached to the standing surface portion 106. As a result, the tape feeder 74 is mounted on the mounting table 100.

  The standing surface portion 106 is provided with a plurality of connector connecting portions 112 corresponding to the plurality of slide grooves 108. On the other hand, the connector 114 is provided on the side wall surface 110 of the tape feeder 74 attached to the standing surface portion 106, and when the side wall surface 110 of the tape feeder 74 is attached to the standing surface portion 106, the connector 114 is connected to the connector 114. The connection unit 112 is connected. Further, a pair of upright pins 116 are provided on the side wall surface 110 of the tape feeder 74 so as to sandwich the connector 114 in the vertical direction, and the connector connection portion 112 of the upright surface portion 106 of the mounting base 100 is connected in the vertical direction. Are fitted into a pair of fitting holes 118 formed so as to be sandwiched between the two.

  Moreover, as shown in FIG. 4, the cover 120 is provided in the upper part of the mounting base 100 so that opening and closing is possible. The cover 120 is attached to the end portion on the front side of the beam portion 22 of the mounting machine 16 so as to be rotatable about an axis extending in the X-axis direction, and the closed position covering the mounting table 100 and the mounting table 100 are opened. It is possible to rotate between the open position. When the cover 120 is closed while the tape feeder 74 is mounted on the mounting base 100, the feeder main body 90 of the tape feeder 74 that is mounted is covered by the cover 120.

  A display portion 124 provided with three display lamps 122 (only one is shown in the figure) is attached to the lower end portion of the cover 120, and the tape feeder 74 is attached to the attachment base 100. When the cover 120 is closed in this state, the display unit 124 is positioned above the feeder main body 90. A plurality of display units 124 are provided corresponding to the plurality of slide grooves 108, and the display lamps 122 of the plurality of display units 124 are turned on when the tape feeder 74 is mounted on the mounting base 100, It is used as a guide to which of the plurality of slide grooves 108 the tape feeder 74 should be attached.

  The mounting machine 16 includes a mark camera (see FIG. 5) 130 and a parts camera (see FIGS. 1 and 5) 132. The mark camera 130 is fixed to the lower surface of the X-axis slider 66 so as to face downward, and is moved by the moving device 30 so that the surface of the circuit board can be imaged at an arbitrary position. Yes. On the other hand, the parts camera 132 is provided between the transport device 26 of the frame unit 20 and the supply device 32 in a state of facing upward, and images the electronic component sucked and held by the suction nozzle 50 of the mounting head 28. It is possible. The image data obtained by the mark camera 130 and the image data obtained by the parts camera 132 are processed by the image processing device 134 (see FIG. 5), and information on the circuit board, the holding position of the circuit board by the board holding device 46. An error, a holding position error of the electronic component by the suction nozzle 50, and the like are acquired.

  Furthermore, the mounting machine 16 includes a control device 140 as shown in FIG. The control device 140 includes a controller 142 mainly composed of a computer having a CPU, ROM, RAM and the like, the electromagnetic motors 44, 64, 68, the substrate holding device 46, the positive / negative pressure supply device 52, the nozzle lifting / lowering device 54, the nozzle rotation. A plurality of drive circuits 144 corresponding to each of the device 56 and the delivery device 75 and a plurality of control circuits 146 corresponding to each of the plurality of display lamps 122 provided in the plurality of display units 124 are provided. The controller 142 is connected to a drive source such as a transfer device or a moving device via each drive circuit 144, and can control the operation of the transfer device, the moving device, or the like. The controller 142 is connected to a plurality of display lamps 122 via each control circuit 146, and each of the plurality of display lamps 122 can be lit up in a controllable manner. The plurality of display units 124 may be provided with various switches (not shown), and various control signals accompanying switch inputs are sent to the control circuits 146. Further, an image processing device 134 that processes image data obtained by the mark camera 130 and the part camera 132 is connected to the controller 142.

  With the above-described configuration, the mounting machine 16 can perform an electronic component mounting operation with the mounting head 28 on the circuit board held by the transport device 26. More specifically, the circuit board is first transported to the mounting work position by the transport device 26, and the circuit board is fixedly held at that position. Next, the mounting device 28 is moved onto the circuit board by the moving device 30, and the circuit board is imaged by the mark camera 130. By the imaging, the type of the circuit board and the holding position error of the circuit board by the transfer device 26 are acquired. An electronic component corresponding to the acquired type of circuit board is supplied by the tape feeder 74 of the supply device 32, and the mounting head 28 is moved by the moving device 30 to the supply position of the electronic component. Thereby, the electronic component is sucked and held by the suction nozzle 50 of the mounting head 28.

  Subsequently, the mounting head 28 holding the electronic component is moved onto the parts camera 132 by the moving device 30, and the electronic component held by the mounting head 28 is imaged by the parts camera 132. The holding position error of the electronic component is acquired by the imaging. The moving device 30 moves the mounting head 28 to the mounting position on the circuit board, and the mounting head 28 rotates the mounting nozzle 50 based on the holding position error between the circuit board and the electronic component. Installed.

  The multiplexed communication system of the present application can be applied to an electronic component mounting apparatus, an electronic component mounting apparatus exemplified in the electronic component mounting apparatus 10 described above, or an automatic machine that operates in various other production lines. It is a possible system. As described above, in the electronic component mounting apparatus 10, various data are transmitted from the control device 140 to various electromagnetic motors 44, 64, 68 (see FIG. 5), other movable devices, and the display lamp 122. These devices are controlled. The control device 140 receives various data (not shown) from the mark camera 130, the parts camera 132, various electromagnetic motors 44, 64, 68, other movable devices, the display unit 124, and the like for control. Provide.

  Specifically, operation command data is sent from each drive circuit 144 of the control device 140 to the various electromagnetic motors 44, 64, 68 and other movable devices to perform drive control. Further, lighting control data is sent from the control circuit 146 of the control device 140 to the display lamp 122 to perform lighting control. On the other hand, the control device 140 receives image data from the mark camera 130 and the parts camera 132, and receives device information data such as torque information and position information from various electromagnetic motors 44, 64, 68 and other movable devices. Various input data are received from sensors (not shown) or the like (not shown) provided in each device.

  In a multiplexed communication system, a transmission device, and a reception device in which such various data transmission is performed by optical communication, a light emitting element such as a laser diode is provided on the transmission side. FIG. 6 shows the characteristics of such a light emitting element. The light emitting element generally emits light by current driving, and has a characteristic that the light output increases as the amount of current increases. If the light emission state is set when the logical value is high, the drive current of the light emitting element becomes large at the high logical value. The light emitting element generates heat when a driving current flows, and there is a risk that the element characteristics may be deteriorated due to a temperature rise due to the heat generation. In order to reduce the temperature of the light emitting device during actual use, measures such as lowering the drive current value, lowering the ambient temperature, and designing heat dissipation can be considered, but reducing the drive current value causes a decrease in light output. In addition, a decrease in ambient temperature and an increase in cost due to heat radiation design are also conceivable.

  In the following embodiments, for various data to be transmitted, the fact that the logical value of the data has transitioned is transmitted, so that the amount of transmission is compressed to reduce power consumption in the light emitting element during transmission, and the temperature of the light emitting element A multiplexing communication system, a transmission apparatus, and a reception apparatus suitable for suppressing the increase and improving the element lifetime will be described.

  FIG. 7 is a block diagram showing an apparatus provided on the transmission side. Each block operates in synchronization with the clock signal CLK. In the electronic component mounting apparatus 10 in the operating state, operation command data and lighting control data transmitted from the control device 140 to the outside, and input data exemplified as image data and device information data transmitted to the control device 140 DT1, DT2,..., DTn are divided into two. One of them is input to the state holding & transition extraction circuit B1, and the other is directly input to the selector B5. The state holding & transition detection circuit B1 detects whether or not the logical value of each data has changed and inverted. When the logical value transitions, high level transition detection signals DT1S, DT2S,..., DTnS are output to the selector B5. Further, a counter B3 for counting the number of clocks of the clock signal CLK is provided. The counter B3 outputs a high level mode signal MODE for every predetermined number of cycles. The mode signal MODE is input to the selector B5.

  The selector B5 selects any one of the transition detection signals DT1S, DT2S,..., DTnS and the input data DT1, DT2,. Specifically, the transition detection signals DT1S, DT2S,..., DTnS are selected in the low-level mode signal MODE (MODE = 0) until the counter B3 counts the predetermined number of cycles, and the predetermined number of cycles is counted. , DTn is selected in the high level mode signal MODE (MODE = 1) for informing the user. The selected data is sent as transmission data D1, D2,..., Dn to the packet generation circuit B7. In addition, the selection result by selector B5 demonstrated above is shown in FIG.

  Further, a fixed pattern synchronization frame is input to the packet generation circuit B7. The synchronization frame is a bit string for recognizing the head of the packet on the receiving side, and is generated by the synchronization frame generation circuit B9.

  In the packet generation circuit B7, the synchronization frame, the mode signal MODE, and the transmission data D1, D2,..., Dn are multiplexed to generate a transmission packet. While the count value of the counter B3 is less than the predetermined number of cycles, the low level mode signal MODE is output, and the transition detection signals DT1S, DT2S,..., DTnS are selected as the transmission data D1, D2,. Is done. Information on the input data DT1, DT2,..., DTn having a logical value transition is transmitted. When the count value of the counter B3 reaches a predetermined number of cycles, a high-level mode signal MODE is output, and the input data DT1, DT2,..., DTn are transmitted as transmission data D1, D2,. Selected. The logical value of each input data DT1, DT2,..., DTn is transmitted.

  Further, when the mode signal MODE and the transmission data D1, D2,..., Dn are both at the low level, no packet is generated. In the low level mode signal MODE, transition detection signals DT1S, DT2S,..., DTnS are selected as transmission data D1, D2,. In this case, since the transition detection signals DT1S, DT2S,..., DTnS are all at the low level, all the input data DT1, DT2,. Indicates that no data is available. In this case, since it is not necessary to perform data transmission again, no packet is generated. Thereby, unnecessary packet transmission is suppressed and unnecessary power consumption in the light emitting element is reduced. The contents of the generated packet in the packet generating circuit B7 described above are listed in FIG.

  FIG. 8 is a block diagram showing an apparatus provided on the receiving side. First, the clock synchronization circuit B21 detects the clock synchronization for the transmitted bit string and extracts the recovered clock signal RCLK. Each block operates in synchronization with the reproduction clock signal RCLK.

  The received bit string is input to the frame synchronization circuit B23 to detect a synchronization frame. Thereby, the head of the packet is recognized. The mode signal MODE and transmission data D1, D2,..., Dn are extracted from the recognized packet and stored in the register B25. The transmission data D1, D2,..., Dn are output together with the mode signal MODE toward the state holding circuit B27 provided for each data. The state holding circuit B27 determines the contents of the transmission data D1, D2,..., Dn according to the mode signal MODE, and rewrites and controls the contents of the state holding circuit B27.

  Specifically, in the low level mode signal MODE, the transmission data D1, D2,..., Dn are transition detection signals DT1S, DT2S,. In this case, the contents of the state holding circuit B27 corresponding to the high level transmission data D1, D2,..., Dn are inverted. Further, in the high-level mode signal MODE, the transmission data D1, D2,..., Dn are input data DT1, DT2,. In this case, the contents of all the state holding circuits B27 are rewritten to the received input data DT1, DT2,... DTn. As a result, the received data DR1, DR2,..., DRn output from the state holding circuit B27 coincides with the input data DT1, DT2,... DTn, and the state holding circuit B27 is set correctly. FIG. 15 shows the contents of the reception data DR1, DR2,..., DRn held in the state holding circuit B27 described above.

  Here, a specific example of each block in the block diagrams (FIGS. 7 and 8) showing devices provided on the transmission side and the reception side will be exemplified.

  FIG. 9 is a specific circuit example of the counter B3 provided on the transmission side, and FIG. 10 is a timing chart relating to the count operation. The three-stage D-type flip-flops D-FF0 to D-FF2 have a serial connection configuration in which the output from the BQ terminal (BQ) in the previous stage is connected to the clock terminal (CLK) in the subsequent stage. Output signals Q0 to Q2 from the Q terminals (Q) of the D-type flip-flops D-FF0 to D-FF2 are input to the AND gate AND1, and a mode signal MODE is output as the logical product of the output signals Q0 to Q2. The Each stage is operated by a clock signal CLK and sequentially counts the number of clocks. In the configuration illustrated in FIG. 9, the predetermined count value at which the high-level mode signal MODE is output is 8 cycles.

  FIG. 11 is a specific circuit example of the state holding & transition extraction circuit B1 provided on the transmission side. Input data DT1, DT2,..., DTn (denoted as “DTx” in FIG. 11) are input to one input terminal of the AND gates AND2, AND3 and the exclusive OR gate XOR1. Here, the logical product is inverted and input to the AND gate AND3. The output terminals of the AND gates AND2 and AND3 are connected to the set terminal (S) and the reset terminal (R) of the RS flip-flop circuit SR-FF, respectively. The Q output terminal (Q) of the RS flip-flop circuit SR-FF is connected to the other input terminal of the exclusive OR gate XOR1. The output terminal of the exclusive OR gate XOR1 is connected to the other input terminal of the AND gates AND2 and AND3. Transition detection signals DT1S, DT2S,..., DTnS (denoted as “DTxS” in FIG. 11) are output from the output terminal of the exclusive OR gate XOR. The AND gates AND2 and AND3, and the RS flip-flop circuit SR-FF are circuits that hold the state, and the exclusive OR gate XOR1 is a circuit that performs transition detection.

  Here, although not shown in the figure, it is assumed that new input data DTx is taken in response to the clock signal CLK. When new input data DTx is fetched, coincidence detection is performed with the input data DTx held in the RS flip-flop circuit SR-FF in the exclusive OR gate XOR1. If they do not match, it is determined that the bit value has transitioned, and a high-level transition detection signal DTxS is output from the exclusive OR gate XOR1. Further, since the high-level transition detection signal DTxS is input to the AND gates AND2 and 3, the RS flip-flop circuit SR-FF is set or reset according to the logical value of the newly input data DTx. . The RS flip-flop circuit SR-FF is rewritten to the logical value of the input data DTx and held. Specifically, when high-level input data DTx is input, the RS flip-flop circuit SR-FF is set via the AND gate AND2, and the high-level ethical value is held. When the low level input data DTx is input, the RS flip-flop circuit SR-FF is reset via the AND gate AND3 and the low level logical value is held.

  FIG. 14 is a specific circuit example of the frame synchronization circuit B23 provided on the receiving side. A shift register including D-type flip-flops DFF connected in multiple stages is provided. The transmitted packets are sequentially stored in the shift register. Among the shift registers, a group of D-type flip-flops DFF corresponding to the head of the packet in which the synchronization frame is arranged is connected to the synchronization frame detection circuit B41. A mode signal MODE and transmission data D1, D2,..., Dn are arranged at the subsequent stage of the packet. A group of D-type flip-flops DFF corresponding to these data is connected to one input terminal of the AND gate. The other input terminal of the AND gate is connected to the output terminal of the synchronization frame detection circuit B41.

  In response to the detection of the synchronization frame by the synchronization frame detection circuit B41, the mode signal MODE and transmission data D1, D2,..., Dn are taken in via the AND gate.

  FIG. 16 illustrates the configuration of the data string transmitted according to this embodiment. In FIG. 16, the process according to the change of the logical value in 12 cycles is illustrated about three input data DTa, DTb, and DTc. The mode signal MODE is assumed to be at the high level in the first cycle, and at the same time, the low level is maintained.

  The logical value of the input data DTa changes in the fifth, eighth, and eleventh cycles. Therefore, the transition detection signal DTaS becomes high level in the fifth, eighth, and eleventh cycles, and is maintained at low level in the other cycles. The input data DTb transitions in logic value in the third, fourth, seventh, eighth, and eleventh cycles. Therefore, the transition detection signal DTbS becomes high level in the third, fourth, seventh, eighth, and eleventh cycles, and is maintained at low level in the other cycles. In addition, the logical value of the input data DTc changes in the fourth cycle. Therefore, the transition detection signal DTcS becomes high level in the fourth cycle and is maintained at low level in the other cycles.

  As for the transmission data, the selector B5 selects the input data DTa, DTb, DTc for the high level mode signal MODE, and the transition detection signals DTaS, DTbS, DTcS for the low level mode signal MODE. Therefore, as shown in the figure, the multiplexed transmission data is multiplexed with the logical values (states) of the input data DTa, DTb, and DTc in the first cycle in which the mode signal MODE is at a high level. Since the mode signal MODE is at the low level after the second cycle, the logical values (transition information) of the transition detection signals DTaS, DTbS, and DTcS are multiplexed. In this case, in the second, sixth, ninth, tenth, and twelfth cycles, the input data DTa, DTb, and DTc have no logic transition, and the transition detection signals DTaS, DTbS, and DTcS are all at the low level. Therefore, in these cycles, no packet is generated and data transmission is not performed.

  As described in detail above, according to this embodiment, the state holding & transition detection circuit B1 on the transmission side causes the logic level to be held and transitioned for each of the input data DT1, DT2,. When it is detected that the logic level held in the detection circuit B1 is inverted, transition detection signals DT1S, DT2S,..., DTnS are output and transmitted as detection results. On the receiving side, the logic level held in the state holding circuit B27 according to the contents of the transmission data D1, D2,..., Dn in which the contents of the transition detection signals DT1S, DT2S,. Invert.

  Instead of transmitting data for each cycle of the clock signal CLK, the inversion detection result is notified for data whose logic level is inverted, and data is not transmitted when there is no inversion. Further, if the bit values of all input data DT1, DT2,..., DTn do not transition, transmission for generating a packet is not performed. The amount of data to be transmitted can be limited, and power consumption during transmission can be reduced.

  In optical communication, the frequency with which a light emitting light source enters a light emitting state can be reduced, the power consumption of the light source is reduced, the temperature rise of the light emitting element is suppressed, and the element characteristics and the product life of the element are improved. Can do.

  Further, the counter B3 counts the number of cycles of the clock signal CLK, and sets the mode signal MODE to the high level every predetermined cycle. Then, the logical value of the input data DT1, DT2,... DTn is transmitted in the high level mode signal MODE to update the reception-side state holding circuit B27. Since the logical value of each data held in the state holding circuit B27 can be updated periodically, the logical value of the held data can be correctly held.

  Here, in the state holding & transition extraction circuit B1, the AND gates AND2 and AND3 and the RS flip-flop circuit SR-FF are examples of a transmission side state holding unit, and the exclusive OR gate XOR1 is a state transition detection unit. It is an example. The counter B3 is an example of a time measuring unit, the selector B5 is an example of a selection unit, and the packet generation circuit B7 is an example of a multiplexing unit. The frame synchronization circuit B23 is an example of a restoration unit, and the state holding circuit B27 is an example of a reception side state holding unit. Further, the process illustrated in FIG. 15 is an example of the process performed by the control unit.

Needless to say, the present invention is not limited to the above-described embodiment, and various modifications and changes can be made without departing from the spirit of the present invention.
For example, in the present embodiment, a case has been described in which transition detection signals DT1S, DT2S,..., DTnS that are detected to have transitioned after detecting transitions of logical values for all input data are transmitted. Is not limited to this. When a plurality of signals are multiplexed and transmitted, the signal to be transmitted can be changed in a manner that reduces the frequency of the high level (logical value that becomes the light emission state of the light source) in the multiplexed state. For example, for input data whose logic value frequently changes, it can be set to transmit input data instead of transmitting a transition detection signal that detects a transition.
In this embodiment, the transition detection signals DT1S, DT2S,..., DTnS that are output when the transition of the logical value is detected are set to the high level. This is based on the premise that the device is in a light emitting state and consumes a large amount of power. The present invention is not limited to this, and other settings can be used as long as the power consumption of the light emitting element during transmission is suppressed. For example, in a transmission system that consumes a large amount of power when transmitting a low level, it may be set to output a low level signal as a transition detection signal.

  DESCRIPTION OF SYMBOLS 10: Electronic component mounting apparatus 44, 64, 68: Electromagnetic motor 122: Display lamp 124: Display part 130: Mark camera 132: Parts camera 140: Control apparatus B1: State holding & transition extraction circuit B3: Counter B5: Selector B7: Packet generation circuit B9: frame generation circuit for synchronization B21: clock synchronization circuit B23: frame synchronization circuit B25: register B27: state holding circuit B41: frame detection circuit for synchronization CLK: clock signals D1, D2,..., Dn: transmission Data DT1, DT2, ..., DTn, DTa, DTb, DTc, DTx: Input data DT1S, DT2S, ..., DTnS, DTaS, DTbS, DTcS, DTxS: Transition detection signal MODE: Mode signal RCLK: Regenerated clock signal

Claims (5)

A multiplexing communication system for performing optical communication by multiplexing a plurality of data,
On the sending side,
For each of the plurality of data, a transmission side state holding unit that holds a logic level for each synchronization cycle;
For each of the plurality of data, a state transition detection unit that detects that the logic level is inverted from the logic level held in the transmission-side state holding unit;
A multiplexing unit that multiplexes detection signals from the state transition detection unit,
On the receiving side,
For each of the plurality of data, a receiving state holding unit that holds a logic level;
A restoration unit for restoring the multiplexed signal;
A multiplexing communication system, comprising: a control unit that inverts a logic level held in the reception-side state holding unit for the plurality of data corresponding to the restored detection signal. 2. The multiplexed communication system according to claim 1, wherein, in the optical communication of the multiplexed detection signal, a light source used for the optical communication is set in a light emitting state in response to transmission of the detection signal. . A time measuring unit for measuring a predetermined number of cycles of the synchronization cycle;
On the transmission side, comprising a selection unit that selects one of the transmission side state holding unit and the state transition detection unit,
Each time the timing unit counts a predetermined number of cycles, the selection unit selects the transmission side state holding unit, and the control unit stores the plurality of data restored by the restoration unit in the reception side state holding unit. The multiplexed communication system according to claim 1, wherein the multiplexed communication system is held. A transmission apparatus provided in a multiplexed communication system that performs optical communication by multiplexing a plurality of data,
For each of the plurality of data, a transmission side state holding unit that holds a logic level for each synchronization cycle;
For each of the plurality of data, a state transition detection unit that detects that the logic level is inverted from the logic level held in the transmission-side state holding unit;
A multiplexing unit that multiplexes detection signals from the state transition detection unit,
On the receiving side, a transmission apparatus characterized by inverting the logic levels of the plurality of data held corresponding to the restored detection signal. A receiving apparatus provided in a multiplexed communication system that performs optical communication by multiplexing a plurality of data,
For each of the plurality of data, a receiving state holding unit that holds a logic level;
A restoration signal that detects a logical level inversion for each of the plurality of data, and restores the multiplexed and transmitted signal; and
A receiving apparatus comprising: a control unit that inverts a logic level held in the receiving-side state holding unit for each of the plurality of data corresponding to the restored detection signal.

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