JPWO2013080289A1 - Signal processing apparatus and signal processing method - Google Patents

Abstract

The signal processing device includes an arithmetic control unit that controls timing of arithmetic processing executed by the arithmetic unit, and data that is subject to the arithmetic processing so that the arithmetic processing unit can load the data subject to the arithmetic processing. A transfer control unit that controls timing for transfer.

Description

  The present invention relates to a signal processing apparatus.

  In the field of mobile communication, new communication methods are standardized one after another and put into practical use. When a new communication method is put into practical use, the current communication method is gradually switched to a new communication method. Therefore, in a transition period from the current communication method to a new communication method, a plurality of communication methods may be supported by one mobile terminal.

  When a plurality of communication methods are supported by one mobile terminal, it is conceivable to prepare dedicated hardware for each communication method. However, the method of preparing dedicated hardware for each communication method increases the circuit scale of the mobile terminal. If the circuit scale of the mobile terminal increases, problems such as an increase in cost and an increase in power consumption may occur.

  In addition, when the standardization standard is updated, it is necessary to make the mobile terminal flexibly correspond to the updated standard. The method of preparing dedicated hardware for each communication method cannot quickly respond to the updated standard.

  For the above reasons, it is desired to support a plurality of communication schemes with a single mobile terminal using software-defined radio (SDR). Software-defined radio is a software implementation of a communication method. Specifically, the wireless device is configured such that wireless processing can be realized using a processor program, rewritable logic, or the like. By realizing the software defined radio, it is possible to switch the communication method by changing the software without changing the hardware.

  As a method for realizing a radio (radio) by software, there are a method using a processor and a method using reconfigurable hardware. When implementing a wireless device with software, it is easier to implement with a processor whose development method is general, and therefore, a method using a processor has become the mainstream. By using reconfigurable hardware, the hardware configuration is dynamically reconfigured at runtime.

  On the other hand, the transmission rate required by recent wireless communication systems is very high. As the transmission rate is increased, the arithmetic processing performance required for the portable terminal is also very high. Recent wireless communication systems include a wireless communication system that employs an OFDM (Orthogonal Frequency Division Multiplex) system, represented by the LTE (Long Term Evolution) system. In a wireless communication system employing the OFDM system, a large number of wireless resources deployed in the frequency direction and the time direction are prepared, thereby improving the overall transmission rate.

  A process that realizes a wireless communication system such as the OFDM system requires almost no complicated control, and a configuration capable of efficiently executing simple process repetition is suitable. Here, the complicated control includes branch processing using the calculation result.

  Further, as one method for improving the calculation performance, there is a method in which a plurality of instructions are combined into one instruction having a long word length and executed simultaneously. For example, there is a technique using VLIW (Very Long Instruction Word). VLIW is a type of processor architecture, and is a method in which a plurality of functions are prepared and instructions for operating each function are combined into one instruction and executed as one instruction having a long word length.

  Regarding a signal processing device, there is known a signal processing device that can suppress a rapid increase in circuit scale even if the degree of parallelism of arithmetic units is increased (see, for example, Patent Document 1).

JP 2011-141791 A

  In the method using VLIW, there are many cases where there is no direct causal relationship between a plurality of combined instructions. In the method using the VLIW, there is a problem that execution of a certain instruction is hindered by a stall caused by another instruction not having a causal relationship with the certain instruction as a result of the combined instructions being executed almost simultaneously. is there. Stall means that the process is stopped for some reason. For example, when the cycle time of the processor is different from the cycle time of the memory, the operation of the device having an early cycle time may stop (stall). If the memory cycle time is slower than the processor cycle time, the processor operation stops.

  Specifically, a load (LOAD) instruction and an operation (OPERATION) instruction are executed substantially simultaneously, and when the load instruction is stalled, the operation instruction is also stalled under the influence of the stall.

  FIG. 1 shows an example of a time chart of processing using VLIW. In FIG. 1, the horizontal axis represents time. For example, the horizontal axis is represented by “cycle”. In FIG. 1, (1) to (10) are attached corresponding to each cycle. FIG. 1 shows a case where the loaded data is used to execute the operation 1-1 (OP1-1). That is, the loaded data is not directly used for the execution of the operation 1-2 (OP1-2) and the operation 1-3 (OP1-3).

  In cycle (1), a process of loading data 1 (data1) is executed (LD1).

  In cycle (2), operation 1-1 is executed using data 1 loaded in cycle (1).

  In cycle (3), operation 1-2 is executed.

  In cycle (4), a process of loading data 2 (data2) is executed (LD2) and operation 1-3 is executed.

  In cycle (5), operation 1-1 is executed using data 2 loaded in cycle (4).

  In cycle (6), operation 1-2 is executed.

  In cycle (7), the process of loading data 3 (data3) is executed (LD3), and operation 1-3 is executed.

  In cycle (8), operation 1-1 is executed using data 3 loaded in cycle (7).

  In cycle (9), operation 1-2 is executed.

  In cycle (10), the process of loading data 4 is executed (LD4), and operation 1-3 is executed.

  In the example shown in FIG. 1, both the load process and the arithmetic process are executed in one cycle. In FIG. 1, no stall occurs.

  FIG. 2 shows an example (part 2) of a time chart of processing using VLIW. In FIG. 2, the horizontal axis represents time. For example, the horizontal axis is represented by “cycle”. In FIG. 2, (1)-(14) are attached corresponding to each cycle. FIG. 2 shows a case where the loaded data is used to execute the operation 1-1 (OP1-1). That is, when operation 1-2 (OP1-2) and operation 1-3 (OP1-3) are executed, the loaded data is not directly used.

  In cycle (1) and cycle (2), data loading is executed in two cycles (LD1). A stall occurs during one cycle of the first half of the two cycles in which data loading is executed. That is, one cycle stall occurs when reading data from the memory.

  In cycle (3), operation 1-1 is executed using data 1 (data1) read in cycle (2).

  In cycle (4), operation 1-2 is executed.

  In cycle (5) and cycle (6), data loading is executed in two cycles (LD2). Further, in cycle (5) and cycle (6), operation 1-3 is executed in two cycles. However, a stall has occurred during the first half of the two cycles in which data loading is executed, so a stall has occurred during the first half of the two cycles in which operation 1-3 is executed. Yes. Basically, an operation instruction can be executed in one cycle when necessary data is available. However, due to the influence of a stall that occurs when data is loaded, a stall also occurs in operation 1-3, resulting in two cycles.

  In cycle (7), operation 1-1 is executed using data 2 read in cycle (6).

  In cycle (8), operation 1-2 is executed.

  In cycle (9) and cycle (10), data loading is executed in two cycles (LD3). Further, in cycle (9) and cycle (10), operation 1-3 is executed in two cycles. However, a stall has occurred during the first half of the two cycles in which data loading is executed, so a stall has occurred during the first half of the two cycles in which operation 1-3 is executed. Yes.

  In cycle (11), operation 1-1 is executed using data 3 read in cycle (10).

  In the cycle (12), the operation 1-2 is executed.

  In cycle (13) and cycle (14), data loading is executed in two cycles (LD4). Further, in cycle (13) and cycle (14), operation 1-3 is executed in two cycles. However, a stall has occurred during the first half of the two cycles in which data loading is executed, so a stall has occurred during the first half of the two cycles in which operation 1-3 is executed. Yes.

  In the example shown in FIG. 2, before the data loaded by the load instruction is overwritten by the subsequent load instruction, it is necessary to describe the program so that the operation instruction using the data is executed. is there. Specifically, before the data loaded in cycle (2) is overwritten by the data loaded in cycle (6), an arithmetic instruction using the data loaded in cycle (2) is executed. There is a need. That is, it is necessary to strictly define the timing at which transfer instructions and arithmetic instructions are executed. This is because the transfer instruction and the operation instruction influence each other. In the example shown in FIG. 2, stalls can occur frequently, so it is difficult to write a program so as to avoid the occurrence of stalls.

  Further, if the calculation efficiency decreases due to the occurrence of a stall, a lot of hardware is required to realize the same processing amount. When a lot of hardware is used, there arises a problem that the circuit scale and power consumption increase.

  It is an object of the disclosed signal processing apparatus to independently control a load instruction and an operation instruction.

A signal processing apparatus according to an embodiment of the disclosure includes:
An arithmetic control unit that controls the timing of arithmetic processing executed by the arithmetic unit;
A transfer control unit that controls timing for transferring the data to be subjected to the arithmetic processing so that the data to be subject to the arithmetic processing can be loaded by the arithmetic unit.

  According to the disclosed signal processing apparatus, the load instruction and the operation instruction can be controlled independently.

An example of the time chart of the process using VLIW is shown. An example of the time chart of the process using VLIW is shown. It is a figure which shows one Example of a portable terminal. It is a figure which shows one Example of a demodulation part. It is a figure which shows one Example of a signal processing apparatus. It is a time chart (the 1) which shows one Example of operation | movement of a signal processing apparatus. It is a time chart (the 2) which shows one Example of operation | movement of a signal processing apparatus. It is a time chart which shows an example of operation | movement of a signal processing apparatus. It is a flowchart which shows one Example of operation | movement of a signal processing apparatus. It is a flowchart which shows one Example of operation | movement of a signal processing apparatus. It is a figure which shows the effect by one Example of a signal processing apparatus. It is a figure which shows the modification of a signal processing apparatus.

DESCRIPTION OF SYMBOLS 100 Portable terminal 102 Radio | wireless part 104 L1 process part 106 L2 process part 108 Communication control CPU
110 Application CPU
112 User Interface Circuit 142 Demodulator 144 Decoder 146 Encoder 148 Modulator 202 RF Interface 204 Bus Interface 206 ₁ -206 ₃ DSP
208 ₁ -208 ₂ Accelerator 210 Memory 212 Bus 302 Transfer control unit 304 Data transfer unit 306 Input side temporary storage unit 308 Output side temporary storage unit 310 Operation control unit 312 Operation unit 314 Transfer sequencer 316 Operation sequencer 318 DMA transfer control unit

Embodiments will be described below with reference to the drawings.
In all the drawings for explaining the embodiments, the same reference numerals are used for those having the same function, and repeated explanation is omitted.

<Mobile terminal 100>
FIG. 3 shows an embodiment of the mobile terminal 100. FIG. 1 mainly shows a hardware configuration.

  The portable terminal 100 includes a wireless unit 102, an L1 processing unit 104, an L2 processing unit 106, a communication control CPU 108, an application CPU 110, and a user interface circuit 112.

  The radio unit 102 converts the modulated wave from the L1 processing unit 104 into a high frequency signal. The radio unit 102 amplifies the high frequency signal with a power amplifier and transmits it from the antenna. The radio unit 102 amplifies a radio signal from the antenna and inputs the amplified signal to the L1 processing unit 104.

  The L1 processing unit 104 is connected to the wireless unit 102. The L1 processing unit 104 performs processing related to a radio signal, that is, processing related to the physical layer. The L1 processing unit 104 includes a demodulation unit 142 that demodulates a signal from the wireless unit 102. The L1 processing unit 104 includes a decoding unit 144 that decodes the signal demodulated by the demodulation unit 142. The signal decoded by the decoding unit 144 is input to the L2 control unit 106. The L1 processing unit 104 also includes an encoding unit 146 that performs encoding processing of transmission data. The L1 processing unit 104 includes a modulation unit 148 that performs modulation processing on the transmission data encoded by the encoding unit 146. The signal modulated by the modulation unit 148 is input to the radio unit 102.

  The L2 processing unit 106 is connected to the L1 processing unit 104. The L2 processing unit 106 performs processing related to layer 2 with a base station (not shown). Layer 2 provides layer 3 with a logical channel transmission service. A logical channel is comprised from a control channel (CCH: Control Channel) and a traffic channel (TCH: Traffic Channel). Transmission of these channels is realized by functions of an RLC (Radio Link Control) sublayer and a MAC (Medium Access Control) sublayer. The RLC sublayer provides services such as transmission transmission, non-delivery confirmation transmission, delivery confirmation transmission, and transmission quality setting to the upper layer. The MAC sublayer provides services such as mapping of logical channels to transport channels, priority control, flow control, flow rate monitoring, and reporting to RRC (Radio Resource Control) to the upper layer.

  The communication control CPU 108 is connected to the L2 processing unit 106. The communication control CPU 108 performs communication control such as transmission / reception of control signals.

  Application CPU 110 is connected to communication control CPU 108. The application CPU 110 processes an application installed in the mobile terminal 100.

  The user interface circuit 112 is connected to the application CPU 110. The user interface circuit 112 outputs information to the user. From the user interface circuit 112, the processing result by the application CPU 110 may be output.

  In one embodiment of the portable terminal 100, the L1 control unit 104 is realized by software-defined radio so as to be compatible with a plurality of wireless communication schemes. The L1 control unit 104 has a plurality of functions. FIG. 3 shows a demodulator 142, a decoder 144, an encoder 146, and a modulator 148 as examples of a plurality of functions. Other functions may be included, and any of a plurality of functions illustrated in FIG. 3 may be included. Each function is executed by one or more processors. Specifically, the L1 control unit 104 includes a DSP (Digital Signal Processor), an accelerator, a memory, and the like in order to be realized by software-defined radio.

  FIG. 4 shows an embodiment of the demodulator 142 of the L1 controller 104. FIG. 4 mainly shows the hardware configuration.

The demodulator 142 includes an RF interface 202, a bus interface 204, DSPs 206 ₁ -206 ₃ , accelerators 208 ₁ -208 _2, and a memory 210. The RF interface 202, the bus interface 204, the DSPs 206 _{1 to} 206 ₃ , the accelerators 208 _{1 to} 208 ₂ , and the memory 210 are connected to each other via the bus 212. FIG. 4 shows an example in which the demodulation unit 142 includes three DSPs, but the number of DSPs may be one, two, or four or more. 4 shows an example in which the demodulator 142 includes two accelerators, the number of accelerators may be one or three or more.

  The circuit scale of the L1 processing unit 104 is affected by the number of processors included in each unit. By improving the calculation performance of the processor, the number of processors included in each unit can be reduced. By reducing the number of processors included in each unit, the circuit scale of the L1 processing unit 104 can be reduced.

  The modulation unit 148 may also be realized with substantially the same hardware configuration as the demodulation unit 142. The decoding unit 144 and the encoding unit 146 may also be realized with substantially the same hardware configuration as the demodulation unit 142. However, the bus interface 204 may be provided instead of the RF interface 202.

  The RF interface 202 is an interface between the demodulation unit 142 and the wireless unit 102.

  The bus interface 204 is an interface between the demodulation unit 142 and the encoding unit 144.

The DSPs 206 ₁ -206 ₃ process signals from the wireless unit 102. That is, the DSPs 206 _{1 to} 206 ₃ execute processing for demodulating the signal from the wireless unit 102. Hereinafter, the DSPs 206 _{1 to} 206 ₃ may be referred to as signal processing devices. When executing the process of demodulating the signal from the wireless unit 102, the process may be shared and executed by all the DSPs, or may be executed by some DSPs.

The accelerators 208 ₁ -208 ₂ improve the processing capabilities of the DSPs 206 ₁ -206 ₃ . Depending on the processing capabilities of the DSPs 206 ₁ -206 ₃ , the accelerators 208 ₁ -208 ₂ are not necessarily required.

  The memory 210 temporarily stores a signal from the wireless unit 102.

<Signal processing device>
FIG. 5 shows an embodiment of the function of the signal processing device. FIG. 5 shows an embodiment of the functions of the DSPs 206 _{1 to} 206 ₃ as an embodiment of the signal processing apparatus.

Since the DSPs 206 _{1 to} 206 ₃ are represented by substantially the same functional block diagrams, the DSP 206 ₁ will be described as a representative in FIG.

The DSP 206 ₁ includes a transfer control unit 302, a data transfer unit 304, an input-side temporary storage unit 306, an output-side temporary storage unit 308, an operation control unit 310, an operation unit 312, a transfer sequencer 314, and an operation sequencer. 316.

  The transfer control unit 302 performs control to write the data stored in the memory 210 to the input side temporary storage unit 306 as necessary. In addition, the transfer control unit 302 performs control to transfer the data written in the output side temporary storage unit 308 to the decryption unit 144. The data written in the output side temporary storage unit 306 includes data processed by the arithmetic unit 312. The transfer control unit 302 may perform control to transfer data to the encoding unit 144 via the bus 212 and the bus interface 204. Further, the transfer control unit 302 may perform control to transfer data to the memory 210.

  Specifically, the transfer control unit 302 performs the process of transferring the above-described data in accordance with an instruction issued by the transfer sequencer 314 that is activated by executing a program for demodulation processing. For example, the transfer sequencer 314 sequentially takes out the instructions stored in the program memory and issues the instructions to the transfer control unit 302. The transfer sequencer 314 stores an address on the currently executing program memory. The transfer sequencer 314 may use a register to store an address on the currently executing program memory.

  The transfer control unit 302 starts access to the memory 210 in accordance with an instruction from the transfer sequencer 314. When the transfer control unit 302 starts access to the memory 210, the transfer control unit 302 outputs information indicating access. As a response to the information indicating access, the memory 210 responds with information indicating whether or not the memory 210 is accessible. The information indicating whether access is possible includes information indicating whether data can be read from the memory 210. Further, the information indicating whether or not access is possible may include information indicating whether or not writing to the memory 210 is possible. The transfer control unit 302 controls the data transfer unit 304 to control the arithmetic unit 312 from the memory 210 when it is accessible based on a signal indicating whether or not the memory 210 is accessible. Transfer the read data. In this case, if necessary, data read from the memory 210 is stored in the input-side temporary storage unit 306 and then transferred to the arithmetic unit 312.

  For example, when processing is performed using VLIW, the transfer control unit 302 handles processing having one function as one instruction. The transfer control unit 302 bundles a plurality of instructions and executes them as one long instruction. The instructions include “load” for reading data from the memory 210, “store” for writing data to the memory 210, “calculation” for calculating data read from the memory 210, “branch”, and the like. The transfer control unit 302 combines these genre commands to create one long command. Specifically, the transfer control unit 302 may create one instruction by combining “load” and “store” among these genre instructions.

  By combining instructions to create one long instruction, multiple processes can be executed with one instruction. Since a plurality of processes can be executed with one instruction, the processing performance can be improved. Since the processing performance can be improved, the number of processors for processing can be reduced. However, there are cases where the execution timings of processes classified by genre are different, and the instructions included in one instruction are not usually related to each other. In other words, the data loaded by the load instruction in the combined instruction may not be used in the operation instruction in the same instruction.

  The data transfer unit 304 is connected to the transfer control unit 302 and the bus 212. The data transfer unit 304 performs processing for inputting the data read from the memory 210 to the arithmetic unit 312. The data transfer unit 304 performs processing for writing the data read from the memory 210 to the input-side temporary storage unit 306 in accordance with control by the transfer control unit 302. Further, the data transfer unit 304 performs processing for transferring the data written in the output side temporary storage unit 308 to the bus 212 in accordance with control by the transfer control unit 302. The data written in the output-side temporary storage unit 308 includes data processed by the arithmetic unit 312. The data transfer unit 304 transfers data to the encoding unit 144 via the bus 212 and the bus interface 204.

  The input side temporary storage unit 306 is connected to the data transfer unit 304. The input side temporary storage unit 306 temporarily stores data from the data transfer unit 304.

  The output side temporary storage unit 308 is connected to the data transfer unit 304. The output side temporary storage unit 308 temporarily stores data from the arithmetic unit 312.

  The arithmetic control unit 310 controls arithmetic processing executed by the arithmetic unit 312. For example, the arithmetic control unit 310 performs control related to matrix calculation for demodulation processing. For example, the arithmetic control unit 310 controls the arithmetic unit 312 to perform arithmetic processing on the data from the data transfer unit 304. Further, for example, the arithmetic control unit 310 performs control to acquire data written in the input-side temporary storage unit 306 by controlling the arithmetic unit 312. Further, for example, the arithmetic control unit 310 controls the arithmetic unit 312 to perform arithmetic processing on the data from the input-side temporary storage unit 306. Further, for example, the arithmetic control unit 310 performs control to output data to the output side temporary storage unit 308 by controlling the arithmetic unit 312.

  For example, the arithmetic control unit 310 may create an “arithmetic” instruction. Specifically, the arithmetic control unit 310 performs control related to the arithmetic processing described above in accordance with an instruction issued by the arithmetic sequencer 316 that is activated by executing a program for demodulation processing. For example, the arithmetic sequencer 316 sequentially takes out the instructions stored in the program memory and issues the instructions to the arithmetic control unit 310. The arithmetic sequencer 316 stores an address on the currently executing program memory. The arithmetic sequencer 316 may use a register to store an address on the currently executing program memory.

  The arithmetic unit 312 is connected to the arithmetic control unit 310, the input side temporary storage unit 306, and the output side temporary storage unit 308. The arithmetic unit 312 performs arithmetic processing related to demodulation processing according to control by the arithmetic control unit 310. Specifically, the arithmetic unit 312 acquires data from the data transfer unit 304 via the input-side temporary storage unit 306 as necessary. The arithmetic unit 312 performs an operation related to demodulation using the data. The arithmetic unit 312 outputs the arithmetic result to the data transfer unit 304. When the calculation result is output to the data transfer unit 304, it is output via the output-side temporary storage unit 308 as necessary.

  A processor (not shown) and a control circuit (not shown) exist above the transfer sequencer 314 and the operation sequencer 316. The transfer sequencer 314 and the operation sequencer 316 operate according to instructions from the processor and the control circuit.

  In response to an instruction from the processor or control circuit, the transfer instruction sequencer 314 and the operation instruction sequencer 316 start executing the program substantially simultaneously. Alternatively, the transfer instruction sequencer 314 may start processing slightly earlier than the operation instruction sequencer 316 in accordance with an instruction from the processor or the control circuit.

  The data loaded from the memory 210 by the data transfer unit 304 is temporarily buffered in the input side temporary storage unit 306 as necessary. The arithmetic unit 312 reads the data buffered in the input-side temporary storage unit 306 and executes arithmetic processing. The arithmetic unit 312 may read data buffered in the input-side temporary storage unit 306 by a FIFO (First-In First-Out) method. The arithmetic unit 312 outputs the processed data to the output-side temporary storage unit 308 as necessary.

  When data is stored in the output-side temporary storage unit 308, the transfer sequencer 314 issues an instruction to store the data to the memory 210. The transfer control unit 302 controls the data transfer unit 304 in accordance with an instruction for storing the data.

  The transfer sequencer 314 and the operation sequencer 316 may synchronize instructions using a FIFO full flag and an empty flag. With this configuration, the arithmetic unit 312 can always access data to be processed. Since the arithmetic unit 312 can always access data to be processed, the occurrence of a stall can be reduced. Further, even when a stall occurs during execution of loading by the data transfer unit 304, it is absorbed by the input-side temporary storage unit 306. For this reason, the stall in the arithmetic unit 312 can be reduced.

<Time chart (part 1)>
FIG. 6 shows processing executed by the signal processing device. In FIG. 6, the horizontal axis represents time. For example, the horizontal axis is represented by “cycle”. In FIG. 6, (1)-(11) are attached corresponding to each cycle. The arithmetic unit 312 uses the loaded data for execution of the operation 1-1 (OP1-1). That is, the loaded data is not directly used for the execution of the operation 1-2 (OP1-2) and the operation 1-3 (OP1-3).

  According to the control by the transfer control unit 302, the data transfer unit 304 executes data loading continuously in time. For example, load instructions are sequentially issued from the transfer sequencer 314. The data transfer unit 304 performs transfer processing with the maximum capacity in accordance with the load instruction. The arithmetic unit 312 starts processing when the temporarily stored data can be read.

  In cycle (1) and cycle (2), an instruction for executing data loading is issued from the transfer sequencer 314. In cycle (1) and cycle (2), data loading is executed in two cycles by the data transfer unit 304 under the control of the transfer control unit 302 (LD1). A stall occurs during one cycle of the first half of the two cycles in which data loading is executed. The stall may occur due to the influence of other transfers, or may occur due to a slow transfer rate. The two cycles in which data loading is executed are an example, and may be one cycle or three or more cycles.

  In cycle (3), an instruction for executing data loading is issued from the transfer sequencer 314. In cycle (3), data is loaded by the data transfer unit 304 under the control of the transfer control unit 302 (LD2). In cycle (3), a stall has occurred. In the cycle (3), the data transfer unit 304 writes the data 1 (data1) loaded by the data transfer unit 304 in the cycle (2) to the input side temporary storage unit 306 according to the control by the transfer control unit 302. Further, in cycle (3), an instruction for executing operation 1-1 is input from the arithmetic control unit 310 to the arithmetic unit 312. The arithmetic unit 312 acquires data 1 from the input-side temporary storage unit 306 in order to execute operation 1-1. The arithmetic unit 312 discards the data 1 from the input side temporary storage unit 306.

  In cycle (4), data loading is continued by the data transfer unit 304 under the control of the transfer control unit 302 (LD2). In cycle (4), data loading is executed. In cycle (4), an instruction for executing operation 1-2 is issued from operation sequencer 316. In cycle (4), an instruction for executing operation 1-2 is output from the arithmetic control unit 310 to the arithmetic unit 312. Operation 1-2 may be processing that uses the result of operation 1-1.

  In cycle (5), the transfer sequencer 314 issues an instruction for executing data loading. In cycle (5), data is loaded by the data transfer unit 304 under the control of the transfer control unit 302 (LD3). In cycle (5), a stall has occurred. In the cycle (5), the data transfer unit 304 writes the data 2 loaded in the cycle (4) by the data transfer unit 304 to the input side temporary storage unit 306 in accordance with the control by the transfer control unit 302. Further, in cycle (5), an instruction for executing operation 1-3 is issued from operation sequencer 316. In cycle (5), an instruction for executing operation 1-3 is output from arithmetic control unit 310 to arithmetic unit 312. Operation 1-3 may be processing that uses the result of operation 1-2. Since the arithmetic unit 312 does not acquire the data 2 from the input side temporary storage unit 306, the data 2 is still written in the input side temporary storage unit 306.

  In cycle (6), data loading is continued by the data transfer unit 304 under the control of the transfer control unit 302 (LD3). In cycle (6), data loading is executed. Further, in cycle (6), an instruction for executing operation 1-1 is issued from the operation sequencer 316. In the cycle (6), an instruction for executing the operation 1-1 is output from the arithmetic control unit 310 to the arithmetic unit 312. The arithmetic unit 312 acquires data 2 from the input side temporary storage unit 306 in order to execute the operation 1-1. The arithmetic unit 312 discards the data 2 from the input side temporary storage unit 306.

  In cycle (7), the transfer sequencer 314 issues an instruction for executing data loading. In cycle (7), data is loaded by the data transfer unit 304 under the control of the transfer control unit 302 (LD4). In cycle (7), a stall has occurred. In the cycle (7), the data transfer unit 304 writes the data 3 (data3) loaded in the cycle (6) by the data transfer unit 304 to the input side temporary storage unit 306 according to the control by the transfer control unit 302. Further, in cycle (6), an instruction for executing operation 1-2 is issued from operation sequencer 316. In the cycle (7), an instruction for executing the operation 1-2 is output from the arithmetic control unit 310 to the arithmetic unit 312. Operation 1-2 may be processing that uses the result of operation 1-1. Since the arithmetic unit 312 does not acquire the data 3 from the input side temporary storage unit 306, the data 3 is still written in the input side temporary storage unit 306.

  In cycle (8), the data transfer unit 304 continues to load data according to the control by the transfer control unit 302 (LD4). In cycle (8), data loading is executed. Further, in the cycle (8), an instruction for executing the operation 1-3 is issued from the arithmetic sequencer 316. In the cycle (8), an instruction for executing the operation 1-3 is output from the arithmetic control unit 310 to the arithmetic unit 312. Operation 1-3 may be processing that uses the result of operation 1-2. Since the arithmetic unit 312 does not acquire the data 3 from the input side temporary storage unit 306, the data 3 is still written in the input side temporary storage unit 306.

  In cycle (9), an instruction for executing operation 1-1 is issued from arithmetic sequencer 316. In cycle (9), an instruction for executing operation 1-1 is output from the arithmetic control unit 310 to the arithmetic unit 312. The arithmetic unit 310 acquires data 3 from the input side temporary storage unit 306 in order to execute the operation 1-1. The arithmetic unit 312 discards the data 3 from the input side temporary storage unit 306.

  In cycle (10), an instruction for executing operation 1-2 is issued from operation sequencer 316. In the cycle (10), an instruction for executing the operation 1-2 is output from the arithmetic control unit 310 to the arithmetic unit 312.

  In cycle (11), an instruction for executing operation 1-3 is issued from operation sequencer 316. In the cycle (11), an instruction for executing the operation 1-3 is output from the arithmetic control unit 310 to the arithmetic unit 312.

  When data loading is executed a plurality of times by the data transfer unit 304, the data may be sequentially stored in the input side temporary storage unit 306. The arithmetic unit 312 may acquire data from the input-side temporary storage unit 306 according to the FIFO method in order to execute the operation. In this case, there are cases where there are a plurality of types of data and the data needs to be identified, but the transfer order is controlled so that the data are arranged in the order of calculation.

  For example, when transfer control is performed based on an instruction created using VLIW, a portion corresponding to the transfer instruction of an instruction created using VLIW is extracted, and data transfer unit 304 stores input side primary storage. The data is arranged in the order used by the unit 306.

  Further, instead of acquiring data from the input-side temporary storage unit 306 according to the FIFO method, a path to which data is supplied may be identified. Since the path to which the data is supplied can be identified, the data can be identified even when the data transfer unit 304 loads the data a plurality of times. Since the data can be identified, the data that is the target of the operation instruction can be acquired.

  For example, if there is a plurality of types of data to be calculated in accordance with the calculation instruction and it is necessary to identify the data, the same number of input side primary storage units as the data to be calculated may be prepared. The arithmetic unit 312 selects the data to be used from the plurality of input side temporary storage units.

  According to the time chart shown in FIG. 6, since the data loading and the arithmetic processing can be controlled independently, the load instruction can be executed in a temporally continuous cycle. Since the load instruction can be executed in a continuous cycle in time, even when a stall occurs when reading from the memory, data for executing the arithmetic instruction is prepared in advance when the arithmetic instruction is executed. be able to. Since data for executing the operation instruction can be prepared in advance, the stall of the operation instruction can be reduced.

  If the instruction is issued so that the data transfer instruction and the arithmetic instruction are executed substantially simultaneously, even if the order of data to be transferred is clear, the transfer is not performed until the transfer instruction is issued. . When a transfer command is issued and a data transfer command is executed, a stall due to the speed of the memory may occur or a stall due to the use of a bus of another device may occur. For this reason, there may be a delay until the execution of the arithmetic instruction programmed to be executed almost simultaneously with the transfer instruction. According to the time chart shown in FIG. 6, by temporarily storing the loaded data, it is possible to absorb a time difference that requires data between the data transfer unit 304 and the arithmetic unit 312. For this reason, it is possible to reduce a stall caused by the speed of the memory and a stall caused by using a bus of another device. For this reason, it is possible to reduce the execution delay of the arithmetic instruction.

<Time chart (2)>
FIG. 7 shows processing executed by the signal processing device. In FIG. 7, the horizontal axis represents time. For example, the horizontal axis is represented by “cycle”. In FIG. 7, (1) to (13) are attached corresponding to each cycle.

  In cycle (1) and cycle (2), an instruction for executing data loading is issued from the transfer sequencer 314. In cycle (1) and cycle (2), data loading is executed in each cycle by the data transfer unit 304 in accordance with control by the transfer control unit 302.

  Further, in cycle (2), an instruction for storing data from the arithmetic control unit 310 to the memory 210 is output to the arithmetic unit 312. However, since the memory 210 is stalled, the arithmetic unit 312 writes data to the output side temporary storage unit 308.

  In cycle (3), an instruction for executing the operation is issued from the operation sequencer 316. In the cycle (3), under the control of the arithmetic control unit 310, the arithmetic unit 312 performs an operation using the data loaded in the cycle (1). Further, the data transfer unit 304 transfers the data written in the output side temporary storage unit 308 to the memory 210 according to the control by the transfer control unit 302. The data transfer unit 304 outputs the data written in the output side temporary storage unit 308 by the FIFO method. By having the output-side temporary storage unit 308, data loading and arithmetic processing can be controlled independently, so that congestion can be avoided. Further, when there are a plurality of types of data to be transferred, it is necessary to identify the data, and it is necessary to supply the data in the order in which the transfer instructions are issued. By outputting the data using the FIFO method, data can be supplied in the order in which transfer instructions are issued.

  In cycle (4), the transfer sequencer 314 issues an instruction for executing data loading. In cycle (4), data loading is executed by the data transfer unit 304 under the control of the transfer control unit 302. In cycle (4), an instruction for executing the operation is issued from the operation sequencer 316. In the cycle (4), an operation using the data loaded in the cycle (2) is executed by the operation unit 312 under the control of the operation control unit 310.

  In cycle (5), the transfer sequencer 314 issues an instruction for executing data loading. In cycle (5), data is loaded by the data transfer unit 304 under the control of the transfer control unit 302. In cycle (5), an instruction for executing the operation is issued from the operation sequencer 316. In the cycle (5), the calculation using the data loaded in the cycle (4) is executed by the calculation unit 312 according to the control by the calculation control unit 310.

  In cycle (6), the transfer sequencer 314 issues an instruction for executing data loading. In cycle (6), data loading is executed by the data transfer unit 304 in accordance with control by the transfer control unit 302. Further, in cycle (6), an instruction for storing data from the arithmetic control unit 310 to the memory 210 is output to the arithmetic unit 312. However, since the memory 210 is stalled, the arithmetic unit 312 writes data to the output side temporary storage unit 308.

  In cycle (7), an instruction for executing the operation is issued from the operation sequencer 316. In the cycle (7), the calculation using the data loaded in the cycle (5) is executed by the calculation unit 312 according to the control by the calculation control unit 310. Further, the data transfer unit 304 transfers the data written in the output side temporary storage unit 308 to the memory 210 according to the control by the transfer control unit 302. The data transfer unit 304 outputs the data written in the output side temporary storage unit 308 by the FIFO method.

  In cycle (8), the transfer sequencer 314 issues an instruction for executing data loading. In cycle (8), data loading is executed by the data transfer unit 304 in accordance with control by the transfer control unit 302. In cycle (8), an instruction for executing the operation is issued from the operation sequencer 316. In the cycle (8), an operation using the data loaded in the cycle (6) is executed by the operation unit 312 according to the control by the operation control unit 310.

  In cycle (9), the transfer sequencer 314 issues an instruction for executing data loading. In cycle (9), data is loaded by the data transfer unit 304 in accordance with the control by the transfer control unit 302. In the cycle (9), an instruction for executing an operation is issued from the arithmetic sequencer 316. In the cycle (9), an operation using the data loaded in the cycle (8) is executed by the operation unit 312 according to the control by the operation control unit 310.

  In cycle (10), the transfer sequencer 314 issues an instruction for executing data loading. In cycle (10), data loading is executed by the data transfer unit 304 in accordance with control by the transfer control unit 302. Further, in cycle (10), an instruction for storing data in the memory 210 is output from the arithmetic control unit 310 to the arithmetic unit 312. However, since the memory 210 is stalled, the arithmetic unit 312 writes data to the output side temporary storage unit 308.

  In the cycle (11), an instruction for executing an operation is issued from the arithmetic sequencer 316. In the cycle (11), an operation using the data loaded in the cycle (9) is executed by the operation unit 312 according to the control by the operation control unit 310. Further, the data transfer unit 304 transfers the data written in the output side temporary storage unit 308 to the memory 210 according to the control by the transfer control unit 302. The data transfer unit 304 outputs the data written in the output side temporary storage unit 308 by the FIFO method.

  In cycle (12), the transfer sequencer 314 issues an instruction for executing data loading. In the cycle (12), data loading is executed by the data transfer unit 304 under the control of the transfer control unit 302. In the cycle (12), an instruction for executing the operation is issued from the arithmetic sequencer 316. In the cycle (12), an operation using the data loaded in the cycle (10) is executed by the operation unit 312 under the control of the operation control unit 310.

  In the cycle (13), an instruction for executing an operation is issued from the arithmetic sequencer 316. In the cycle (13), an operation using the data loaded in the cycle (12) is performed by the operation unit 312 under the control of the operation control unit 310.

  In the cycle (3), the data transfer unit 304 can identify the path to which data is supplied instead of outputting the data (calculation result) written in the output-side temporary storage unit 308 by the FIFO method. Good. Since the path to which data is supplied can be identified, the data can be identified even when a plurality of types of data are transferred. Since the data can be identified, the data can be supplied in the order in which the transfer instructions are issued.

  Since the path to which the data is supplied can be identified, the calculation result can be identified even when the calculation process is executed a plurality of times by the calculation unit 312. Since the calculation result can be identified, the calculation result can be acquired according to the calculation process.

  For example, when there are a plurality of calculation results that have been processed in accordance with a calculation command and it is necessary to identify the calculation results, the same number of output side primary storage units as the calculation results may be prepared.

  FIG. 8 shows processing according to the conventional configuration. In FIG. 8, the horizontal axis represents time. For example, the horizontal axis is represented by “cycle”. In FIG. 8, (1)-(13) are attached corresponding to each cycle.

  In cycle (1), data loading is executed.

  In cycle (2), an attempt is made to load data. However, no data is loaded because the memory stores. The reason why the data is not loaded is that the load and store cannot be performed simultaneously because there is one access port to the memory. In the time chart shown in FIG. 7, the output side temporary storage unit 108 avoids the stall.

  In cycle (3), the data that was supposed to be loaded in cycle (2) is loaded. The memory stores the data stored in cycle (2).

  In cycle (4), an operation using the data loaded in cycle (1) is executed.

  In cycle (5), data loading is executed. In cycle (5), an operation using the data loaded in cycle (3) is executed.

  In cycle (6), data loading is executed. In cycle (6), an operation using the data loaded in cycle (5) is executed.

  In cycle (7), an attempt is made to load data. However, no data is loaded because the memory stores. The reason why the data is not loaded is that the load and store cannot be performed simultaneously because there is one access port to the memory.

  In cycle (8), the data that was supposed to be loaded in cycle (7) is loaded. The memory stores the data stored in cycle (7).

  In cycle (9), an operation using the data loaded in cycle (6) is executed.

  In cycle (10), data loading is executed. In the cycle (10), an operation using the data loaded in the cycle (8) is executed.

  In cycle (11), data loading is executed. In the cycle (11), an operation using the data loaded in the cycle (10) is executed.

  In cycle (12), an attempt is made to load data. However, since the memory is stored, no data is loaded. The reason why the data is not loaded is that the load and store cannot be performed simultaneously because there is one access port to the memory.

  In cycle (13), loading of data that should have been loaded in cycle (12) is performed. The memory stores the data stored in cycle (12).

  In the time chart shown in FIG. 8, it can be seen that the calculation efficiency is reduced because memory congestion occurs in cycles (2), (7), and (12).

<Operation of signal processing device>
9 and 10 are flowcharts showing an embodiment of the operation of the signal processing apparatus.

  FIG. 9 mainly shows processing executed by the data transfer unit 304 in accordance with control by the transfer control unit 302.

  FIG. 10 mainly shows processing executed by the arithmetic unit 312 in accordance with control by the arithmetic control unit 310.

  Processing executed by the data transfer unit 304 in accordance with control by the transfer control unit 302 will be described with reference to FIG.

  In step S902, the data transfer unit 304 is activated. For example, the data transfer unit 304 may be turned on by turning on the power of the mobile terminal 100.

  In step S904, the transfer control unit 302 determines whether there is data to be transferred.

  If there is data to be transferred, in step S906, the transfer control unit 302 determines whether the input temporary storage unit 306 has free space. For example, the transfer control unit 302 determines whether or not the input temporary storage unit 306 has a free space corresponding to the data determined to exist in step 904.

  In step S908, the transfer control unit 302 controls the data transfer unit 304 to transfer the data from the memory 210 to the input-side temporary storage unit 306.

  If there is no data to be transferred in step S904, the processes in steps S906 and S908 are not executed. If there is no free space in the input side temporary storage unit 306 in step S906, the process in step S908 is not executed.

  In step S910, the transfer control unit 302 determines whether there is data to be transferred in the output-side temporary storage unit 308.

  If there is data to be transferred in step S912, the transfer control unit 302 controls the data transfer unit 304 to transfer the data from the output side temporary storage unit 308 to the memory 210.

  If there is no data to be transferred in step S910, the process in step S912 is not executed.

  In step S914, the transfer control unit 302 determines whether or not the data transfer process has ended. When the data transfer process ends, the transfer control unit 302 ends the process. If the data transfer process does not end, the transfer control unit 302 executes the process from step S904.

  In the flowchart shown in FIG. 9, the processes in steps S904 to S908 and the processes in steps S910 to S912 may be interchanged.

  Processing executed by the arithmetic unit 312 in accordance with control by the arithmetic control unit 310 will be described with reference to FIG.

  In step S1002, the arithmetic unit 312 is activated. For example, the power of the arithmetic unit 312 may be turned on when the power of the mobile terminal 100 is turned on.

  In step S1004, the arithmetic control unit 310 determines whether unprocessed data exists in the input-side temporary storage unit 306.

  If unprocessed data exists, in step S1006, the arithmetic control unit 310 controls the arithmetic unit 312 to read data from the input-side temporary storage unit 306 and execute arithmetic processing.

  In step S1008, the arithmetic control unit 310 determines whether or not the output-side temporary storage unit 308 has free space. For example, the arithmetic control unit 310 determines whether or not the output side temporary storage unit 308 has a free space corresponding to the data processed in step 1006.

  In step S <b> 1010, the arithmetic control unit 310 controls the arithmetic unit 312 to transfer data to the output side temporary storage unit 308.

  If there is no unprocessed data in step S1004, the determination in step S1004 is performed again. If the output side temporary storage unit 308 has no free space in step S1008, the determination in step S1008 is performed again.

  In step S1012, the arithmetic control unit 310 determines whether or not the arithmetic processing has ended. When the calculation process is completed, the calculation control unit 310 ends the process. If the calculation process is not terminated, the calculation control unit 310 executes the process from step S1004.

<Effect of this embodiment>
FIG. 11 shows the effect of an embodiment of the signal processing apparatus.

  The diagram (1) on the left represents the processing by the conventional signal processing device, and the diagram (2) on the right represents the processing by the signal processing device of the present embodiment.

  “A” represents the entire processing capacity of the processor. “B” represents the ability lost due to the occurrence of a stall. “C” and “d” represent effective abilities that can be used to execute the process.

  The number of processors capable of processing the required calculation amount is obtained by dividing the required calculation amount by the processing capacity of the portion “c”.

  In the conventional signal processing apparatus, the ratio of the capacity lost due to the occurrence of the stall is large in the entire processing capacity of the processor. As a result, the required number of processors increases in the conventional signal processing apparatus.

  In the signal processing apparatus according to the present embodiment, the ratio of the capacity lost due to the occurrence of the stall is small in the entire processing capacity of the processor as compared with the conventional signal processing apparatus. As a result, the signal processing apparatus of this embodiment can reduce the required number of processors. Since the required number of processors can be reduced, the circuit scale for realizing the target processing can be reduced.

<Modification>
FIG. 12 shows a modification of the function of the signal processing device.

  A modification of the signal processing apparatus is different in that the signal processing apparatus described with reference to FIG. 5 includes a DMA (Direct Memory Access) transfer control unit 318 instead of the transfer sequencer 314. The function of the DMA transfer control unit 318 is substantially the same as the function of the transfer control unit 302. The DMA transfer control unit 318 may include a load DMA transfer control unit and a store DMA transfer control unit. The DMA transfer control unit 318 performs the data transfer process without depending on the instruction stored in the program memory. For example, the DMA transfer control unit 318 sets transfer contents. The transfer content includes information indicating the address where the data exists and information indicating the size of the data to be transferred. The DMA transfer control unit 318 is different in that the DMA transfer control unit 318 is started according to the setting by the arithmetic sequencer 316. In this case, the DMA transfer control unit 318 may be activated by executing a calculation instruction from the calculation sequencer 316. The DMA transfer control unit 318 may be activated by a control signal from a higher-level functional block level control processor or control circuit.

  By having the DMA transfer control unit 318, the instruction can be issued to the transfer control unit 302 so as to directly access the memory after the startup according to the setting by the arithmetic sequencer 316, so that the processing speed can be improved.

  The signal processing apparatus according to the present embodiment and the modification can achieve an effect by being applied to a communication system that executes a large amount of relatively simple operations represented by OFDM. OFDM is a method of frequency division multiplexing, in which carriers are arranged so as to be orthogonal to each other, thereby increasing the carrier frequency density and improving the frequency efficiency. OFDM is used for LTE, WiMAX, terrestrial digital broadcasting, and the like. This is because the order of data to be transferred is clear in advance in the communication method, and the influence on each other can be reduced while executing instructions in parallel. That is, by separating the control of the data transfer used for the calculation and the control for performing the actual calculation, it is possible to reduce the influence of the stall caused by the data transfer on the calculation process. For this reason, the arithmetic unit can be operated efficiently.

Claims (12)

An arithmetic control unit that controls the timing of arithmetic processing executed by the arithmetic unit;
Transfer control for controlling the timing for transferring the data subject to the arithmetic processing so that the data subject to the arithmetic processing can be loaded by the arithmetic unit according to the timing of the arithmetic processing controlled by the arithmetic control unit A signal processing device having a unit.   The signal processing apparatus according to claim 1, wherein the transfer control unit controls timing for transferring data to be subjected to the arithmetic processing in accordance with an instruction stored in a program memory.   The signal processing apparatus according to claim 1, wherein the transfer control unit controls a timing for transferring the data to be subjected to the arithmetic processing according to a DMA (Direct Memory Access) method.   4. The transfer control unit according to claim 1, wherein the transfer control unit follows a FIFO (First-In First-Out) system when controlling timing for transferring a plurality of data to be subjected to the arithmetic processing. 5. A signal processing device according to 1. One or more storage units for storing data transferred according to the timing controlled by the transfer control unit;
The transfer control unit transfers a plurality of data to be subjected to the arithmetic processing to the one or a plurality of storage units when controlling timing for transferring the plurality of data to be subjected to the arithmetic processing. The signal processing apparatus according to claim 1, wherein timing for controlling the signal is controlled. Control the timing of arithmetic processing executed by the arithmetic unit,
A signal processing method for controlling a timing for transferring data to be subjected to the arithmetic processing so that the arithmetic unit can load the data to be the arithmetic processing according to the timing of the arithmetic processing.   The signal processing device according to claim 1, wherein a timing controlled by the arithmetic control unit and a timing controlled by the transfer control unit are synchronized.   The signal processing apparatus according to claim 1, wherein the arithmetic control unit controls the arithmetic processing timing in accordance with an instruction stored in a program memory.   The signal processing device according to claim 1, wherein the arithmetic control unit controls a timing for transferring the data processed by the arithmetic unit.   The signal processing apparatus according to claim 9, wherein the arithmetic control unit conforms to a first-in first-out (FIFO) method when controlling timing for transferring the arithmetically processed data. Having one or a plurality of storage units for storing data transferred according to the timing controlled by the arithmetic control unit;
When the arithmetic control unit controls the timing for transferring the plurality of arithmetically processed data, the arithmetic control unit sets the timing for transferring the arithmetically processed plurality of data to the one or more storage units. The signal processing device according to claim 9, wherein the signal processing device is controlled.   A portable terminal comprising the signal processing device according to claim 1.

Images