JPWO2013065080A1 - Semiconductor integrated circuit device - Google Patents

Abstract

  The second cell (CL2) is adjacent to the first cell (CL1) having a cell height N times the reference cell height (N is an integer of 2 or more) in the cell width direction. A diffusion wiring (102) made of an impurity diffusion region is formed under the power supply metal wiring (101) of the second cell (CL2). The first cell (CL1) includes a transistor diffusion region (D_MP23) formed to face the diffusion wiring (102) so as to straddle the extension region in the cell width direction of the metal wiring (101). The diffusion wiring (102) is arranged away from the cell boundary (BL1) in the cell width direction.

Description

  The present invention relates to a semiconductor integrated circuit device having standard cells (hereinafter referred to as cells as appropriate), and more particularly to a layout having a configuration in which other cells are arranged adjacent to a so-called multi-height cell.

  As a method for designing a semiconductor integrated circuit, a design method using a standard cell is known. FIG. 20 shows an example of a standard cell layout, and a one-dot chain line indicates a cell frame. The length of the standard cell in the Y direction (y1 in FIG. 20) is called cell height, and the length in the X direction (x1 in FIG. 20) is called cell width. A cell having the same cell height as the reference height is called a single height cell. The cell width varies depending on the circuit configuration or the driving capability even in the same circuit configuration.

  In FIG. 20, the power supply wiring 501 and the ground wiring 506 formed in the metal wiring layer are arranged at the upper and lower ends of the cell so as to extend from the right end to the left end of the cell frame. PMOS transistors MP51 to MP53 are formed in the N well NW, and NMOS transistors MN51 to MN53 are formed in the P well PW. The P + diffusion wiring 502 formed of the P-type impurity diffusion region is disposed so as to overlap the power supply wiring 501 and is connected to the power supply wiring 501 through the contact 503. The N + diffusion wiring 507 formed of the N-type impurity diffusion region is disposed so as to overlap the ground wiring 506 and is connected to the ground wiring 506 through the contact 508.

  In FIG. 20, P + diffusion lines 504 and 505 branched from the P + diffusion line 502 are connected to the source diffusion region of the PMOS transistors MP51 to MP53, and N + diffusion lines 509 and 510 branched from the N + diffusion line 507 are The NMOS transistors MN51 to MN53 are connected to the source diffusion region. On the other hand, FIG. 21 shows a layout configuration in which the diffusion wirings 502A and 507A arranged under the power supply wiring 501 and the ground wiring 506 are used to fix the potentials of the wells NW and PW. The layout configuration shown in FIGS. 20 and 21 is well known as a general layout configuration.

  Usually, it is possible to reduce the area of the semiconductor integrated circuit by reducing the cell height of the standard cell. However, if a cell including a complicated circuit such as a flip-flop circuit or a cell having a large driving capability is created with a reference cell height, the cell width becomes very large, and conversely, the area may increase. is there.

  For this reason, a technique for creating such a cell as a multi-height cell whose cell height is N times the reference height (N is an integer of 2 or more) is known. For example, a double-height cell whose cell height is twice the reference height has a structure in which one of two single-height cells is inverted and integrated, and the central portion in the cell height direction. In FIG. 2, wells having a height approximately twice that of single-height cells are arranged. Since a transistor having a wide gate width can be arranged in this well, for example, a cell with high driving capability can be realized.

JP-A-7-249747 JP 2001-237328 A

  In recent semiconductor integrated circuit devices, the above-described multi-height cell is often arranged in addition to the single-height cell, and standard cells having a plurality of cell heights may be mixed. On the other hand, each standard cell used in the design needs to have a layout configuration so that the design rules can be observed even if any other standard cells are arranged adjacent to each other vertically or horizontally.

  FIG. 22 shows an example of a layout configuration in which a single height cell is arranged adjacent to a double height cell. CLa is a double-height cell in which a P-well PW, an N-well NW, and a P-well PW are arranged in order from the top in the cell height direction, and the height of the central N-well NW is N of a single-height cell. It is twice that of the well NW. CLb is a single height cell, and is arranged such that the lower end coincides with the cell CLa. That is, the ground wiring 606 and the N + diffusion wiring 607 of the cell CLa are connected to the ground wiring 506 and the N + diffusion wiring 507 of the cell CLb, respectively. Further, the layout of the diffusion region of the transistor MP63a of the cell CLa and the diffusion region of the transistor MP51 of the cell CLb are designed in advance so that the distance between them becomes the minimum value SP of the separation rule. In other words, the diffusion regions of the transistors MP63a and MP51 are each spaced apart by 1/2 SP from the cell frame.

  In the N well NW of the double height cell CLa, since no diffusion wiring is disposed under the power supply wiring 611, a large diffusion region of the transistor can be taken. In the layout of FIG. 22, a transistor MP62 having a large gate width and a large driving capability is formed.

  On the other hand, at the upper end of the single height cell CLb, the P + diffusion wiring 502 extends to both ends of the cell frame. For this reason, in the double height cell CLa, the diffusion region formed in the N well NW must be arranged at a distance SP or more away from the left end of the P + diffusion wiring 502 in order to observe the separation rule with the P + diffusion wiring 502. Don't be. Therefore, with respect to the gate wiring GA63, it is necessary to divide the diffusion region into two in the cell height direction, so that a single transistor with a large gate width cannot be formed, and two transistors MP63a and MP63b are formed. Regarding the gate wiring GA61, for the same reason, the diffusion region is divided into two in the cell height direction, and two transistors MP61a and MP61b are formed.

  In FIG. 22, the diffusion region of the entire N well NW of the double height cell CLa has a shape that is further recessed from the P + diffusion wiring 502 than the distance SP. The minimum dimension of the diffusion region with respect to the gate electrode in the transistor This is because there are restrictions by design rules.

  As described above, in consideration of the layout configuration of adjacent cells, in the wide well at the center of the double height cell, the transistors arranged near both ends in the cell width direction can have a sufficiently wide gate width according to the design rule. Can not. For this reason, the improvement of the driving capability of the transistor, which is one of the purposes of using the double height cell, cannot always be sufficiently realized. In particular, since the PMOS transistor has a low current capability, in order to obtain a large driving capability with a small area, it is desirable to form a transistor having a large gate width by utilizing a region where the PMOS transistor can be formed as much as possible.

  In a fine process, a dummy gate may be arranged on the cell boundary so that the gate electrodes are arranged at an equal pitch in order to suppress variation in the shape of the gate electrode of the transistor. For example, in FIG. 22, it is necessary to arrange dummy gates at the cell boundaries at the same pitch as the gates GA61 to GA63. However, if the dummy gate is arranged at the cell boundary with the layout of FIG. 22, there arises a problem that an unnecessary transistor is formed by the P + diffusion wiring 502 and the dummy gate.

  The problems described above are not limited to double-height cells, but may occur if the multi-height cell has a wide well and a layout configuration in which the diffusion wiring of other cells can be adjacent to the well. It is a problem.

  In view of the above-described problems, the present invention provides a layout configuration that can sufficiently improve the drive capability of a transistor in a multi-height cell in a semiconductor integrated circuit device having a configuration in which other cells are arranged adjacent to the multi-height cell. Is to provide.

  In one aspect of the present invention, in the semiconductor integrated circuit device in which a plurality of cells are arranged, the plurality of cells have a cell height that is N times the reference cell height (N is an integer of 2 or more). And a second cell disposed adjacent to the first cell in the cell width direction, and the second cell extends in the cell width direction at one end in the cell height direction. A first metal wiring arranged in this manner, and an impurity diffusion region formed so as to extend in the cell width direction under the first metal wiring, and is connected to the first metal wiring through a contact. The first cell is opposed to the first diffusion wiring in the cell width direction, and is formed so as to straddle the extension region in the cell width direction of the first metal wiring in the cell height direction. And tiger Comprising a first transistor diffusion region constituting the register, the first diffusion line, in a cell width direction, is spaced apart from the cell boundary between the first cell and the second cell.

  According to this aspect, the second cell arranged adjacent to the first cell which is a multi-height cell has the first metal wiring extending in the cell width direction at one end in the cell height direction, and the cell width direction under the metal wiring. And a first diffusion wiring composed of an impurity diffusion region formed so as to extend in the direction. The first cell includes a first transistor diffusion region formed so as to straddle an extension region in the cell width direction of the first metal wiring of the second cell in the cell height direction. The first diffusion wiring of the second cell facing the first transistor diffusion region is separated from the cell boundary between the first cell and the second cell in the cell width direction. For this reason, the separation rule between the first transistor diffusion region of the first cell and the diffusion wiring of the second cell is reliably maintained, and it is not necessary to divide the first transistor diffusion region. Therefore, a transistor having a large gate width can be formed without being influenced by the layout even in the vicinity of other adjacent cells.

  According to the present invention, in a multi-height cell, a transistor having a large gate width can be formed even in the vicinity of other adjacent cells. As a result, the driving capability of the transistor in the multi-height cell can be improved as compared with the prior art.

It is a top view which shows the layout structure of the single height cell in 1st Embodiment. It is a top view which shows the layout structure of the double height cell in 1st Embodiment. 1 is a plan view showing a layout configuration of a semiconductor integrated circuit device according to a first embodiment. It is a top view which shows the layout structure of the single height cell in 2nd Embodiment. It is a top view which shows the layout structure of the double height cell in 2nd Embodiment. It is a top view which shows the layout structure of the semiconductor integrated circuit device which concerns on 2nd Embodiment. It is a top view which shows the layout structure of the semiconductor integrated circuit device which concerns on 2nd Embodiment. It is a top view which shows the other example of the layout structure of the semiconductor integrated circuit device which concerns on 2nd this embodiment. It is a figure which shows a part of design flow of the semiconductor integrated circuit device which concerns on 3rd Embodiment. It is a figure which shows the design data of the single height cell in 3rd Embodiment. It is a figure which shows the design data of the double height cell in 3rd this embodiment. It is an example of the layout design data created in the layout design process S11 of FIG. It is a top view which shows the layout structure of the semiconductor integrated circuit device which concerns on 3rd Embodiment. It is an example of the layout design data created in the layout design process S11 of FIG. It is a top view which shows the layout structure of the semiconductor integrated circuit device which concerns on 3rd Embodiment. It is a figure which shows the design data of the single height cell in 4th Embodiment. It is a figure which shows the design data of the double height cell in 4th this embodiment. It is a top view which shows the layout structure of the semiconductor integrated circuit device which concerns on 4th Embodiment. It is a top view which shows the other example of the layout structure of the single height cell in embodiment. It is a top view which shows the layout structure of a general single height cell. It is a top view which shows the layout structure of a general single height cell. It is a figure for demonstrating the subject of this invention.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a plan view showing a layout configuration of a single height cell in the first embodiment. A single height cell is a cell having a reference cell height. In FIG. 1, the alternate long and short dash line indicates a cell frame. The horizontal direction (X direction) in the drawing is the cell width direction, and the vertical direction (Y direction) in the drawing is the cell height direction (the same applies to the following drawings).

  In FIG. 1, MP11 to MP13 are PMOS transistors formed in the N well NW, and MN11 to MN13 are NMOS transistors formed in the P well PW. 101 is a power supply wiring, and 106 is a ground wiring, both of which are formed in the first metal wiring layer. The power supply wiring 101 and the ground wiring 106 are respectively arranged at both ends in the cell height direction of the single height cell so as to extend in the cell width direction from the right end to the left end of the cell frame. The center line of the power supply wiring 101 coincides with the upper end of the cell frame, and the center line of the ground wiring coincides with the lower end of the cell frame. Reference numeral 102 denotes a P + diffusion wiring formed of a P-type impurity diffusion region formed so as to extend in the cell width direction below the power supply wiring 101, and is connected to the power supply wiring 101 through a contact 103. Reference numeral 107 denotes an N + diffusion wiring composed of an N-type impurity diffusion region formed so as to extend in the cell width direction below the ground wiring 106, and is connected to the ground wiring 106 via a contact 108.

  In the configuration of FIG. 1, the P + diffusion wiring 102 and the N + diffusion wiring 107 are arranged with a predetermined interval from the left and right ends of the cell frame in the cell width direction. Here, an interval corresponding to the sum of the width of one contact and the interval between contacts (that is, one grid in the contact arrangement) is provided. Therefore, the wiring 111 branched from the power supply wiring 101 is connected to the source diffusion region of the PMOS transistor MP11 via a contact, and the wiring 112 branched from the ground wiring 106 is connected to the source diffusion region of the NMOS transistor MN11. Connected through contacts. Although the wirings 111 and 112 are formed in the first metal wiring layer, they are arranged in limited areas at the upper left and lower left of the cell frame, so that the influence on the use of the first metal wiring layer as the wiring area is not affected. Limited. The P + diffusion wiring 104 branched from the P + diffusion wiring 102 is connected to the source diffusion regions of the PMOS transistors MP12 and MP13, and the N + diffusion branching from the N + diffusion wiring 107 is connected to the source diffusion regions of the NMOS transistors MN12 and MN13. A wiring 109 is connected.

  FIG. 2 is a plan view showing the layout configuration of the double height cell in the present embodiment. A double-height cell is a cell having a cell height that is twice the reference cell height.

  In FIG. 2, MP21 to MP23 are PMOS transistors formed in the N well NW, and MN21 to MN23 and MN24 to MN26 are NMOS transistors formed in the P well PW. In the configuration of FIG. 2, the PMOS transistors MP21 and MP23 arranged in the N well NW are not divided in the cell height direction, and the outer shape of the entire diffusion region constituting the PMOS transistors MP21 to MP23 has a recess. It is rectangular. The power supply wiring 211 is formed in the first metal wiring layer, and is arranged so as to extend in the cell width direction from the right end to the left end of the cell frame at the center in the cell height direction of the double height cell. A line branched from the power supply line 211 is connected to the source diffusion region of the PMOS transistors MP21 to MP23 through a contact.

  The ground wirings 201 and 206 are formed in the first metal wiring layer, and are arranged at both ends in the cell height direction of the double height cell so as to extend in the cell width direction from the right end to the left end of the cell frame. The center lines of the ground wires 201 and 206 coincide with the upper end and the lower end of the cell frame, respectively. Reference numeral 202 denotes an N + diffusion wiring composed of an N-type impurity diffusion region formed so as to extend in the cell width direction below the ground wiring 201, and is connected to the ground wiring 201 through a contact 203. Reference numeral 207 denotes an N + diffusion wiring made of an N-type impurity diffusion region formed so as to extend in the cell width direction under the ground wiring 206, and is connected to the ground wiring 206 through a contact 208. N + diffusion wirings 204 and 205 branched from the N + diffusion wiring 202 are connected to the source diffusion regions of the transistors MN24 to MN26, and N + diffusion wirings 209 and 210 branched from the N + diffusion wiring 207 are the source diffusion regions of the transistors MN21 to MN23. Connected with.

  FIG. 3 is a plan view showing a layout configuration of the semiconductor integrated circuit device according to the present embodiment. The first cell CL1 has the same configuration as the double height cell shown in FIG. 2, and the same configuration as the single height cell shown in FIG. A configuration in which the second cell CL2 is disposed adjacent to each other in the cell width direction is shown.

  In the configuration of FIG. 3, the first and second cells CL1, CL2 are arranged so that the lower ends thereof are aligned, and the ground wiring 206 as the third metal wiring of the first cell CL1 and the second metal wiring of the second cell CL2 are arranged. Are arranged so as to be in a straight line in the cell width direction and are connected to each other. However, the N + diffusion wiring 207 formed at the lower end of the first cell CL1 and the N + diffusion wiring 107 formed at the lower end of the second cell CL2 are such that the N + diffusion wiring 107 as the second diffusion wiring is predetermined from the cell frame. Since they are arranged at an interval (here, 1 grit), they are not connected.

  Further, in the central portion of the first cell CL1 in the cell height direction, the power supply wiring 211 is connected to the power supply wiring 101 as the first metal wiring of the second cell CL2. In the first cell CL1, the drain diffusion region D_MP23 of the transistor MP23 extends in the cell width direction so that the extended region in the cell width direction of the power supply wiring 101 of the second cell CL2 extends across the cell height direction. Formed opposite to the P + diffusion region 102. However, since the P + diffusion wiring 102 as the first diffusion wiring is arranged at a predetermined interval (here, 1 grit) from the cell frame, the drain diffusion region D_MP23 and the P + diffusion wiring 102 as the first transistor diffusion region are arranged. Is SP1 which is larger than the minimum value SP of the separation rule between diffusion regions. Note that the drain diffusion region D_MP23 of the transistor MP23 is disposed at a distance of 1/2 SP from the cell frame. An interval SP1 between the drain diffusion region D_MP23 and the P + diffusion wiring 102 is larger than a minimum interval SP between the drain diffusion region D_MP23 and the source diffusion region D_MP11 as the first diffusion region of the transistor MP11 facing the drain diffusion region D_MP23. Further, the drain diffusion region D_MP23 of the transistor MP23 has no recess and is rectangular.

  In other words, since the P + diffusion wiring 102 is arranged apart from the cell boundary BL1 between the first cell CL1 and the second cell CL2 in the cell width direction, the P + diffusion wiring 102 is related to the PMOS transistor MP23 of the first cell CLl. There is no need to divide up and down according to the separation rule with the diffusion wiring 102. Therefore, in the N well NW, a PMOS transistor having a large gate width can be formed near both ends in the cell width direction, so that the driving capability can be improved as compared with the conventional double height cell.

  Also, both ends of the diffusion wirings 102 and 107 arranged at the upper and lower ends of the second cell CL2 are separated from the cell frame. For this reason, even if the second cell CL2 is arranged upside down or upside down, a design rule error does not occur between the diffusion region of the transistor of the first cell CL1.

  According to this embodiment, the diffusion wiring arranged at both ends in the cell height direction of the single height cell has a layout configuration arranged with a predetermined interval from the cell frame in the cell width direction. The gate width of the transistor disposed in the well in the central portion can be expanded. Thereby, it becomes possible to improve the driving capability of the cell. In addition, the layout configuration shown in the present embodiment can be easily realized by modifying the conventional layout, and therefore can be handled with a small number of man-hours.

(Second Embodiment)
FIG. 4 is a plan view showing a layout configuration of a single height cell in the second embodiment. 4, the same components as those in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and detailed description thereof will be omitted here.

  The layout configuration of FIG. 4 is almost the same as that of FIG. 1, and the P + diffusion wiring 102 and the N + diffusion wiring 107 are arranged at a predetermined interval from the left and right ends of the cell frame in the cell width direction. However, the predetermined interval is different from that in FIG. In FIG. 4, the P + diffusion wiring 102 and the N + diffusion wiring 107 are arranged at a distance of 1/2 SP from the left and right ends of the cell frame. In addition, the arrangement position of the contact 103 connecting the P + diffusion wiring 102 and the power supply wiring 101 and the contact 108 connecting the N + diffusion wiring 107 and the ground wiring 106 is relative to the contact on the diffusion region constituting the transistor. It is shifted by half grid.

  As a result, the P + diffusion wiring 102 and the N + diffusion wiring 107 are larger than those in the first embodiment. For example, a diffusion wiring satisfying the minimum area rule of the diffusion wiring can be created even for a cell having a small cell width. . In addition, by shifting the contact of the diffusion wiring by a half grid, it is possible to sufficiently overlap the contact and the diffusion wiring, and it is possible to increase the number of contacts compared to the first embodiment.

  In the layout configuration of FIG. 4, a diffusion wiring 105 branched from the P + diffusion wiring 102 is connected to the source diffusion region of the PMOS transistor MP11, and a branch from the N + diffusion wiring 107 is connected to the source diffusion region of the NMOS transistor MN11. The diffused wiring 110 thus connected is connected. As described above, since the diffusion wiring can be used more for supplying the power source potential or the ground potential to the source diffusion region of the transistor than the layout configuration of FIG. 1, the first metal wiring layer is more effectively used as the wiring region. Can be used.

  FIG. 5 is a plan view showing the layout configuration of the double height cell in the present embodiment. In FIG. 5, the same components as those in FIG. 2 are denoted by the same reference numerals as those in FIG. 2, and detailed description thereof is omitted here.

  The layout configuration of FIG. 5 is almost the same as that of FIG. 2, but N + diffusion wirings 202 and 207 are different from FIG. Yes. In FIG. 5, N + diffusion wirings 202 and 207 are arranged at a distance of 1/2 SP from the left and right ends of the cell frame. In addition, the arrangement position of the contact 203 connecting the N + diffusion wiring 202 and the ground wiring 201 and the contact 208 connecting the N + diffusion wiring 207 and the ground wiring 206 is relative to the contact on the diffusion region constituting the transistor. It is shifted by half grid.

  6 is a plan view showing the layout configuration of the semiconductor integrated circuit device according to the present embodiment. The first cell CL1 has the same configuration as the double-height cell shown in FIG. 5, and the same configuration as the single-height cell shown in FIG. A configuration in which the second cell CL2 is disposed adjacent to each other in the cell width direction is shown.

  In the configuration of FIG. 6, the first and second cells CL1 and CL2 are arranged so that their lower ends are aligned, and the ground wiring 206 of the first cell CL1 and the ground wiring 106 of the second cell CL2 are in the cell width direction. They are arranged in a straight line and are connected to each other. However, the N + diffusion wiring 207 formed at the lower end of the first cell CL1 and the N + diffusion wiring 107 formed at the lower end of the second cell CL2 both have a predetermined distance (here) In this case, they are not connected because they are arranged at 1/2 SP).

  Further, the power supply wiring 211 is connected to the power supply wiring 101 of the second cell CL2 in the center portion in the cell height direction of the first cell CL1. In the first cell CL1, the drain diffusion region D_MP23 of the transistor MP23 extends in the cell width direction so that the extended region in the cell width direction of the power supply wiring 101 of the second cell CL2 extends across the cell height direction. It is formed opposite to the P + diffusion region 102. However, since the P + diffusion wiring 102 is arranged at a predetermined interval (1/2 SP in this case) from the cell frame, the interval between the drain diffusion region D_MP23 and the P + diffusion wiring 102 is the minimum of the separation rule between the diffusion regions. The value is SP. This is equal to the minimum distance SP between the drain diffusion region D_MP23 and the source diffusion region D_MP11 of the transistor MP11 facing the drain diffusion region D_MP23. Note that the drain diffusion region D_MP23 of the transistor MP23 is disposed at a distance of 1/2 SP from the cell frame. Further, the drain diffusion region D_MP23 of the transistor MP23 has no recess and is rectangular.

  In other words, since the P + diffusion wiring 102 is arranged apart from the cell boundary BL1 between the first cell CL1 and the second cell CL2 in the cell width direction, the P + diffusion wiring 102 is related to the PMOS transistor MP23 of the first cell CLl. There is no need to divide up and down according to the separation rule with the diffusion wiring 102. Therefore, in the N well NW, a PMOS transistor having a large gate width can be formed near both ends in the cell width direction, so that the driving capability can be improved as compared with the conventional double height cell.

  The distance between the contact 208 in the first cell CL1 closest to the cell boundary BL1 and the distance between the cell boundary BL1 and the contact 108 in the second cell CL2 closest to the cell boundary BL1 It is equal to the interval between BL1.

  FIG. 7 is a layout in which the third and fourth cells CL3 and CL4 having the same configuration as the single height cell shown in FIG. The third and fourth cells CL3 and CL4 are arranged adjacent to each other in the cell width direction, and adjacent to each other in the cell height direction so as to share the ground wirings 206 and 106 with the first and second cells CL1 and CL2. Are arranged. In the single-height cell of FIG. 4 and the double-height cell of FIG. 5, the contacts on the diffusion wirings at the upper and lower ends of the cell frame are present on the same grid.

  In the configuration of FIG. 7, the position of the cell boundary BL2 in the cell width direction of the third and fourth cells CL3 and CL4 is shifted from the position of the cell boundary BL1 in the cell width direction of the first and second cells CL1 and CL2. Has been. For this reason, the third cell CL3 is arranged so as to straddle the cell boundary BL1 between the first and second cells CL1 and CL2, and as a result, the space between the N + diffusion wirings 207 and 107 becomes smaller in the third cell CL3. It is filled with N + diffusion wiring 107a. Similarly, the space on the right side of the N + diffusion wiring 107 is filled with the N + diffusion wiring 107b of the fourth cell CL4. That is, the diffusion wirings 207, 107a, 107, and 107b formed below the ground wirings 206 and 106 are continuously arranged without gaps across the cell boundary BL1. Along with this, the number of contacts is also increasing. Therefore, the resistance value of the ground wirings 206 and 106 can be further reduced. Similarly, it is possible to further reduce the resistance value of the power supply wiring.

  FIG. 8 is a plan view showing another example of the layout configuration of the semiconductor integrated circuit device according to the present embodiment. The first cell CL1 has the same configuration as the double height cell shown in FIG. 5, and the double height cell has another configuration. The 2nd cell CL2A which is is shown adjacently arranged in the cell width direction.

  The second cell CL2A has a configuration in which the N well NW and the P well PW are interchanged with respect to the double height cell shown in FIG. That is, the power supply wiring 301 as the first metal wiring is arranged at the upper end in the cell height direction so as to extend in the cell width direction, and the P + diffusion wiring 302 as the first diffusion wiring is formed under the power supply wiring 301. ing. The power supply wiring 301 and the P + diffusion wiring 302 are connected via a contact 303. The P + diffusion wiring 302 is disposed at a distance of 1/2 SP from the left and right ends of the cell frame in the cell width direction. Further, the arrangement position of the contact 303 connecting the P + diffusion wiring 302 and the power supply wiring 301 is shifted by a half grid from the contact on the diffusion region constituting the transistor.

  Also in the configuration of FIG. 8, the interval between the drain diffusion region D_MP23 and the P + diffusion wiring 302 is the minimum value SP of the separation rule between the diffusion regions. In other words, the interval SP between the drain diffusion region D_MP23 and the P + diffusion wiring 302 is equal to the minimum interval between the drain diffusion region D_MP23 and the source diffusion region D_MP31 of the transistor MP31. That is, the same effect as the configuration of FIG. 6 can be obtained.

  In addition, the ground wiring 311 is connected to the ground wiring 206 as the third metal wiring of the first cell CL2 in the central portion of the second cell CL2A in the cell height direction. In the second cell CL2A, the source diffusion region D_MN31 of the transistor MN31 extends in the cell width direction so that the extension region in the cell width direction of the ground wiring 206 of the first cell CL1 extends across the cell height direction. It is formed opposite to the N + diffusion wiring 207 as the third diffusion wiring. However, since the N + diffusion wiring 207 is arranged 1/2 SP apart from the cell frame, the distance between the drain diffusion region D_MN31 as the second transistor diffusion region and the N + diffusion wiring 207 is determined by the separation rule between the diffusion regions. The minimum value SP is obtained. Therefore, it is not necessary to divide the NMOS transistor MN31 of the second cell CL2A vertically according to the separation rule with the N + diffusion wiring 207. Therefore, in the P well PW, an NMOS transistor having a large gate width can be formed near both ends in the cell width direction.

  In FIG. 8, the configuration in which the double-height cell is adjacent to the first cell CL1 has been described. However, a multi-height cell having a cell height M times the reference cell height (M is an integer of 2 or more) Even if they are adjacent to each other, a similar configuration can be realized. For example, the second cell CL2A in FIG. 8 has a cell height that is three times the reference cell height, and is a multi-height cell having an N well, a P well, an N well, and a P well in order from the top in the cell height direction. It may be.

(Third embodiment)
FIG. 9 is a diagram showing a part of the design flow of the semiconductor integrated circuit device according to the third embodiment. In FIG. 9, S11 is a layout design process, in which standard cell placement and wiring between standard cells are performed to create layout design data. Here, the standard cells are arranged with reference to the cell frame. S12 is a layer calculation processing step, and the layout design data created in the layout design step S12 is changed in consideration of the overlapping of calculation layers. The calculation layer is a concept on design data used for layout correction, and does not appear in an actual layout configuration. S13 is a layout verification step in which design rules and the like are checked for the post-computation layout data LD1.

  FIG. 10 is a diagram showing design data of a single height cell in the present embodiment. In FIG. 10, the P + diffusion wiring 102 and the N + diffusion wiring 107 extend to both ends in the cell width direction of the cell frame, and the P + diffusion wiring 102 and the N + diffusion wiring 107 are within a distance of 1/2 SP from both ends in the cell inner direction. The first calculation layer 401 having the same width as is arranged. The contacts 103 and 108 on the P + diffusion wiring 102 and the N + diffusion wiring 107 are arranged on the same grid as the contacts arranged in each diffusion region constituting the transistor. The second calculation layer 402 having the same shape as the contacts is disposed only on the contacts 103 and 108 at both ends in the cell width direction. Other than that, it is the same as the single height cell shown in FIG.

  FIG. 11 is a diagram showing design data of a double height cell in the present embodiment. In FIG. 11, the N + diffusion wirings 202 and 207 extend to both ends in the cell width direction of the cell frame. One calculation layer 401 is arranged. Further, the contacts 203 and 208 of the N + diffusion wirings 202 and 207 are arranged on the same grid as the contacts arranged in each diffusion region constituting the transistor. The second calculation layer 402 having the same shape as the contacts is disposed only on the contacts 203 and 208 at both ends in the cell width direction. Further, the third calculation layer 403 is disposed so as to extend outward from the cell frame at the center of the double height cell in the cell height direction. The third calculation layer 403 has the same width as the P + diffusion wiring of the single height cell, and the length is at least 1/2 SP or more. The rest is the same as the double height cell shown in FIG.

  FIG. 12 shows an example of the layout design data created in the layout design step S11. The single height cells CL2a, CL2b, and CL2c shown in FIG. 10 are arranged on both sides in the cell width direction of the double height cell CL1 shown in FIG. Indicates. The cells CL1, CL2a, CL2b, and CL2c are arranged so that the lower ends of the cell frames are aligned at the same position in the cell height direction.

  In the layer calculation processing step S12, the P + diffusion wiring and the N + diffusion wiring are deleted from the layout design data created in the layout design step S11 in a portion where the first calculation layer 401 and the third calculation layer 403 overlap. To do. Further, the contact is deleted from the portion where the second calculation layer 402 and the third calculation layer 403 overlap. In the layout design data of FIG. 12, with respect to the cell CL2a, the range 102_ra from the right end of the cell in the P + diffusion wiring 102a to the distance 1 / 2SP and the contact 103_4a closest to the right end of the cells among the contacts on the P + diffusion wiring 102a are deleted. The In addition, for the cell CL2b, the range 102_lb from the left end of the cell in the P + diffusion wiring 102b to the distance 1 / 2SP and the contact 103_1b closest to the left end of the cells among the contacts on the P + diffusion wiring 102b are deleted.

  FIG. 13 shows layout design data after the layout calculation processing step S12 is executed, and corresponds to a layout plan view of the semiconductor integrated circuit device according to the present embodiment. Note that wiring between the standard cells performed in the layout design step S11 is omitted. In FIG. 13, the distance between the diffusion region of the transistor MP21 of the cell CL1 and the P + diffusion wiring 102a of the cell CL2a and the distance between the diffusion region of the transistor MP23 of the cell CL1 and the P + diffusion wiring 102b of the cell CL2b are designed. It is the same as the minimum value SP of the rule. Therefore, for the cell CL1, it is not necessary to divide the transistors MP21 and MP23 arranged in the N well NW, and it can be configured as one transistor having a large gate width.

  In addition, between the right end of the P + diffusion wiring 102a in the cell CL2a and the rightmost contact 103_2a and between the left end of the P + diffusion wiring 102b in the cell CL2b and the leftmost contact 103_3b, sufficient Overlap ovl1 is secured. Thereby, it is possible to prevent the occurrence of a design rule error in the layout verification process S13.

  Further, N + diffusion wirings 107a, 207, 107b, and 107c arranged at the lower ends of the cells CL1, CL2a, CL2b, and CL2c are connected to each other. Further, P + diffusion wirings 102b and 102c arranged at the upper ends of the cells CL2b and CL2c are connected. That is, the number of contacts between the diffusion wiring region and the ground wiring or power supply wiring created by the diffusion wiring and the metal wiring is not reduced so much. As a result, a decrease in resistance value due to the supply of the ground potential or the power supply potential is suppressed.

  In the cell CL2b, an interval between the cell boundary with the cell CL1 and the contact closest to the cell boundary among the contacts arranged on the P + diffusion wiring 102b is the distance between the cell boundary and the N + diffusion wiring 107b. This is larger than the distance between the contacts arranged in the cell and those closest to the cell boundary. Similarly, in the cell CL2a, the distance between the cell boundary with the cell CL1 and the contact closest to the cell boundary among the contacts arranged on the P + diffusion wiring 102a is the cell boundary and the N + diffusion wiring 107a. It is larger than the distance between the contacts arranged above and the one closest to the cell boundary.

  Further, when viewed with reference to the position of the diffusion region of the transistor MP23 in the cell width direction, the contact disposed on the P + diffusion wiring 102b is closest to the diffusion region of the transistor MP23 in the cell width direction. The distance between the diffusion region of the transistor MP23 and the diffusion region of the transistor MP23 is the distance between the contact disposed on the N + diffusion wiring 107b and closest to the diffusion region of the transistor MP23 in the cell width direction. It is larger than the interval in the cell width direction. Similarly, when viewed with reference to the position of the diffusion region of the transistor MP21 in the cell width direction, the contact disposed on the P + diffusion wiring 102a is closest to the diffusion region of the transistor MP21 in the cell width direction. The space in the cell width direction between the transistor MP21 and the diffusion region of the transistor MP21 is the closest to the diffusion region of the transistor MP21 in the cell width direction among the contacts arranged on the N + diffusion wiring 107a. It is larger than the space | interval regarding the cell width direction between.

  FIG. 14 shows an example of the layout design data created in the layout design step S11. An N well NW and a P well PW are arranged on the right side in the cell width direction of the double height cell CL1 shown in FIG. The structure which has arrange | positioned double height cell CL2B of the replaced structure is shown. The cell CL2B is arranged so that the upper end of the cell CL2B matches the center of the cell CL1.

  In the layer calculation processing step S12, for the cell CL1, the range 207_r from the right end of the cell in the N + diffusion wiring 207 to the distance 1 / 2SP and the contact 208_4 closest to the right end of the cells among the contacts on the N + diffusion wiring 207 are deleted. . In addition, for the cell CL2B, the range 302_l from the left end of the cell to the distance 1 / 2SP in the P + diffusion wiring 302 and the contact 303_1 closest to the right end of the cells among the contacts on the P + diffusion wiring 302 are deleted.

  FIG. 15 shows layout design data after the layout calculation processing step S12 is executed, and corresponds to a layout plan view of the semiconductor integrated circuit device according to the present embodiment. Note that wiring between the standard cells performed in the layout design step S11 is omitted. In FIG. 15, the distance between the diffusion region of the transistor MP23 of the cell CL1 and the P + diffusion wiring 302 of the cell CL2B and the distance between the diffusion region of the transistor MN31 of the cell CL2B and the N + diffusion wiring 207 of the cell CL1 are designed. It is the same as the minimum value SP of the rule. Therefore, it is not necessary to divide the transistor arranged in the N well NW of the cell CL1 and the transistor arranged in the P well PW of the cell CL2B, and it can be configured as one transistor having a large gate width. is there.

  That is, the layout configurations of FIGS. 13 and 15 have the same characteristics as those of the first and second embodiments as a semiconductor integrated circuit device, and the same functions and effects can be obtained.

  As described above, according to the present embodiment, in the cell design data, the first calculation layers are provided at both the left and right ends of the diffusion wirings arranged at the upper and lower ends of the cell, and the first closest layer to the left and right ends of the diffusion wiring is provided. Two calculation layers are provided. For the double height cell, a third calculation layer extending from the cell frame to the left and right is provided at the center in the cell height direction. In the layout design data, the diffusion wiring is deleted for the portion where the first calculation layer and the third calculation layer overlap, and the contact is deleted for the portion where the second calculation layer and the third calculation layer overlap. The arithmetic processing to be performed is performed. By such a design flow, the transistor arranged in the center of the double height cell does not need to be divided according to the layout rule between the adjacent cells, and is configured as one transistor having a large gate width. Is possible.

  In the present embodiment, the contacts on the diffusion wiring are arranged on the same grid as the contacts on the transistor. However, for example, they may be shifted by a half grid. In this case, it is not necessary to use the second calculation layer for deleting the contact on the diffusion wiring, and the contact can be arranged on the average.

(Fourth embodiment)
Also in the fourth embodiment, it is assumed that the design flow of FIG. 9 is followed. That is, layout design data is created using design data of a cell having a calculation layer, and then the diffusion wiring is deleted at a portion where the first calculation layer and the third calculation layer overlap, and the second calculation layer And a calculation process for deleting the contact in a portion where the third calculation layer overlaps.

  FIG. 16 is a diagram showing design data of a single height cell in the present embodiment. The configuration of FIG. 16 is almost the same as that of FIG. However, dummy gates DG11 and DG13 are respectively disposed at both ends of the P well PW, and dummy gates DG12 and DG14 are respectively disposed at both ends of the N well NW.

  FIG. 17 is a diagram showing design data of a double height cell in the present embodiment. The configuration of FIG. 17 is almost the same as that of FIG. However, dummy gates DG291 and DG292 are disposed at both ends of the N well NW, dummy gates DG21 and DG25 are respectively disposed at both ends of the lower P well PW, and dummy gates are disposed at both ends of the upper P well PW. Gates DG24 and DG28 are respectively arranged. The dummy gates DG291 and DG292 extend over almost the entire range of the N well NW so as to straddle the center of the cell in the cell height direction. For this reason, the length of the dummy gates DG291 and DG292 in the cell height direction is longer than the gate width of the transistors MP21 and MP23.

  FIG. 18 shows layout design data created and modified in the layout design step S11 and the layer calculation processing step S12, and corresponds to a layout plan view of the semiconductor integrated circuit device according to this embodiment. 18 shows a configuration in which the single height cells CL2a, CL2b, and CL2c shown in FIG. 16 are arranged on both sides in the cell width direction of the double height cell CL1 shown in FIG. The cells CL1, CL2a, CL2b, and CL2c are arranged so that the lower ends of the cell frames are aligned at the same position in the cell height direction. Note that wiring between the standard cells performed in the layout design step S11 is omitted.

  In FIG. 18, as in FIG. 13, the layout calculation processing step S <b> 12 causes the distance from the right end of the cell in the P + diffusion wiring 102 a of the cell CL <b> 2 a to the distance ½ SP and the distance 1 The range up to / 2SP has been deleted. That is, there is a gap SP between the diffusion region of the transistor MP21 of the cell CL1 and the P + diffusion wiring 102a of the cell CL2a, and between the diffusion region of the transistor MP23 of the cell CL1 and the P + diffusion wiring 102b of the cell CL2b. Yes. Therefore, dummy gates DG291 and DG292 do not overlap with the diffusion wiring, and unnecessary transistors are not formed. As a result, variation in the shape of the gate electrode of the transistor of the cell CL1 can be suppressed.

  As described above, according to the present embodiment, dummy gates can be arranged on both sides of the transistor arranged in the center of the double height cell without forming unnecessary transistors. As a result, it is possible to suppress variation in the shape of the gate electrode of the transistor disposed at the center of the double height cell.

  In FIG. 18, a dummy gate is added to the configuration of FIG. 13 shown in the third embodiment. For example, the configuration shown in the first and second embodiments is different from the configuration shown in FIG. Of course, the same effect can be obtained even when a dummy gate is added. For example, in the layout of FIG. 3 or FIG. 6, a dummy gate is arranged to extend in the cell height direction while the diffusion region D_MP23 of the transistor MP23 of the cell CL1 and the P + diffusion wiring 102 of the cell CL2 face each other. May be. That is, in each of the above-described embodiments, no gate wiring is arranged between the rectangular transistor diffusion region of the multi-height cell and the diffusion wiring of the adjacent cell facing this, or one gate wiring is provided. Only arranged.

  In each of the above-described embodiments, the N-well is disposed in the center of the double-height cell, and the diffusion wiring of another cell is adjacently disposed in this N-well. However, the present invention is not limited to this. For example, even if the P well is arranged in the center of the double height cell and the diffusion wiring of another cell is arranged adjacent to the P well, the same as in the above embodiments It is applicable to.

  In each of the above-described embodiments, the configuration in which other cells are arranged adjacent to the double height cell has been described as an example. However, the configuration is not limited to the double height cell, and is N times the reference cell height (N is The above-described embodiments can be applied as long as other cells are arranged adjacent to a multi-height cell having a cell height of 2 or more. That is, the above-described embodiments are effective as long as the multi-height cell has a large well region and diffusion wirings of other cells are arranged adjacent to this well region.

  Further, in each of the above-described embodiments, the diffusion wirings arranged at the upper and lower ends of the cell have been described as an example connected to the source region of the transistor. However, for example, the diffusion wirings arranged at the upper and lower ends of the cell The same effect can be obtained even if the diffusion wiring is used to fix the substrate potential by reversing P / N. For example, FIG. 19 shows an example in which the diffusion wiring is changed to a configuration for fixing the substrate potential with respect to the single height cell of FIG. In FIG. 19, the N + diffusion wiring 102A is used for fixing the potential of the N well NW, and the P + diffusion wiring 107A is used for fixing the potential of the P well PW.

  According to the present invention, in the semiconductor integrated circuit device, it is possible to improve the driving capability of the transistor in the multi-height cell as compared with the conventional art. Therefore, for example, it is effective in reducing the area of LSI and improving the performance.

CL1 Double height cell (first cell)
CL2, CL2b Single height cell (second cell)
CL2A, CL2B Double height cell (second cell)
CL3 cell (third cell)
CL4 cell (4th cell)
101 Power supply wiring (first metal wiring)
102, 102b, 102A P + diffusion wiring (first diffusion wiring)
103 Contact 106 Ground wiring (second metal wiring)
107, 107A N + diffusion wiring (second diffusion wiring)
108 Contact 206 Ground wiring (third metal wiring)
207 N + diffusion wiring (third diffusion wiring)
208 Contact 301 Power supply wiring (first metal wiring)
302 P + diffusion wiring (first diffusion wiring)
303 Contact D_MP23 Source diffusion region of transistor MP23 (first transistor diffusion region)
D_MP11 Drain diffusion region (first diffusion region) of the transistor MP11
D_MN31 Source diffusion region of transistor MN11 (second transistor diffusion region)
DG291, DG292 Dummy gates BL1, BL2 Cell boundary

  The present invention relates to a semiconductor integrated circuit device having standard cells (hereinafter referred to as cells as appropriate), and more particularly to a layout having a configuration in which other cells are arranged adjacent to a so-called multi-height cell.

  As a method for designing a semiconductor integrated circuit, a design method using a standard cell is known. FIG. 20 shows an example of a standard cell layout, and a one-dot chain line indicates a cell frame. The length of the standard cell in the Y direction (y1 in FIG. 20) is called cell height, and the length in the X direction (x1 in FIG. 20) is called cell width. A cell having the same cell height as the reference height is called a single height cell. The cell width varies depending on the circuit configuration or the driving capability even in the same circuit configuration.

  In FIG. 20, the power supply wiring 501 and the ground wiring 506 formed in the metal wiring layer are arranged at the upper and lower ends of the cell so as to extend from the right end to the left end of the cell frame. PMOS transistors MP51 to MP53 are formed in the N well NW, and NMOS transistors MN51 to MN53 are formed in the P well PW. The P + diffusion wiring 502 formed of the P-type impurity diffusion region is disposed so as to overlap the power supply wiring 501 and is connected to the power supply wiring 501 through the contact 503. The N + diffusion wiring 507 formed of the N-type impurity diffusion region is disposed so as to overlap the ground wiring 506 and is connected to the ground wiring 506 through the contact 508.

  In FIG. 20, P + diffusion lines 504 and 505 branched from the P + diffusion line 502 are connected to the source diffusion region of the PMOS transistors MP51 to MP53, and N + diffusion lines 509 and 510 branched from the N + diffusion line 507 are The NMOS transistors MN51 to MN53 are connected to the source diffusion region. On the other hand, FIG. 21 shows a layout configuration in which the diffusion wirings 502A and 507A arranged under the power supply wiring 501 and the ground wiring 506 are used to fix the potentials of the wells NW and PW. The layout configuration shown in FIGS. 20 and 21 is well known as a general layout configuration.

  Usually, it is possible to reduce the area of the semiconductor integrated circuit by reducing the cell height of the standard cell. However, if a cell including a complicated circuit such as a flip-flop circuit or a cell having a large driving capability is created with a reference cell height, the cell width becomes very large, and conversely, the area may increase. is there.

  For this reason, a technique for creating such a cell as a multi-height cell whose cell height is N times the reference height (N is an integer of 2 or more) is known. For example, a double-height cell whose cell height is twice the reference height has a structure in which one of two single-height cells is inverted and integrated, and the central portion in the cell height direction. In FIG. 2, wells having a height approximately twice that of single-height cells are arranged. Since a transistor having a wide gate width can be arranged in this well, for example, a cell with high driving capability can be realized.

JP-A-7-249747 JP 2001-237328 A

  In recent semiconductor integrated circuit devices, the above-described multi-height cell is often arranged in addition to the single-height cell, and standard cells having a plurality of cell heights may be mixed. On the other hand, each standard cell used in the design needs to have a layout configuration so that the design rules can be observed even if any other standard cells are arranged adjacent to each other vertically or horizontally.

  FIG. 22 shows an example of a layout configuration in which a single height cell is arranged adjacent to a double height cell. CLa is a double-height cell in which a P-well PW, an N-well NW, and a P-well PW are arranged in order from the top in the cell height direction, and the height of the central N-well NW is N of a single-height cell. It is twice that of the well NW. CLb is a single height cell, and is arranged such that the lower end coincides with the cell CLa. That is, the ground wiring 606 and the N + diffusion wiring 607 of the cell CLa are connected to the ground wiring 506 and the N + diffusion wiring 507 of the cell CLb, respectively. Further, the layout of the diffusion region of the transistor MP63a of the cell CLa and the diffusion region of the transistor MP51 of the cell CLb are designed in advance so that the distance between them becomes the minimum value SP of the separation rule. In other words, the diffusion regions of the transistors MP63a and MP51 are each spaced apart by 1/2 SP from the cell frame.

  In the N well NW of the double height cell CLa, since no diffusion wiring is disposed under the power supply wiring 611, a large diffusion region of the transistor can be taken. In the layout of FIG. 22, a transistor MP62 having a large gate width and a large driving capability is formed.

  On the other hand, at the upper end of the single height cell CLb, the P + diffusion wiring 502 extends to both ends of the cell frame. For this reason, in the double height cell CLa, the diffusion region formed in the N well NW must be arranged at a distance SP or more away from the left end of the P + diffusion wiring 502 in order to observe the separation rule with the P + diffusion wiring 502. Don't be. Therefore, with respect to the gate wiring GA63, it is necessary to divide the diffusion region into two in the cell height direction, so that a single transistor with a large gate width cannot be formed, and two transistors MP63a and MP63b are formed. Regarding the gate wiring GA61, for the same reason, the diffusion region is divided into two in the cell height direction, and two transistors MP61a and MP61b are formed.

  In FIG. 22, the diffusion region of the entire N well NW of the double height cell CLa has a shape that is further recessed from the P + diffusion wiring 502 than the distance SP. The minimum dimension of the diffusion region with respect to the gate electrode in the transistor This is because there are restrictions by design rules.

  As described above, in consideration of the layout configuration of adjacent cells, in the wide well at the center of the double height cell, the transistors arranged near both ends in the cell width direction can have a sufficiently wide gate width according to the design rule. Can not. For this reason, the improvement of the driving capability of the transistor, which is one of the purposes of using the double height cell, cannot always be sufficiently realized. In particular, since the PMOS transistor has a low current capability, in order to obtain a large driving capability with a small area, it is desirable to form a transistor having a large gate width by utilizing a region where the PMOS transistor can be formed as much as possible.

  In a fine process, a dummy gate may be arranged on the cell boundary so that the gate electrodes are arranged at an equal pitch in order to suppress variation in the shape of the gate electrode of the transistor. For example, in FIG. 22, it is necessary to arrange dummy gates at the cell boundaries at the same pitch as the gates GA61 to GA63. However, if the dummy gate is arranged at the cell boundary with the layout of FIG. 22, there arises a problem that an unnecessary transistor is formed by the P + diffusion wiring 502 and the dummy gate.

  The problems described above are not limited to double-height cells, but may occur if the multi-height cell has a wide well and a layout configuration in which the diffusion wiring of other cells can be adjacent to the well. It is a problem.

  In view of the above-described problems, the present invention provides a layout configuration that can sufficiently improve the drive capability of a transistor in a multi-height cell in a semiconductor integrated circuit device having a configuration in which other cells are arranged adjacent to the multi-height cell. Is to provide.

  In one aspect of the present invention, in the semiconductor integrated circuit device in which a plurality of cells are arranged, the plurality of cells have a cell height that is N times the reference cell height (N is an integer of 2 or more). And a second cell disposed adjacent to the first cell in the cell width direction, and the second cell extends in the cell width direction at one end in the cell height direction. A first metal wiring arranged in this manner, and an impurity diffusion region formed so as to extend in the cell width direction under the first metal wiring, and is connected to the first metal wiring through a contact. The first cell is opposed to the first diffusion wiring in the cell width direction, and is formed so as to straddle the extension region in the cell width direction of the first metal wiring in the cell height direction. And tiger Comprising a first transistor diffusion region constituting the register, the first diffusion line, in a cell width direction, is spaced apart from the cell boundary between the first cell and the second cell.

  According to this aspect, the second cell arranged adjacent to the first cell which is a multi-height cell has the first metal wiring extending in the cell width direction at one end in the cell height direction, and the cell width direction under the metal wiring. And a first diffusion wiring composed of an impurity diffusion region formed so as to extend in the direction. The first cell includes a first transistor diffusion region formed so as to straddle an extension region in the cell width direction of the first metal wiring of the second cell in the cell height direction. The first diffusion wiring of the second cell facing the first transistor diffusion region is separated from the cell boundary between the first cell and the second cell in the cell width direction. For this reason, the separation rule between the first transistor diffusion region of the first cell and the diffusion wiring of the second cell is reliably maintained, and it is not necessary to divide the first transistor diffusion region. Therefore, a transistor having a large gate width can be formed without being influenced by the layout even in the vicinity of other adjacent cells.

  According to the present invention, in a multi-height cell, a transistor having a large gate width can be formed even in the vicinity of other adjacent cells. As a result, the driving capability of the transistor in the multi-height cell can be improved as compared with the prior art.

It is a top view which shows the layout structure of the single height cell in 1st Embodiment. It is a top view which shows the layout structure of the double height cell in 1st Embodiment. 1 is a plan view showing a layout configuration of a semiconductor integrated circuit device according to a first embodiment. It is a top view which shows the layout structure of the single height cell in 2nd Embodiment. It is a top view which shows the layout structure of the double height cell in 2nd Embodiment. It is a top view which shows the layout structure of the semiconductor integrated circuit device which concerns on 2nd Embodiment. It is a top view which shows the layout structure of the semiconductor integrated circuit device which concerns on 2nd Embodiment. It is a top view which shows the other example of the layout structure of the semiconductor integrated circuit device which concerns on 2nd this embodiment. It is a figure which shows a part of design flow of the semiconductor integrated circuit device which concerns on 3rd Embodiment. It is a figure which shows the design data of the single height cell in 3rd Embodiment. It is a figure which shows the design data of the double height cell in 3rd this embodiment. It is an example of the layout design data created in the layout design process S11 of FIG. It is a top view which shows the layout structure of the semiconductor integrated circuit device which concerns on 3rd Embodiment. It is an example of the layout design data created in the layout design process S11 of FIG. It is a top view which shows the layout structure of the semiconductor integrated circuit device which concerns on 3rd Embodiment. It is a figure which shows the design data of the single height cell in 4th Embodiment. It is a figure which shows the design data of the double height cell in 4th this embodiment. It is a top view which shows the layout structure of the semiconductor integrated circuit device which concerns on 4th Embodiment. It is a top view which shows the other example of the layout structure of the single height cell in embodiment. It is a top view which shows the layout structure of a general single height cell. It is a top view which shows the layout structure of a general single height cell. It is a figure for demonstrating the subject of this invention.

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
FIG. 1 is a plan view showing a layout configuration of a single height cell in the first embodiment. A single height cell is a cell having a reference cell height. In FIG. 1, the alternate long and short dash line indicates a cell frame. The horizontal direction (X direction) in the drawing is the cell width direction, and the vertical direction (Y direction) in the drawing is the cell height direction (the same applies to the following drawings).

  In FIG. 1, MP11 to MP13 are PMOS transistors formed in the N well NW, and MN11 to MN13 are NMOS transistors formed in the P well PW. 101 is a power supply wiring, and 106 is a ground wiring, both of which are formed in the first metal wiring layer. The power supply wiring 101 and the ground wiring 106 are respectively arranged at both ends in the cell height direction of the single height cell so as to extend in the cell width direction from the right end to the left end of the cell frame. The center line of the power supply wiring 101 coincides with the upper end of the cell frame, and the center line of the ground wiring coincides with the lower end of the cell frame. Reference numeral 102 denotes a P + diffusion wiring formed of a P-type impurity diffusion region formed so as to extend in the cell width direction below the power supply wiring 101, and is connected to the power supply wiring 101 through a contact 103. Reference numeral 107 denotes an N + diffusion wiring composed of an N-type impurity diffusion region formed so as to extend in the cell width direction below the ground wiring 106, and is connected to the ground wiring 106 via a contact 108.

  In the configuration of FIG. 1, the P + diffusion wiring 102 and the N + diffusion wiring 107 are arranged with a predetermined interval from the left and right ends of the cell frame in the cell width direction. Here, an interval corresponding to the sum of the width of one contact and the interval between contacts (that is, one grid in the contact arrangement) is provided. Therefore, the wiring 111 branched from the power supply wiring 101 is connected to the source diffusion region of the PMOS transistor MP11 via a contact, and the wiring 112 branched from the ground wiring 106 is connected to the source diffusion region of the NMOS transistor MN11. Connected through contacts. Although the wirings 111 and 112 are formed in the first metal wiring layer, they are arranged in limited areas at the upper left and lower left of the cell frame, so that the influence on the use of the first metal wiring layer as the wiring area is not affected. Limited. The P + diffusion wiring 104 branched from the P + diffusion wiring 102 is connected to the source diffusion regions of the PMOS transistors MP12 and MP13, and the N + diffusion branching from the N + diffusion wiring 107 is connected to the source diffusion regions of the NMOS transistors MN12 and MN13. A wiring 109 is connected.

  FIG. 2 is a plan view showing the layout configuration of the double height cell in the present embodiment. A double-height cell is a cell having a cell height that is twice the reference cell height.

  In FIG. 2, MP21 to MP23 are PMOS transistors formed in the N well NW, and MN21 to MN23 and MN24 to MN26 are NMOS transistors formed in the P well PW. In the configuration of FIG. 2, the PMOS transistors MP21 and MP23 arranged in the N well NW are not divided in the cell height direction, and the outer shape of the entire diffusion region constituting the PMOS transistors MP21 to MP23 has a recess. It is rectangular. The power supply wiring 211 is formed in the first metal wiring layer, and is arranged so as to extend in the cell width direction from the right end to the left end of the cell frame at the center in the cell height direction of the double height cell. A line branched from the power supply line 211 is connected to the source diffusion region of the PMOS transistors MP21 to MP23 through a contact.

  The ground wirings 201 and 206 are formed in the first metal wiring layer, and are arranged at both ends in the cell height direction of the double height cell so as to extend in the cell width direction from the right end to the left end of the cell frame. The center lines of the ground wires 201 and 206 coincide with the upper end and the lower end of the cell frame, respectively. Reference numeral 202 denotes an N + diffusion wiring composed of an N-type impurity diffusion region formed so as to extend in the cell width direction below the ground wiring 201, and is connected to the ground wiring 201 through a contact 203. Reference numeral 207 denotes an N + diffusion wiring made of an N-type impurity diffusion region formed so as to extend in the cell width direction under the ground wiring 206, and is connected to the ground wiring 206 through a contact 208. N + diffusion wirings 204 and 205 branched from the N + diffusion wiring 202 are connected to the source diffusion regions of the transistors MN24 to MN26, and N + diffusion wirings 209 and 210 branched from the N + diffusion wiring 207 are the source diffusion regions of the transistors MN21 to MN23. Connected with.

  FIG. 3 is a plan view showing a layout configuration of the semiconductor integrated circuit device according to the present embodiment. The first cell CL1 has the same configuration as the double height cell shown in FIG. 2, and the same configuration as the single height cell shown in FIG. A configuration in which the second cell CL2 is disposed adjacent to each other in the cell width direction is shown.

  In the configuration of FIG. 3, the first and second cells CL1, CL2 are arranged so that the lower ends thereof are aligned, and the ground wiring 206 as the third metal wiring of the first cell CL1 and the second metal wiring of the second cell CL2 are arranged. Are arranged so as to be in a straight line in the cell width direction and are connected to each other. However, the N + diffusion wiring 207 formed at the lower end of the first cell CL1 and the N + diffusion wiring 107 formed at the lower end of the second cell CL2 are such that the N + diffusion wiring 107 as the second diffusion wiring is predetermined from the cell frame. Since they are arranged at an interval (here, 1 grit), they are not connected.

  Further, in the central portion of the first cell CL1 in the cell height direction, the power supply wiring 211 is connected to the power supply wiring 101 as the first metal wiring of the second cell CL2. In the first cell CL1, the drain diffusion region D_MP23 of the transistor MP23 extends in the cell width direction so that the extended region in the cell width direction of the power supply wiring 101 of the second cell CL2 extends across the cell height direction. Formed opposite to the P + diffusion region 102. However, since the P + diffusion wiring 102 as the first diffusion wiring is arranged at a predetermined interval (here, 1 grit) from the cell frame, the drain diffusion region D_MP23 and the P + diffusion wiring 102 as the first transistor diffusion region are arranged. Is SP1 which is larger than the minimum value SP of the separation rule between diffusion regions. Note that the drain diffusion region D_MP23 of the transistor MP23 is disposed at a distance of 1/2 SP from the cell frame. An interval SP1 between the drain diffusion region D_MP23 and the P + diffusion wiring 102 is larger than a minimum interval SP between the drain diffusion region D_MP23 and the source diffusion region D_MP11 as the first diffusion region of the transistor MP11 facing the drain diffusion region D_MP23. Further, the drain diffusion region D_MP23 of the transistor MP23 has no recess and is rectangular.

  In other words, since the P + diffusion wiring 102 is arranged apart from the cell boundary BL1 between the first cell CL1 and the second cell CL2 in the cell width direction, the P + diffusion wiring 102 is related to the PMOS transistor MP23 of the first cell CLl. There is no need to divide up and down according to the separation rule with the diffusion wiring 102. Therefore, in the N well NW, a PMOS transistor having a large gate width can be formed near both ends in the cell width direction, so that the driving capability can be improved as compared with the conventional double height cell.

  Also, both ends of the diffusion wirings 102 and 107 arranged at the upper and lower ends of the second cell CL2 are separated from the cell frame. For this reason, even if the second cell CL2 is arranged upside down or upside down, a design rule error does not occur between the diffusion region of the transistor of the first cell CL1.

  According to this embodiment, the diffusion wiring arranged at both ends in the cell height direction of the single height cell has a layout configuration arranged with a predetermined interval from the cell frame in the cell width direction. The gate width of the transistor disposed in the well in the central portion can be expanded. Thereby, it becomes possible to improve the driving capability of the cell. In addition, the layout configuration shown in the present embodiment can be easily realized by modifying the conventional layout, and therefore can be handled with a small number of man-hours.

(Second Embodiment)
FIG. 4 is a plan view showing a layout configuration of a single height cell in the second embodiment. 4, the same components as those in FIG. 1 are denoted by the same reference numerals as those in FIG. 1, and detailed description thereof will be omitted here.

  The layout configuration of FIG. 4 is almost the same as that of FIG. 1, and the P + diffusion wiring 102 and the N + diffusion wiring 107 are arranged at a predetermined interval from the left and right ends of the cell frame in the cell width direction. However, the predetermined interval is different from that in FIG. In FIG. 4, the P + diffusion wiring 102 and the N + diffusion wiring 107 are arranged at a distance of 1/2 SP from the left and right ends of the cell frame. In addition, the arrangement position of the contact 103 connecting the P + diffusion wiring 102 and the power supply wiring 101 and the contact 108 connecting the N + diffusion wiring 107 and the ground wiring 106 is relative to the contact on the diffusion region constituting the transistor. It is shifted by half grid.

  As a result, the P + diffusion wiring 102 and the N + diffusion wiring 107 are larger than those in the first embodiment. For example, a diffusion wiring satisfying the minimum area rule of the diffusion wiring can be created even for a cell having a small cell width. . In addition, by shifting the contact of the diffusion wiring by a half grid, it is possible to sufficiently overlap the contact and the diffusion wiring, and it is possible to increase the number of contacts compared to the first embodiment.

  In the layout configuration of FIG. 4, a diffusion wiring 105 branched from the P + diffusion wiring 102 is connected to the source diffusion region of the PMOS transistor MP11, and a branch from the N + diffusion wiring 107 is connected to the source diffusion region of the NMOS transistor MN11. The diffused wiring 110 thus connected is connected. As described above, since the diffusion wiring can be used more for supplying the power source potential or the ground potential to the source diffusion region of the transistor than the layout configuration of FIG. 1, the first metal wiring layer is more effectively used as the wiring region. Can be used.

  FIG. 5 is a plan view showing the layout configuration of the double height cell in the present embodiment. In FIG. 5, the same components as those in FIG. 2 are denoted by the same reference numerals as those in FIG. 2, and detailed description thereof is omitted here.

  The layout configuration of FIG. 5 is almost the same as that of FIG. 2, but N + diffusion wirings 202 and 207 are different from FIG. Yes. In FIG. 5, N + diffusion wirings 202 and 207 are arranged at a distance of 1/2 SP from the left and right ends of the cell frame. In addition, the arrangement position of the contact 203 connecting the N + diffusion wiring 202 and the ground wiring 201 and the contact 208 connecting the N + diffusion wiring 207 and the ground wiring 206 is relative to the contact on the diffusion region constituting the transistor. It is shifted by half grid.

  6 is a plan view showing the layout configuration of the semiconductor integrated circuit device according to the present embodiment. The first cell CL1 has the same configuration as the double-height cell shown in FIG. 5, and the same configuration as the single-height cell shown in FIG. A configuration in which the second cell CL2 is disposed adjacent to each other in the cell width direction is shown.

  In the configuration of FIG. 6, the first and second cells CL1 and CL2 are arranged so that their lower ends are aligned, and the ground wiring 206 of the first cell CL1 and the ground wiring 106 of the second cell CL2 are in the cell width direction. They are arranged in a straight line and are connected to each other. However, the N + diffusion wiring 207 formed at the lower end of the first cell CL1 and the N + diffusion wiring 107 formed at the lower end of the second cell CL2 both have a predetermined distance (here) In this case, they are not connected because they are arranged at 1/2 SP).

  Further, the power supply wiring 211 is connected to the power supply wiring 101 of the second cell CL2 in the center portion in the cell height direction of the first cell CL1. In the first cell CL1, the drain diffusion region D_MP23 of the transistor MP23 extends in the cell width direction so that the extended region in the cell width direction of the power supply wiring 101 of the second cell CL2 extends across the cell height direction. It is formed opposite to the P + diffusion region 102. However, since the P + diffusion wiring 102 is arranged at a predetermined interval (1/2 SP in this case) from the cell frame, the interval between the drain diffusion region D_MP23 and the P + diffusion wiring 102 is the minimum of the separation rule between the diffusion regions. The value is SP. This is equal to the minimum distance SP between the drain diffusion region D_MP23 and the source diffusion region D_MP11 of the transistor MP11 facing the drain diffusion region D_MP23. Note that the drain diffusion region D_MP23 of the transistor MP23 is disposed at a distance of 1/2 SP from the cell frame. Further, the drain diffusion region D_MP23 of the transistor MP23 has no recess and is rectangular.

  In other words, since the P + diffusion wiring 102 is arranged apart from the cell boundary BL1 between the first cell CL1 and the second cell CL2 in the cell width direction, the P + diffusion wiring 102 is related to the PMOS transistor MP23 of the first cell CLl. There is no need to divide up and down according to the separation rule with the diffusion wiring 102. Therefore, in the N well NW, a PMOS transistor having a large gate width can be formed near both ends in the cell width direction, so that the driving capability can be improved as compared with the conventional double height cell.

  The distance between the contact 208 in the first cell CL1 closest to the cell boundary BL1 and the distance between the cell boundary BL1 and the contact 108 in the second cell CL2 closest to the cell boundary BL1 It is equal to the interval between BL1.

  FIG. 7 is a layout in which the third and fourth cells CL3 and CL4 having the same configuration as the single height cell shown in FIG. The third and fourth cells CL3 and CL4 are arranged adjacent to each other in the cell width direction, and adjacent to each other in the cell height direction so as to share the ground wirings 206 and 106 with the first and second cells CL1 and CL2. Are arranged. In the single-height cell of FIG. 4 and the double-height cell of FIG. 5, the contacts on the diffusion wirings at the upper and lower ends of the cell frame are present on the same grid.

  In the configuration of FIG. 7, the position of the cell boundary BL2 in the cell width direction of the third and fourth cells CL3 and CL4 is shifted from the position of the cell boundary BL1 in the cell width direction of the first and second cells CL1 and CL2. Has been. For this reason, the third cell CL3 is arranged so as to straddle the cell boundary BL1 between the first and second cells CL1 and CL2, and as a result, the space between the N + diffusion wirings 207 and 107 becomes smaller in the third cell CL3. It is filled with N + diffusion wiring 107a. Similarly, the space on the right side of the N + diffusion wiring 107 is filled with the N + diffusion wiring 107b of the fourth cell CL4. That is, the diffusion wirings 207, 107a, 107, and 107b formed below the ground wirings 206 and 106 are continuously arranged without gaps across the cell boundary BL1. Along with this, the number of contacts is also increasing. Therefore, the resistance value of the ground wirings 206 and 106 can be further reduced. Similarly, it is possible to further reduce the resistance value of the power supply wiring.

  FIG. 8 is a plan view showing another example of the layout configuration of the semiconductor integrated circuit device according to the present embodiment. The first cell CL1 has the same configuration as the double height cell shown in FIG. 5, and the double height cell has another configuration. The 2nd cell CL2A which is is shown adjacently arranged in the cell width direction.

  The second cell CL2A has a configuration in which the N well NW and the P well PW are interchanged with respect to the double height cell shown in FIG. That is, the power supply wiring 301 as the first metal wiring is arranged at the upper end in the cell height direction so as to extend in the cell width direction, and the P + diffusion wiring 302 as the first diffusion wiring is formed under the power supply wiring 301. ing. The power supply wiring 301 and the P + diffusion wiring 302 are connected via a contact 303. The P + diffusion wiring 302 is disposed at a distance of 1/2 SP from the left and right ends of the cell frame in the cell width direction. Further, the arrangement position of the contact 303 connecting the P + diffusion wiring 302 and the power supply wiring 301 is shifted by a half grid from the contact on the diffusion region constituting the transistor.

  Also in the configuration of FIG. 8, the interval between the drain diffusion region D_MP23 and the P + diffusion wiring 302 is the minimum value SP of the separation rule between the diffusion regions. In other words, the interval SP between the drain diffusion region D_MP23 and the P + diffusion wiring 302 is equal to the minimum interval between the drain diffusion region D_MP23 and the source diffusion region D_MP31 of the transistor MP31. That is, the same effect as the configuration of FIG. 6 can be obtained.

Further, the ground wiring 311 is connected to the ground wiring 206 as the third metal wiring of the first cell CL1 at the center portion in the cell height direction of the second cell CL2A. And in the second cell CL2a, so as to straddle the extended area in the cell width direction of the ground wire 206 of the first cell CL1 cell height direction, the source diffusion region D_MN31 transistor MN31 is in the cell width direction of the first cell CL1 It is formed opposite to the N + diffusion wiring 207 as the third diffusion wiring. However, since the N + diffusion wiring 207 is arranged 1/2 SP apart from the cell frame, the distance between the drain diffusion region D_MN31 as the second transistor diffusion region and the N + diffusion wiring 207 is determined by the separation rule between the diffusion regions. The minimum value SP is obtained. Therefore, it is not necessary to divide the NMOS transistor MN31 of the second cell CL2A vertically according to the separation rule with the N + diffusion wiring 207. Therefore, in the P well PW, an NMOS transistor having a large gate width can be formed near both ends in the cell width direction.

  In FIG. 8, the configuration in which the double-height cell is adjacent to the first cell CL1 has been described. However, a multi-height cell having a cell height M times the reference cell height (M is an integer of 2 or more) Even if they are adjacent to each other, a similar configuration can be realized. For example, the second cell CL2A in FIG. 8 has a cell height that is three times the reference cell height, and is a multi-height cell having an N well, a P well, an N well, and a P well in order from the top in the cell height direction. It may be.

(Third embodiment)
FIG. 9 is a diagram showing a part of the design flow of the semiconductor integrated circuit device according to the third embodiment. In FIG. 9, S11 is a layout design process, in which standard cell placement and wiring between standard cells are performed to create layout design data. Here, the standard cells are arranged with reference to the cell frame. S12 is a layer calculation processing step, and the layout design data created in the layout design step S12 is changed in consideration of the overlapping of calculation layers. The calculation layer is a concept on design data used for layout correction, and does not appear in an actual layout configuration. S13 is a layout verification step in which design rules and the like are checked for the post-computation layout data LD1.

  FIG. 10 is a diagram showing design data of a single height cell in the present embodiment. In FIG. 10, the P + diffusion wiring 102 and the N + diffusion wiring 107 extend to both ends in the cell width direction of the cell frame, and the P + diffusion wiring 102 and the N + diffusion wiring 107 are within a distance of 1/2 SP from both ends in the cell inner direction. The first calculation layer 401 having the same width as is arranged. The contacts 103 and 108 on the P + diffusion wiring 102 and the N + diffusion wiring 107 are arranged on the same grid as the contacts arranged in each diffusion region constituting the transistor. The second calculation layer 402 having the same shape as the contacts is disposed only on the contacts 103 and 108 at both ends in the cell width direction. Other than that, it is the same as the single height cell shown in FIG.

  FIG. 11 is a diagram showing design data of a double height cell in the present embodiment. In FIG. 11, the N + diffusion wirings 202 and 207 extend to both ends in the cell width direction of the cell frame. One calculation layer 401 is arranged. Further, the contacts 203 and 208 of the N + diffusion wirings 202 and 207 are arranged on the same grid as the contacts arranged in each diffusion region constituting the transistor. The second calculation layer 402 having the same shape as the contacts is disposed only on the contacts 203 and 208 at both ends in the cell width direction. Further, the third calculation layer 403 is disposed so as to extend outward from the cell frame at the center of the double height cell in the cell height direction. The third calculation layer 403 has the same width as the P + diffusion wiring of the single height cell, and the length is at least 1/2 SP or more. The rest is the same as the double height cell shown in FIG.

  FIG. 12 shows an example of the layout design data created in the layout design step S11. The single height cells CL2a, CL2b, and CL2c shown in FIG. 10 are arranged on both sides in the cell width direction of the double height cell CL1 shown in FIG. Indicates. The cells CL1, CL2a, CL2b, and CL2c are arranged so that the lower ends of the cell frames are aligned at the same position in the cell height direction.

  In the layer calculation processing step S12, the P + diffusion wiring and the N + diffusion wiring are deleted from the layout design data created in the layout design step S11 in a portion where the first calculation layer 401 and the third calculation layer 403 overlap. To do. Further, the contact is deleted from the portion where the second calculation layer 402 and the third calculation layer 403 overlap. In the layout design data of FIG. 12, with respect to the cell CL2a, the range 102_ra from the right end of the cell in the P + diffusion wiring 102a to the distance 1 / 2SP and the contact 103_4a closest to the right end of the cells among the contacts on the P + diffusion wiring 102a are deleted. The In addition, for the cell CL2b, the range 102_lb from the left end of the cell in the P + diffusion wiring 102b to the distance 1 / 2SP and the contact 103_1b closest to the left end of the cells among the contacts on the P + diffusion wiring 102b are deleted.

  FIG. 13 shows layout design data after the layout calculation processing step S12 is executed, and corresponds to a layout plan view of the semiconductor integrated circuit device according to the present embodiment. Note that wiring between the standard cells performed in the layout design step S11 is omitted. In FIG. 13, the distance between the diffusion region of the transistor MP21 of the cell CL1 and the P + diffusion wiring 102a of the cell CL2a and the distance between the diffusion region of the transistor MP23 of the cell CL1 and the P + diffusion wiring 102b of the cell CL2b are designed. It is the same as the minimum value SP of the rule. Therefore, for the cell CL1, it is not necessary to divide the transistors MP21 and MP23 arranged in the N well NW, and it can be configured as one transistor having a large gate width.

  In addition, between the right end of the P + diffusion wiring 102a in the cell CL2a and the rightmost contact 103_2a and between the left end of the P + diffusion wiring 102b in the cell CL2b and the leftmost contact 103_3b, sufficient Overlap ovl1 is secured. Thereby, it is possible to prevent the occurrence of a design rule error in the layout verification process S13.

  Further, N + diffusion wirings 107a, 207, 107b, and 107c arranged at the lower ends of the cells CL1, CL2a, CL2b, and CL2c are connected to each other. Further, P + diffusion wirings 102b and 102c arranged at the upper ends of the cells CL2b and CL2c are connected. That is, the number of contacts between the diffusion wiring region and the ground wiring or power supply wiring created by the diffusion wiring and the metal wiring is not reduced so much. As a result, a decrease in resistance value due to the supply of the ground potential or the power supply potential is suppressed.

  In the cell CL2b, an interval between the cell boundary with the cell CL1 and the contact closest to the cell boundary among the contacts arranged on the P + diffusion wiring 102b is the distance between the cell boundary and the N + diffusion wiring 107b. This is larger than the distance between the contacts arranged in the cell and those closest to the cell boundary. Similarly, in the cell CL2a, the distance between the cell boundary with the cell CL1 and the contact closest to the cell boundary among the contacts arranged on the P + diffusion wiring 102a is the cell boundary and the N + diffusion wiring 107a. It is larger than the distance between the contacts arranged above and the one closest to the cell boundary.

  Further, when viewed with reference to the position of the diffusion region of the transistor MP23 in the cell width direction, the contact disposed on the P + diffusion wiring 102b is closest to the diffusion region of the transistor MP23 in the cell width direction. The distance between the diffusion region of the transistor MP23 and the diffusion region of the transistor MP23 is the distance between the contact disposed on the N + diffusion wiring 107b and closest to the diffusion region of the transistor MP23 in the cell width direction. It is larger than the interval in the cell width direction. Similarly, when viewed with reference to the position of the diffusion region of the transistor MP21 in the cell width direction, the contact disposed on the P + diffusion wiring 102a is closest to the diffusion region of the transistor MP21 in the cell width direction. The space in the cell width direction between the transistor MP21 and the diffusion region of the transistor MP21 is the closest to the diffusion region of the transistor MP21 in the cell width direction among the contacts arranged on the N + diffusion wiring 107a. It is larger than the space | interval regarding the cell width direction between.

  FIG. 14 shows an example of the layout design data created in the layout design step S11. An N well NW and a P well PW are arranged on the right side in the cell width direction of the double height cell CL1 shown in FIG. The structure which has arrange | positioned double height cell CL2B of the replaced structure is shown. The cell CL2B is arranged so that the upper end of the cell CL2B matches the center of the cell CL1.

In the layer calculation processing step S12, for the cell CL1, the range 207_r from the right end of the cell in the N + diffusion wiring 207 to the distance 1 / 2SP and the contact 208_4 closest to the right end of the cells among the contacts on the N + diffusion wiring 207 are deleted. . In addition, for the cell CL2B, the range 302_1 from the left end of the cell to the distance 1 / 2SP in the P + diffusion wiring 302 and the contact 303_1 closest to the left end of the cells among the contacts on the P + diffusion wiring 302 are deleted.

  FIG. 15 shows layout design data after the layout calculation processing step S12 is executed, and corresponds to a layout plan view of the semiconductor integrated circuit device according to the present embodiment. Note that wiring between the standard cells performed in the layout design step S11 is omitted. In FIG. 15, the distance between the diffusion region of the transistor MP23 of the cell CL1 and the P + diffusion wiring 302 of the cell CL2B and the distance between the diffusion region of the transistor MN31 of the cell CL2B and the N + diffusion wiring 207 of the cell CL1 are designed. It is the same as the minimum value SP of the rule. Therefore, it is not necessary to divide the transistor arranged in the N well NW of the cell CL1 and the transistor arranged in the P well PW of the cell CL2B, and it can be configured as one transistor having a large gate width. is there.

  That is, the layout configurations of FIGS. 13 and 15 have the same characteristics as those of the first and second embodiments as a semiconductor integrated circuit device, and the same functions and effects can be obtained.

  As described above, according to the present embodiment, in the cell design data, the first calculation layers are provided at both the left and right ends of the diffusion wirings arranged at the upper and lower ends of the cell, and the first closest layer to the left and right ends of the diffusion wiring is provided. Two calculation layers are provided. For the double height cell, a third calculation layer extending from the cell frame to the left and right is provided at the center in the cell height direction. In the layout design data, the diffusion wiring is deleted for the portion where the first calculation layer and the third calculation layer overlap, and the contact is deleted for the portion where the second calculation layer and the third calculation layer overlap. The arithmetic processing to be performed is performed. By such a design flow, the transistor arranged in the center of the double height cell does not need to be divided according to the layout rule between the adjacent cells, and is configured as one transistor having a large gate width. Is possible.

  In the present embodiment, the contacts on the diffusion wiring are arranged on the same grid as the contacts on the transistor. However, for example, they may be shifted by a half grid. In this case, it is not necessary to use the second calculation layer for deleting the contact on the diffusion wiring, and the contact can be arranged on the average.

(Fourth embodiment)
Also in the fourth embodiment, it is assumed that the design flow of FIG. 9 is followed. That is, layout design data is created using design data of a cell having a calculation layer, and then the diffusion wiring is deleted at a portion where the first calculation layer and the third calculation layer overlap, and the second calculation layer And a calculation process for deleting the contact in a portion where the third calculation layer overlaps.

  FIG. 16 is a diagram showing design data of a single height cell in the present embodiment. The configuration of FIG. 16 is almost the same as that of FIG. However, dummy gates DG11 and DG13 are respectively disposed at both ends of the P well PW, and dummy gates DG12 and DG14 are respectively disposed at both ends of the N well NW.

  FIG. 17 is a diagram showing design data of a double height cell in the present embodiment. The configuration of FIG. 17 is almost the same as that of FIG. However, dummy gates DG291 and DG292 are disposed at both ends of the N well NW, dummy gates DG21 and DG25 are respectively disposed at both ends of the lower P well PW, and dummy gates are disposed at both ends of the upper P well PW. Gates DG24 and DG28 are respectively arranged. The dummy gates DG291 and DG292 extend over almost the entire range of the N well NW so as to straddle the center of the cell in the cell height direction. For this reason, the length of the dummy gates DG291 and DG292 in the cell height direction is longer than the gate width of the transistors MP21 and MP23.

  FIG. 18 shows layout design data created and modified in the layout design step S11 and the layer calculation processing step S12, and corresponds to a layout plan view of the semiconductor integrated circuit device according to this embodiment. 18 shows a configuration in which the single height cells CL2a, CL2b, and CL2c shown in FIG. 16 are arranged on both sides in the cell width direction of the double height cell CL1 shown in FIG. The cells CL1, CL2a, CL2b, and CL2c are arranged so that the lower ends of the cell frames are aligned at the same position in the cell height direction. Note that wiring between the standard cells performed in the layout design step S11 is omitted.

  In FIG. 18, as in FIG. 13, the layout calculation processing step S <b> 12 causes the distance from the right end of the cell in the P + diffusion wiring 102 a of the cell CL <b> 2 a to the distance ½ SP and the distance 1 The range up to / 2SP has been deleted. That is, there is a gap SP between the diffusion region of the transistor MP21 of the cell CL1 and the P + diffusion wiring 102a of the cell CL2a, and between the diffusion region of the transistor MP23 of the cell CL1 and the P + diffusion wiring 102b of the cell CL2b. Yes. Therefore, dummy gates DG291 and DG292 do not overlap with the diffusion wiring, and unnecessary transistors are not formed. As a result, variation in the shape of the gate electrode of the transistor of the cell CL1 can be suppressed.

  As described above, according to the present embodiment, dummy gates can be arranged on both sides of the transistor arranged in the center of the double height cell without forming unnecessary transistors. As a result, it is possible to suppress variation in the shape of the gate electrode of the transistor disposed at the center of the double height cell.

  In FIG. 18, a dummy gate is added to the configuration of FIG. 13 shown in the third embodiment. For example, the configuration shown in the first and second embodiments is different from the configuration shown in FIG. Of course, the same effect can be obtained even when a dummy gate is added. For example, in the layout of FIG. 3 or FIG. 6, a dummy gate is arranged to extend in the cell height direction while the diffusion region D_MP23 of the transistor MP23 of the cell CL1 and the P + diffusion wiring 102 of the cell CL2 face each other. May be. That is, in each of the above-described embodiments, no gate wiring is arranged between the rectangular transistor diffusion region of the multi-height cell and the diffusion wiring of the adjacent cell facing this, or one gate wiring is provided. Only arranged.

  In each of the above-described embodiments, the N-well is disposed in the center of the double-height cell, and the diffusion wiring of another cell is adjacently disposed in this N-well. However, the present invention is not limited to this. For example, even if the P well is arranged in the center of the double height cell and the diffusion wiring of another cell is arranged adjacent to the P well, the same as in the above embodiments It is applicable to.

  In each of the above-described embodiments, the configuration in which other cells are arranged adjacent to the double height cell has been described as an example. However, the configuration is not limited to the double height cell, and is N times the reference cell height (N is The above-described embodiments can be applied as long as other cells are arranged adjacent to a multi-height cell having a cell height of 2 or more. That is, the above-described embodiments are effective as long as the multi-height cell has a large well region and diffusion wirings of other cells are arranged adjacent to this well region.

  Further, in each of the above-described embodiments, the diffusion wirings arranged at the upper and lower ends of the cell have been described as an example connected to the source region of the transistor. However, for example, the diffusion wirings arranged at the upper and lower ends of the cell The same effect can be obtained even if the diffusion wiring is used to fix the substrate potential by reversing P / N. For example, FIG. 19 shows an example in which the diffusion wiring is changed to a configuration for fixing the substrate potential with respect to the single height cell of FIG. In FIG. 19, the N + diffusion wiring 102A is used for fixing the potential of the N well NW, and the P + diffusion wiring 107A is used for fixing the potential of the P well PW.

  According to the present invention, in the semiconductor integrated circuit device, it is possible to improve the driving capability of the transistor in the multi-height cell as compared with the conventional art. Therefore, for example, it is effective in reducing the area of LSI and improving the performance.

CL1 Double height cell (first cell)
CL2, CL2b Single height cell (second cell)
CL2A, CL2B Double height cell (second cell)
CL3 cell (third cell)
CL4 cell (4th cell)
101 Power supply wiring (first metal wiring)
102, 102b, 102A P + diffusion wiring (first diffusion wiring)
103 Contact 106 Ground wiring (second metal wiring)
107, 107A N + diffusion wiring (second diffusion wiring)
108 Contact 206 Ground wiring (third metal wiring)
207 N + diffusion wiring (third diffusion wiring)
208 Contact 301 Power supply wiring (first metal wiring)
302 P + diffusion wiring (first diffusion wiring)
303 Contact D_MP23 Source diffusion region of transistor MP23 (first transistor diffusion region)
D_MP11 Drain diffusion region (first diffusion region) of the transistor MP11
D_MN31 Source diffusion region of transistor MN11 (second transistor diffusion region)
DG291, DG292 Dummy gates BL1, BL2 Cell boundary

Claims (20)

A semiconductor integrated circuit device in which a plurality of cells are arranged,
The plurality of cells are:
A first cell that is a multi-height cell having a cell height N times the reference cell height (N is an integer of 2 or more);
A second cell disposed adjacent to the first cell in the cell width direction,
The second cell is
A first metal wiring disposed at one end in the cell height direction so as to extend in the cell width direction;
A first diffusion wiring comprising an impurity diffusion region formed so as to extend in a cell width direction under the first metal wiring, and connected to the first metal wiring through a contact;
The first cell is
A first transistor diffusion region that is opposed to the first diffusion wiring in the cell width direction and is formed so as to straddle an extension region in the cell width direction of the first metal wiring in the cell height direction. With
The semiconductor integrated circuit device according to claim 1, wherein the first diffusion wiring is disposed apart from a cell boundary between the first cell and the second cell in the cell width direction. In claim 1,
The second cell is a single height cell having the reference cell height, and includes a second metal wiring arranged to extend in the cell width direction at the other end in the cell height direction,
The first cell includes a third metal wiring arranged at one end in the cell height direction so as to extend in the cell width direction,
The second metal wiring of the second cell and the third metal wiring of the first cell are arranged so as to be in a straight line in the cell width direction and are connected to each other. Semiconductor integrated circuit device. In claim 2,
The second cell is
A second diffusion wiring formed of an impurity diffusion region formed so as to extend in a cell width direction under the second metal wiring, and further connected to the second metal wiring through a contact;
The semiconductor integrated circuit device, wherein the second diffusion wiring is disposed apart from a cell boundary between the first cell and the second cell in a cell width direction. In claim 3,
The first cell is
A third diffusion wiring formed of an impurity diffusion region formed so as to extend in a cell width direction under the third metal wiring, and further connected to the third metal wiring through a contact;
The semiconductor integrated circuit device, wherein the third diffusion wiring is disposed apart from a cell boundary between the first cell and the second cell in a cell width direction. In claim 4,
In the first cell, the arrangement position of the contact connecting the third metal wiring and the third diffusion wiring is shifted from the arrangement position of the contact formed in the diffusion region constituting the transistor in the cell width direction. A semiconductor integrated circuit device. In claim 4,
Of the contacts connecting the third metal wiring and the third diffusion wiring in the first cell, the distance between the contact closest to the cell boundary and the cell boundary is the second cell in the second cell. A semiconductor integrated circuit device characterized in that a distance between a contact closest to the cell boundary among contacts connecting a metal wiring and the second diffusion wiring and the cell boundary is equal.
In claim 2,
The plurality of cells are:
Including third and fourth cells arranged adjacent in the cell width direction;
The third and fourth cells are arranged adjacent to each other in the cell height direction so as to share the second and third metal wires with the first and second cells,
The position of the cell boundary in the cell width direction of the third and fourth cells is shifted from the position of the cell boundary in the cell width direction of the first and second cells,
The second diffusion wiring formed of an impurity diffusion region formed so as to extend in the cell width direction under the second and third metal wirings, and connected to the second and third metal wirings through contacts, A semiconductor integrated circuit device, wherein the first and second cells are continuously arranged across cell boundaries in the cell width direction. In claim 2,
The second cell is
A second diffusion wiring formed of an impurity diffusion region formed so as to extend in a cell width direction under the second metal wiring, and further connected to the second metal wiring through a contact;
Of the contacts connecting the first metal wiring and the first diffusion wiring in the second cell, the distance between the contact closest to the cell boundary and the cell boundary is the second cell in the second cell. 2. A semiconductor integrated circuit device, comprising: a contact between a metal wiring and a second diffusion wiring, the contact closest to the cell boundary, and a distance between the cell boundary. In claim 1,
The second cell is
The arrangement position of the contact connecting the first metal wiring and the first diffusion wiring is shifted from the arrangement position of the contact formed in each diffusion region constituting the transistor in the cell width direction. Semiconductor integrated circuit device. In claim 1,
The second cell is
A multi-height cell having a cell height that is M times the reference cell height (M is an integer of 2 or more);
The first cell is
A third metal wiring arranged to extend in the cell width direction at one end in the cell height direction;
A third diffusion wiring formed of an impurity diffusion region formed so as to extend in a cell width direction under the third metal wiring, and further connected to the third metal wiring via a contact;
The second cell is
A second transistor diffusion region that is opposed to the third diffusion wiring in the cell width direction and extends across the extension region in the cell width direction of the third metal wiring in the cell height direction, and constitutes a transistor With
3. The semiconductor integrated circuit device according to claim 1, wherein the third diffusion wiring is disposed apart from a cell boundary between the first cell and the second cell in the cell width direction. In any one of Claims 1-10,
A semiconductor integrated circuit device, wherein a dummy gate is formed so as to extend in a cell height direction while the first transistor diffusion region and the first diffusion wiring face each other. A semiconductor integrated circuit device in which a plurality of cells are arranged,
The plurality of cells are:
A first cell that is a multi-height cell having a cell height N times the reference cell height (N is an integer of 2 or more);
A second cell disposed adjacent to the first cell in the cell width direction,
The second cell is
A first metal wiring disposed at one end in the cell height direction so as to extend in the cell width direction;
A first diffusion wiring composed of an impurity diffusion region formed so as to extend in a cell width direction under the first metal wiring, and connected to the first metal wiring through a contact;
A first diffusion region constituting a transistor,
The first cell is
A transistor is formed so as to face the first diffusion wiring and the first diffusion region in the cell width direction, and to extend the extension region in the cell width direction of the first metal wiring in the cell height direction. A first transistor diffusion region that includes:
2. The semiconductor integrated circuit device according to claim 1, wherein an interval between the first diffusion wiring and the first transistor diffusion region is equal to or greater than a minimum interval between the first diffusion region and the first transistor diffusion region. In claim 12,
The second cell is a single height cell having the reference cell height, and includes a second metal wiring arranged to extend in the cell width direction at the other end in the cell height direction,
The first cell includes a third metal wiring arranged at one end in the cell height direction so as to extend in the cell width direction,
The second metal wiring of the second cell and the third metal wiring of the first cell are arranged so as to be in a straight line in the cell width direction and are connected to each other. Semiconductor integrated circuit device. In claim 13,
The second cell is
A second diffusion wiring formed of an impurity diffusion region formed so as to extend in a cell width direction under the second metal wiring, and further connected to the second metal wiring through a contact;
A cell between the first transistor diffusion region and a contact closest to the first transistor diffusion region in the cell width direction among contacts connecting the first metal wiring and the first diffusion wiring in the second cell. The interval in the width direction is such that a contact closest to the first transistor diffusion region in the cell width direction among contacts connecting the second metal wiring and the second diffusion wiring in the second cell, and the first transistor diffusion. A semiconductor integrated circuit device characterized in that it is larger than an interval between the region in the cell width direction. In claim 12,
The second cell is
The arrangement position of the contact connecting the first metal wiring and the first diffusion wiring is shifted from the arrangement position of the contact formed in each diffusion region constituting the transistor in the cell width direction. Semiconductor integrated circuit device. In any one of Claims 12-15,
A semiconductor integrated circuit device, wherein a dummy gate is formed so as to extend in a cell height direction while the first transistor diffusion region and the first diffusion wiring face each other. A semiconductor integrated circuit device in which a plurality of cells are arranged,
The plurality of cells are:
A first cell that is a multi-height cell having a cell height N times the reference cell height (N is an integer of 2 or more);
A second cell disposed adjacent to the first cell in the cell width direction,
The second cell is
A first metal wiring disposed at one end in the cell height direction so as to extend in the cell width direction;
A first diffusion wiring comprising an impurity diffusion region formed so as to extend in a cell width direction under the first metal wiring, and connected to the first metal wiring via a contact;
The first cell is
A rectangular first transistor that is opposed to the first diffusion wiring in the cell width direction and is formed so as to straddle the extension region in the cell width direction of the first metal wiring in the cell height direction. With diffusion areas,
A semiconductor integrated circuit device characterized in that no gate wiring is arranged or only one gate wiring is arranged between the first diffusion wiring and the first transistor diffusion region. In claim 17,
The second cell is a single height cell having the reference cell height, and includes a second metal wiring arranged to extend in the cell width direction at the other end in the cell height direction,
The first cell includes a third metal wiring arranged at one end in the cell height direction so as to extend in the cell width direction,
The second metal wiring of the second cell and the third metal wiring of the first cell are arranged so as to be in a straight line in the cell width direction and are connected to each other. Semiconductor integrated circuit device. In claim 18,
The second cell is
A second diffusion wiring formed of an impurity diffusion region formed so as to extend in a cell width direction under the second metal wiring, and further connected to the second metal wiring through a contact;
A cell between the first transistor diffusion region and a contact closest to the first transistor diffusion region in the cell width direction among contacts connecting the first metal wiring and the first diffusion wiring in the second cell. The interval in the width direction is such that a contact closest to the first transistor diffusion region in the cell width direction among contacts connecting the second metal wiring and the second diffusion wiring in the second cell, and the first transistor diffusion A semiconductor integrated circuit device characterized in that it is larger than an interval between the region in the cell width direction. In claim 17,
The second cell is
The arrangement position of the contact connecting the first metal wiring and the first diffusion wiring is shifted from the arrangement position of the contact formed in each diffusion region constituting the transistor in the cell width direction. Semiconductor integrated circuit device.

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