JPWO2012035699A1 - Information processing apparatus, information processing method, design support system, and program - Google Patents

Abstract

The information processing apparatus 7 according to the present invention outputs an arithmetic processing device 71 that executes a program including predetermined processing, and an execution request signal that requests execution of the program to the arithmetic processing device 71 and performs predetermined processing. And a reconfiguration device 72 having processing information used in FIG. The arithmetic processing unit 71 activates a program according to the execution request signal output from the reconfiguration device 72, reads out processing information from the reconfiguration device 72, and executes predetermined processing.

Description

  The present invention relates to an information processing apparatus, an information processing method, a design support system, and a non-transitory computer-readable medium storing a program.

  An information processing apparatus is required to have a higher level of arithmetic processing capability or an ability to process a large amount of multimedia data such as an image or a moving image at a high speed as the range of use thereof is expanded. As a technique for satisfying such a requirement, it is known to provide a processor or a circuit that executes a specific operation or process exclusively for a host processor. Examples of such processors and circuits include a DSP (Digital Signal Processor) and an ASIC (Application Specific Integrated Circuit). According to this method, the processing load of the host processor can be reduced, so that the processing capability of the entire information processing apparatus can be improved.

In recent years, compression / decompression processing and arithmetic processing of various standards are required for multimedia data. In communication processing for transmitting / receiving various data via a network, processing based on various protocols is required. Furthermore, in order to ensure security, data encryption / decryption processing may be required.
However, if a large number of dedicated processors and circuits are provided in the information processing apparatus in accordance with these various processes, the circuit scale and cost of the information processing apparatus become enormous.

  Therefore, an FPGA (Field Programmable Gate Array), CPLD (Complex Programmable Logic Device), or DRP (Dynamically Reconfigurable Processor) as described in Patent Documents 1 to 6 and Non-Patent Document 1 is used as the information processing apparatus. It is known to provide various types of processing. These programmable devices are called reconfigurable devices. Since the reconfigurable device changes the circuit configuration and executes various processes, the information processing apparatus can respond to various processing requests at low cost by mounting the reconfigurable device.

A reconfigurable device generally includes an internal memory for temporarily storing configuration codes, that is, circuit information, input data and initial values necessary for processing, and processing results. The internal memory is composed of a plurality of storage elements.
An information processing apparatus including a reconfigurable device is provided with a writing device for writing circuit information to a storage element in the reconfigurable device.

The writing device writes circuit information to each storage element of the reconfigurable device according to control of an MPU (Micro Processing Unit), a CPU (Central Processing Unit), or the like in the information processing device. The reconstruction device configures a circuit inside based on circuit information written in the storage element.
A writing device for an FPGA includes a compact flash (registered trademark). The compact flash is also called configuration hardware or a configuration device. Further, the information processing apparatus can rewrite a part of the FPGA using a write interface compliant with JTAG (Joint Test Action Group).

In order to rewrite the data held in the storage element in the reconstruction device using the writing device, it is necessary to input the position of the storage element to be rewritten to the writing device in addition to the data to be rewritten. . The reconfigurable device is, for example, an FPGA or DRP.
For example, in DRP, an address is assigned to each storage element in the DRP. That is, when viewed from the writing device, the DRP looks like a huge memory composed of storage elements. Therefore, the writing device can write the data to the storage element corresponding to the address in response to the input of the address and data.

In addition to this writing device, an arithmetic processing unit is connected to the bus line. The arithmetic processing unit is, for example, an MPU or a CPU. A shared memory is also connected to this bus line. The arithmetic processing unit and the reconfiguration device exchange data to be processed by the reconfiguration device and the MPU via this shared memory so that they can operate simultaneously. Alternatively, a part of the shared memory is used as a work memory for data processing by the arithmetic processing unit or the reconstruction device.
Further, an interrupt controller is connected to the bus line. The reconfigurable device notifies the arithmetic processing unit of an interrupt via the interrupt controller so that the arithmetic processing unit and the reconfigurable device can operate in a coordinated manner.

  On the other hand, an operating system is usually mounted on the arithmetic processing unit. Application software runs in the operating system. This application software can use a system call provided from the operating system. For example, dynamically secure work memory for data processing from shared memory, input data from keyboard and mouse via input interface, and output text and images to display via output interface be able to.

  The reconfiguration device can flexibly design the processing content by programming. Therefore, various processes such as a specific process and a general-purpose process are mounted on the reconfigurable device. However, the reconfigurable device has limited computing resources and can implement only the amount of processing corresponding to it. For example, as described above, the arithmetic processing apparatus has enough arithmetic resources to mount the operating system, but the reconfigurable device does not have the arithmetic resources up to that point. Here, as a method for compensating for the shortage of computing resources in the reconfigurable device and enabling the reconfigurable device to execute a desired process, a part of the processing in the reconfigurable device is replaced with an arithmetic processing device having a surplus of computing resources. It is possible to execute this method.

  Patent Documents 1 to 6 and Non-Patent Document 1 disclose techniques related to a reconstruction device. However, none of Patent Documents 1 to 6 and Non-Patent Document 1 disclose a technique that makes it possible to execute the processing of the reconfiguration device in place of the arithmetic processing device.

JP 2000-138579 A JP 2000-2224025 A JP 2000-232354 A JP 2000-232162 A Japanese Patent Laid-Open No. 2003-076668 JP-A-2005-242812

Hideharu Amano, Akiya Jouraku, Kenichiro Anjo, "A Dynamicall y Adaptive Hardware on Dynamically Reconfigurable Processor", IEICE Transact ions, Vol. E86-B, No.12, pp. 3385-3391, 2003.

  As described in the background art, there is a problem that the processing of the reconfigurable device cannot be executed in place of the arithmetic processing device.

  An object of the present invention is to store an information processing apparatus, an information processing method, a design support system, and a program that can execute processing of a reconfigurable device instead of an arithmetic processing unit in order to solve the above-described problem. Non-transitory computer readable media.

  The information processing apparatus according to the first aspect of the present invention outputs an execution processing signal for requesting execution of the program to the arithmetic processing apparatus that executes a program including predetermined processing, and the arithmetic processing apparatus. A reconfiguration device having processing information used in the predetermined processing, and the arithmetic processing unit starts the program in response to an execution request signal output from the reconfiguration device, and reconfigures the reconfiguration device. The processing information is read from the device and the predetermined processing is executed.

  In the information processing method according to the second aspect of the present invention, the reconfiguration device outputs an execution request signal for requesting execution of a program including predetermined processing, and the arithmetic processing unit is output from the reconfiguration device. In response to the execution request signal, the program is started, processing information used in the predetermined processing is read from the reconfigurable device, and processing of the processing is executed.

  The design support system according to the third aspect of the present invention is used to generate circuit information of a reconfigurable device based on a first source program including a predetermined process, and the reconfigurable device receives the predetermined process. Library generating means for generating a library including processing for outputting an execution request signal for requesting execution, and the reconfiguration used for generating an execution program executed by an arithmetic processing unit based on the first source program A second source including processing for causing the arithmetic processing unit to read processing information used in the predetermined processing from the reconfigurable device in accordance with an execution request signal output from the device, and to execute the predetermined processing Source program generating means for generating a program.

  When the non-transitory computer-readable medium storing the program according to the fourth aspect of the present invention is executed in response to an execution request signal output from the reconfiguration device, a predetermined process is performed from the reconfiguration device. A non-transitory computer-readable medium storing a program for causing an arithmetic processing unit to execute processing for reading processing information used in the processing, processing for executing the predetermined processing using the read processing information is there.

  According to each aspect of the present invention described above, an information processing apparatus, an information processing method, a design support system, and a program in which a program of a reconstruction device can be executed instead of an arithmetic processing apparatus is stored. A computer readable medium may be provided.

It is a block diagram of the information processor concerning an embodiment of the invention. 1 is a block diagram of a design support system according to an embodiment of the present invention. It is a block diagram which shows one structural example of the target system concerning embodiment of this invention. It is a block diagram which shows the example of 1 structure of the program design support system concerning embodiment of this invention. It is a block diagram which shows one structural example of the program generation apparatus concerning embodiment of this invention. It is a figure which shows the example of 1 description of the user-defined function program concerning embodiment of this invention. It is a figure showing an example of 1 composition of a function list concerning an embodiment of the invention. It is a figure which shows the example of 1 description of the client library concerning embodiment of this invention. It is a figure which shows one example of a description of the server program concerning embodiment of this invention. It is a schematic diagram which shows one structural example of the stack data concerning embodiment of this invention. It is a schematic diagram which shows one structural example of the target system concerning embodiment of this invention. It is a schematic diagram which shows one structural example of the stack data concerning embodiment of this invention. It is a schematic diagram which shows one usage example of stack data concerning embodiment of this invention. It is a schematic diagram which shows one usage example of stack data concerning embodiment of this invention. It is a flowchart which shows the operation | movement sequence of the program design support system concerning embodiment of this invention. It is a figure which shows one example of a description of the behavior level description concerning embodiment of this invention. It is a flowchart which shows the operation | movement sequence of the target system concerning embodiment of this invention. It is a schematic diagram which shows the state of the stack data at the time of target system operation | movement concerning embodiment of this invention. It is a schematic diagram which shows the state of the stack data at the time of target system operation | movement concerning embodiment of this invention. It is a schematic diagram which shows the state of the stack data at the time of target system operation | movement concerning embodiment of this invention. It is a schematic diagram which shows the state of the stack data at the time of target system operation | movement concerning embodiment of this invention. It is a schematic diagram which shows the example of a console output at the time of target system operation | movement concerning embodiment of this invention.

First, with reference to FIG. 1, an information processing apparatus as an outline of a target system according to an embodiment of the present invention will be described. FIG. 1 is a block diagram of an information processing apparatus according to an embodiment of the present invention.
The information processing apparatus 7 includes an arithmetic processing device 71 and a reconstruction device 72.
The arithmetic processing unit 71 executes an operating system. The arithmetic processing unit 71 executes a program that operates on the operating system. The program includes a predetermined process.
The reconfiguration device 72 outputs an execution request signal for requesting execution of the program to the arithmetic processing unit 71. The reconstruction device 72 has processing information used in a predetermined process.

Next, the operation of the information processing apparatus 7 according to the embodiment of the present invention will be described.
The arithmetic processing unit 71 starts execution of the operating system.
The reconstruction device 72 outputs an execution request signal to the arithmetic processing unit.
The arithmetic processing unit 71 executes the program in accordance with the execution request signal output from the reconfiguration device 72. At this time, the arithmetic processing unit 71 reads out processing information from the reconstruction device 72 and executes a predetermined process.

  Next, a design support system that is an outline of the program design support system according to the embodiment of the present invention will be described. FIG. 2 is a block diagram of the design support system according to the embodiment of the present invention.

  The design support system 2 includes a source program generation unit 21 and a library generation unit 22.

Based on the first source program 25, the source program generation unit 21 reads out processing information used in a predetermined process from the reconfiguration device to the arithmetic processing device in accordance with the execution request signal output from the reconfiguration device. The second source program 26 including a process for executing a predetermined process is generated. The second source program 26 is used to generate an execution program that is executed on the operating system by an arithmetic processing unit that executes the operating system.
Based on the first source program 25 including predetermined processing, the library generation unit 22 generates a library 27 including processing for causing the reconfigurable device to output an execution request signal for requesting execution of the predetermined processing. This library 27 is used for behavioral synthesis of circuit information of the reconfigurable device.

Next, the operation of the design support system 2 according to the embodiment of the present invention will be described.
The source program generation unit 21 generates a second source program 26 based on the first source program 25.
The library generation unit 22 generates a library 27 based on the first source program 26.

Embodiments for carrying out the present invention will be described in detail with reference to the drawings.
The respective configurations of the information processing apparatus of the present embodiment and the program design support system for designing the execution program and circuit information will be described in order for the information processing apparatus. Since the information processing apparatus is a design target for the program design support system, the information processing apparatus is hereinafter referred to as a target system.

  FIG. 3 is a block diagram illustrating a configuration example of the target system 6 according to the present embodiment. Referring to FIG. 3, the target system 6 includes an MPU 601, an interrupt controller 602, a reconfiguration device 603, a reading device 604, a bus access device 605, a writing device 606, a shared memory 607, an input / output interface 608, a network interface 609, An input device 610, an output device 611, a network 612, and a bus line 613 are included.

  The MPU 601 is an arithmetic processing device that transmits and receives data to and from the reconfiguration device 603 by controlling the interrupt controller 602, the reading device 604, and the writing device 606. Furthermore, the MPU 601 executes an operating system. The MPU 601 controls the shared memory 607, the input / output interface 608, and the network interface 609 according to the execution of the operating system. The MPU 601 executes, for example, various operations, input from the input device 610, output to the output device 611, input / output with the network 612, and the like.

  The MPU 601 executes an execution program that operates on the operating system. The execution program may include processing for executing a system call provided by the operating system. In this case, a function provided by the operating system such as a system call is used by executing the execution program. The MPU 601 executes the execution program in response to the interrupt signal from the interrupt controller 602.

An MPU 601, an interrupt controller 602, a reading device 604, a bus access device 605, a writing device 606, a shared memory 607, an input / output interface 608, and a network interface 609 are connected to the bus line 613.
The shared memory 607 temporarily holds data to be processed by the MPU 601 and the reconfiguration device 603 and results processed by the MPU 601 and the reconfiguration device 603.
The interrupt controller 602 receives the interrupt signal from the reconfiguration device 603 and causes the MPU 601 to generate an interrupt. Specifically, the interrupt controller 602 outputs an interrupt signal to the MPU 601 in response to an interrupt signal from the reconfiguration device 603.

The reconfiguration device 603 is a reconfiguration device such as FPGA or DRP. A plurality of storage elements 6030 are provided in the reconstruction device 603.
The storage element 6030 temporarily holds data to be processed by the reconfiguration device 603 and processing results. The storage element 6030 also holds stack data for operating a user-defined function set in advance by the MPU 601.

  The reconstruction device 603 constitutes a circuit indicated by the circuit information written in the storage element 6030. Further, the reconfiguration device 603 accesses the shared memory 607 by controlling the bus access device 605. This is because the shared memory 607 holds data to be processed having a size that cannot be held by the storage element 6030, data being processed, and data of the processing result. Further, the reconstruction device 603 generates an interrupt signal in accordance with the circuit information written in the storage element 6030.

  Specifically, when causing the MPU 601 to execute an execution program operating on the operating system, an interrupt signal is output to the interrupt controller 602. Thereby, as described above, the MPU 601 executes the execution program. In other words, this interrupt signal is a signal that requests the arithmetic processing unit 601 to execute the execution program.

  The reading device 604 reads stack data exchanged between the reconfiguration device 603 and the MPU 601 from the storage element 6030 of the reconfiguration device 603 according to the control of the MPU 601. Specifically, the reading device 604 acquires the stack data requested by the MPU 601 from the storage element 6030 and outputs the acquired stack data to the MPU 601.

  The bus access device 605 accesses the shared memory 607 via the bus line 613 under the control of the reconfiguration device 603. Specifically, the bus access device 605 stores the data output from the reconfiguration device 603 in the shared memory 607. In addition, the bus access device 605 acquires the data requested by the reconfiguration device 603 from the shared memory 607 and outputs the acquired data to the reconfiguration device 603.

  The writing device 606 writes circuit information to the storage element 6030 of the reconfiguration device 603 in accordance with the control of the MPU 601. In addition to the circuit information, the writing device 606 writes stack data exchanged between the reconfiguration device 603 and the MPU 601 in the storage element 6030 of the reconfiguration device 603. Specifically, the writing device 606 writes the data output from the MPU 601 into the storage element 6030.

The input / output interface 608 controls data input / output between the MPU 601, the input device 610, and the output device 611.
The network interface 609 controls data transmission / reception between the MPU 601 and the network 612.
The input device 610 is, for example, a keyboard or a mouse.
The output device 611 is, for example, a display.

  With the configuration described above, the reconfiguration device 603 outputs a signal for requesting execution of the execution program to the arithmetic processing device 601, thereby causing the arithmetic processing device 601 to execute the execution program that operates on the operating system. To be able to. That is, the reconfiguration device 603 can use a function provided by the operating system through execution of the execution program.

  Next, the configuration of a program design support system that supports the design of an execution program for starting a user-defined function defined in advance in the MPU 601 shown in FIG. 3 from the reconfiguration device 603 will be described.

FIG. 4 is a block diagram illustrating a configuration example of the program design support system 1. Referring to FIG. 4, the program design support system 1 includes a program generation device 10, a compilation device 14, and a behavioral synthesis device 18.
The program generation apparatus 10 includes a function extraction apparatus 101, a server program generation apparatus 104, and a client library generation apparatus 105.

  The target system information 12 includes the internal configuration of the MPU 601, address map information, the number and type of arithmetic units in the reconfiguration device 603, the structure of the interconnection unit, the number and type of storage elements 6030, and the bus address This is information indicating the map and the configuration of the stack data area. The address map information indicates an address map of the interrupt controller 602, shared memory 607, input / output interface 608, network interface 609, and the like connected to the bus line 613. The bus address map is for accessing the storage element 6030 from the bus line 613 via the writing device 606 or the reading device 604. The stack data area stores stack data exchanged between the MPU 601 and the reconfiguration device 603 of the target system 6. The configuration of the stack data area refers to the position of the storage element 6030 of the reconstruction device 603 in which the stack data is stored, and the bus address for accessing the storage element 6030 via the writing device 606 and the reading device 604. It is.

  A user-defined function program 11 is input to the function extraction device 101. The user-defined function program 11 describes functions executed by the MPU 601 in FIG. Further, the user-defined function program 11 describes a process that the reconfiguration device 603 causes the arithmetic processing unit 601 to execute. The user-defined function program 11 is a source program described in a programming language such as C language, C ++ language, or Java language. A specific example of the contents of the user-defined function program 11 will be described later with reference to FIG.

The function extraction device 101 extracts a function from the user-defined function program 11 according to the programming language specification and outputs a function list 103. The function extraction device 101 transmits the generated function list 103 to the server program generation device 104 and the client library generation device 105, respectively.
The function list 103 is a list in which unique numbers are assigned to the functions extracted by the function extraction apparatus 101. Here, the unique number is, for example, a number generated by the function extraction apparatus 101 so as to be unique for each extracted function. A specific example of the description contents of the function list 103 will be described later with reference to FIG.

  The server program generation device 104 receives a user-defined function program 11, a function list 103, and target system information 12. The server program generation device 104 generates a server program 13 from the user-defined function program 11 and the function list 103 based on the target system information 12 and transmits the server program 13 to the compilation device 14.

  Here, the server program 13 includes an interrupt handler for calling individual user-defined functions of the user-defined function program 11. The interrupt handler calls individual user-defined functions after converting the stack data set in the client library 16 into user-defined function arguments. A specific example of the server program 13 will be described later with reference to FIG. The server program 13 is a source program as illustrated in FIG.

The user-defined function program 11, the function list 103, and the target system information 12 are input to the client library generation device 105.
Based on the target system information 12, the client library generation device 105 generates a client library 16 from the user-defined function program 11 and the function list 103 and transmits it to the behavioral synthesis device 18.

  Here, the client library 16 includes a client function. The client function converts arguments of individual functions of the user-defined function program 11 into stack data, requests the MPU 601 to execute the execution program, and waits for notification of the execution result from the MPU 601. A specific example of the client library 16 will be described later with reference to FIG.

The compiling device 14 converts the server program 13 into a format (execution binary 15) that can be executed by the MPU 601 of the target system 6. The execution binary 15 becomes an execution program executed on the operating system in the MPU 601.
The behavioral synthesis device 18 performs behavioral synthesis, logic synthesis, and placement and routing from the target system information 12, the client library 16, and the behavior level description 17, and a circuit showing the configuration, placement, and wiring of the reconfiguration device 603. Information 19 is generated. A specific example of the behavior level description 17 will be described later with reference to FIG. The behavior level description 17 includes a description for calling the client library 16.
Further, the behavioral synthesis device 18 determines the arrangement location of the stack data area specified by the client library 16 from the configuration of the stack data area included in the target system information 12 and generates circuit information 19.

As described above, the user-defined function program 11, the target system information 12, and the behavior level description 17 are input to the program design support system 1. Inside the program design support system 1, the user-defined function program 11, the function list 103, the server program 13, and the client library 16 are transmitted and received. Then, the program design support system 1 outputs an execution binary 15 and circuit information 19.
These input / output or transmitted / received information is stored in a predetermined storage device (not shown). This storage device may be provided in each device inside the program design support system 1 or may be provided independently outside. This storage device is, for example, a data storage device 203 described later.

Next, a configuration example of the program generation device 10 illustrated in FIG. 4 will be described.
FIG. 5 is a block diagram illustrating a configuration example of the program generation device 10. Referring to FIG. 5, the program generation device 10 includes a CPU 200, a main storage device 201, a recording medium 202, a data storage device 203, a main storage control interface unit 204, a storage medium control interface unit 205, and a data storage. A control interface unit 206, a bus 2000, an input control interface unit 207, an output control interface unit 208, and a network control interface unit 209 are included.

  The program generation device 10 executes a function extraction process, a server program generation process, and a client library generation process according to a program executed by the CPU 200.

The input device 30 inputs a command, the user-defined function program 11, and the target system information 12 to the program generation device 10. For example, when the user periodic function program 11 and the target system information 12 are input by the input device 30, the CPU 200 stores the input user periodic function program 11 and the target system information 12 in the data storage device 203.
The output device 40 outputs processing results such as the server program 13, the client library 16, and the circuit information 19.

  The network device 50 is, for example, a hub or a router. The program generation device 10 is connected to the network via the network device 50. The user-defined function program 11 and the target system information 12 are stored in an information processing apparatus (not shown) on the network, and the CPU 200 acquires the user-defined function program 11 and the target system information 12 from this information processing apparatus, The acquired user-defined function program 11 and target system information 12 may be stored in the data storage device 203.

CPU 200 executes a program recorded on recording medium 202.
The main storage device 201 temporarily holds information necessary for the processing of the CPU 200.
The recording medium 202 is a recording medium such as a magnetic disk, a semiconductor memory, or an optical disk. The recording medium 202 stores a program for causing the CPU 200 to execute processing as the program generation device 10.

  The data storage device 203 stores a user-defined function program 11, target system information 12, a function list 103, a server program 13, a client library 16, and the like. The data storage device 203 may store the execution binary 15 and the circuit information 19. The data storage device 203 is a recording medium such as a magnetic disk, a semiconductor memory, and an optical disk. A part or all of the data storage device 203 may be provided independently outside the program generation device 10 instead of inside the program generation device 10. For example, a part or all of the data storage device 203 may be provided in a storage external to the program generation device 10 or an information processing device. The information processing apparatus is, for example, a PC (Personal computer) or a server.

The main memory control interface unit 204 is connected to the main memory device 201.
The storage medium control interface unit 205 is connected to the recording medium 202.
The data storage control interface unit 206 is connected to the data storage device 203.
The input control interface unit 207 is connected to the input device 30.
The output control interface unit 208 is connected to the output device 40.
The network control interface unit 209 is connected to the network device 50.
Each interface unit 204 to 209 controls data transfer between these devices 200 to 203 and 30 to 50 and the bus 2000.

  The bus 2000 includes a CPU 200, a main storage control interface unit 204, a storage medium control interface unit 205, a data storage control interface unit 206, an input control interface unit 207, an output control interface unit 208, and a network control interface unit. 209 are connected to each other.

Note that each of the function extraction device 101, the server program generation device 104, and the client library generation device 105 shown in FIG. 4 may have the hardware configuration shown in FIG. In this case, the data to be processed and the program to be executed differ from device to device corresponding to the function of each device.
Further, the compiling device 14 and the behavioral synthesis device 18 shown in FIG. 4 are the same as those shown in the block diagram of FIG. 14 and the detailed description of the configuration of the behavioral synthesis device 18 are omitted.

FIG. 6 is an example of a description of a user-defined function program input to the program generation device 10.
This figure illustrates the case where two functions P100 and P101 are described in the C language in the user-defined function program 11. For example, the func2 function P101 executes an operating system call inside the printf () function.
The function extraction device 101 identifies these functions, extracts a function program, and generates a function list 103.

  FIG. 7 is a diagram illustrating an example of a function list extracted by the function extraction device. As shown in the figure, the function list is a list to which a unique number (function ID) is added for each extracted function. In other words, the function list is information in which a function is associated with information for specifying the function.

  FIG. 8 is a diagram illustrating an example of the client library 16 output from the client library generation device. Processing included in the client library 16 is processing executed by the reconfiguration device 603. As shown in the figure, the client library 16 includes two client functions P205 and P209 having the same names and arguments as the functions described in the user-defined function program 11. Further, as shown in FIG. 8, the stack data held in the reconstruction device 603 is described as an array P200. Based on the target system information 12, the behavioral synthesis device 18 appropriately determines the arrangement location in the reconstruction device 603 based on the stack data arrangement.

  Here, the stack data is data stored in a data area formed by the storage element 6030 in the reconfiguration device 603 of the target system 6. It can be freely accessed from the circuit formed in the reconstruction device 603. This data area can also be freely accessed from the MPU 601 via the writing device 606, the reading device 604, and the bus line 613 of the target system 6. That is, the address of __stack [100] is set by the client library 16 to the address of the stack data area in the storage element 6030.

  Hereinafter, processing of the client functions P201, P205, and P209 included in the client library 16 will be described. Actually, the processing described below is executed by the reconstruction device 603.

  Each of the client functions P205 and P209 sets the function ID in the function ID area_stack [0] of the stack data (P206 or P210). Each of the client functions P205 and P209 sets an argument in each of the argument areas __stack [2] [3] and __stack [2] of the stack data (P207 or P211). Each of the client functions P205 and P209 calls the client function P201.

  The client function P201 initializes the control information area __stack [1] of the stack data (P202). The client function P201 generates an interrupt for the MPU 601 (P203). That is, the IntMPU () function P203 includes processing for causing the reconfiguration device 603 to output an interrupt signal for the interrupt controller 602. The client function P201 waits for an execution program execution end notification from the MPU 601 (P204). Specifically, the MPU 601 waits for a value other than 0 to be written in the control information area __stack [1]. When the MPU 601 writes a value other than 0 in the control information area __stack [1], the MPU 601 has notified the execution of the execution program. In this case, the processing returns from the client function P201 to the calling client function P205 or P209. The client function P205 acquires a value from the return value area and argument area of the stack data, sets it as the return value or argument of the client function (P208), and ends the process.

  Further, in the wait for notification of the client function from the MPU 601 (P204), an example is shown in which the MPU 601 waits for the value of __stack [1] to be updated with a value other than 0. That is, the reconfiguration device 603 may wait until the value is updated to a value other than the value exemplified here.

FIG. 9 is a diagram illustrating an example of a server program output from the server program generation device 104. As shown in the figure, the server program 13 includes one interrupt handler P301 for calling a function described in the user-defined function program 11.
Hereinafter, the process of the function P301 included in the server program 13 will be described. Actually, the processing described below is executed by the MPU 601.

  The interrupt handler P301 of the server program clears the interrupt signal to the MPU 601 (P302). The ClearInt () function includes a process of writing a value of 0 in the control information area. The interrupt handler P301 refers to the function ID area of the stack data of the reconfigurable device 603 and acquires the function ID (P303). The interrupt handler P301 switches processing based on the acquired function ID (P304).

  For example, when the function ID is 1 (P305), the interrupt handler P301 executes the func1 function of the user-defined function program 11. In that case, the interrupt handler P301 takes out the arguments x and y from the argument area of the stack data (P306). The interrupt handler P301 executes the func1 function using the acquired arguments x and y as the arguments x and y (P307). The interrupt handler P301 sets the return value ret and the return argument & z of the func1 function in the return value area and argument area of the stack data (P308).

On the other hand, when the function ID is 2 (P309), the interrupt handler P301 executes func2 of the user-defined function program 11. In that case, the interrupt handler P301 takes out the argument x from the argument area of the stack data (P310). The interrupt handler P301 executes the func2 function using the acquired argument x as the argument x (P311).
After executing the func1 function or func2 function of the user-defined function program 11, 1 is written in the control information area of the stack data, and the end of processing on the MPU 601 side is notified to the reconfigurable device (P312).

  Note that when the stack data is accessed from the MPU 601, the bus address of the storage element 6030 forming the stack data is necessary. The bus address is an address for accessing the storage element 6030 from the MPU 601 or the like via the writing device 606 or the reading device 604. These pieces of information are stored in the target system information 12. Therefore, the functions ReadReconfigArea () and WriteReconfigArea () for accessing the stack data are generated by the server program generation device 104 so as to access the bus address of the storage element 6030 based on the target system information 12, for example.

FIG. 10 is a configuration example of stack data in the client library and server program shown in FIGS.
FIG. 10 shows a configuration example in which the stack data has a width of 8 bits (1 byte) and a depth of 100. Information regarding the stack data is included in the target system information 12.

As shown in FIG. 10, the top data (+0) of the stack data represents a function ID. This function ID corresponds to the function ID described in the function list 103. The data at offset + 1 of the stack data represents control information. When the control information is 0, the MPU 601 indicates that the user-defined function has not been executed. When the control information is 1, the MPU 601 indicates that the user-defined function has been executed. The data after the offset +2 of the stack data represents the value of the argument and the return value.
The stack data area in which the stack data illustrated in FIG. 10 is stored is formed in the storage element 6030 of the reconfiguration device 603. For example, when a memory having a width of 8 bits and a depth of 100 exists as the storage element 6030 of the reconstruction device 603, a stack data area can be formed thereon.

  In addition, as illustrated in FIG. 11A, stack data may be formed using a plurality of storage elements 6031 and 6032 in the reconstruction device 603. At this time, as shown in FIG. 11B, if the bus addresses of the storage elements 6031 and 6032 are not continuous, the server program 13 for appropriately accessing the storage elements 6031 and 6032 from the MPU 601 may be generated. The bus address is an address for accessing the storage elements 6031 and 6032 from the MPU 601 or the like via the writing device or the reading device.

FIG. 12 is a diagram illustrating an example of using stack data of each function. 12A shows the case of the user-defined function func1, and FIG. 12B shows the case of the user-defined function func2.
As shown in FIG. 12, the data after the stack data offset +2 can be freely set between the client library 16 and the server program 13 as a pair in the range in which the argument and return value of each user-defined function are handled. Can be used.

For example, the argument and return value may be compressed on the client library 16 side and set as stack data, and the argument and return value may be expanded from the stack data on the server program 13 side. In this case, the number of storage elements of the reconfigurable device 603 required for configuring the stack data can be reduced.
Such a compression / decompression unit may be generated as the client library 16 and the server program 13, or a dedicated hardware or a software subroutine that provides a function equivalent to the dedicated hardware is called from the client library 16 or the server program 13. You may do it.

  Next, the operation of the program design support system 1 will be described with reference to FIG. FIG. 13 is a sequence diagram showing the operation of the program design support system 1.

  The function extraction device 101 acquires the user-defined function program 11 from the data storage device 203. The function extraction device 101 extracts a function from the user-defined function program 11, and generates a function list 103 associated with each individual ID (step S11). The function extraction device 101 stores the generated function list 103 in the data storage device 203. The function extraction apparatus 101 may output the generated function list 103 directly to the server program generation apparatus 104 and the client library generation apparatus 105.

  The server program generation device 104 acquires the user-defined function program, the function list 103, and the target system information 12 from the data storage device 203. The server program generation device 104 generates the server program 13 based on the target system information 12 from the user-defined function program 11 and the function list 103 (step S12). The server program generation device 104 stores the generated server program 13 in the data storage device 203. Note that the server program generation device 104 may output the generated server program 13 directly to the compilation device 14.

  The client library generation device 105 acquires the user-defined function program 11, the function list 103, and the target system information 12 from the data storage device 203. The client library generation device 105 generates the client library 16 from the user-defined function program 11 and the function list 103 based on the target system information 12 (step S13). The client library generation device 105 stores the generated client library 16 in the data storage device 203. Note that the client library generation device 105 may directly output the generated client library 16 to the behavioral synthesis device 18.

The compiling device 14 acquires the user-defined function program 11 and the server program 13 from the data storage device 203. The compiling device 14 compiles the user-defined function program 11 and the server program 13 to generate an execution binary 15 (step S14).
The behavioral synthesis device 18 acquires the client library 16, the behavior level description 17, and the target system information 12 from the data storage device 203. The behavior level description 17 describes a description for calling the client library 16. The behavioral synthesis device 18 generates circuit information 19 from the client library 16, the behavior level description 17, and the target system information 12 (step S15).

FIG. 14 is an example of the behavior level description 17. As shown in FIG. 14, the behavior level description 17 describes that the client function of the client library 16 is executed. The client function has the same interface as the user-defined function of the user-defined function program 11.
Hereinafter, processing of the main function P400 included in the behavior level description 17 will be described. Actually, the processing described below is executed by the reconstruction device 603.

The main function P400 executes the func1 function with the data 2, y, & z as arguments (P401). As a result, the client function P205 described above is called.
Next, the main function P400 executes the func2 function with the data x as an argument (P402). As a result, the above-described client function P209 is read.
As described above, in the reconfigurable device 603, the processing contents in the user-defined functions func1 and func2 can be executed in the MPU 601 simply by calling the user-defined functions func1 and func2.

Next, the operation of the target system 6 will be described with reference to FIGS.
FIG. 15 is a flowchart showing operations of the MPU 601 and the reconfiguration device 603. This operation is started when the execution binary 15 is executable by the MPU 601 and the circuit information 19 is written in the reconfiguration device 603. The actual operation of the user-defined function is executed from an interrupt handler activated from the reconfiguration device 603.

The reconfiguring device 603 activates a client function corresponding to the user-defined function based on the circuit information 19 (step S210). This processing corresponds to Step P401 or Step P402 of the behavior level description 17 in FIG. The client function body corresponds to each of P205 and P209 in FIG. Thereafter, the reconfiguration device 603 executes processing included in the client library 16 and the behavior level description 17 based on the circuit information 19.
Next, the reconfiguration device 603 writes the function ID and the argument in the stack data (step S211). In this processing, the function ID setting corresponds to P206 or P210 in FIG. 8, and the argument setting corresponds to P207 or P211 in FIG.

Next, the reconfiguration device 603 initializes stack data control information (step S212). This process corresponds to P202 in FIG. 8, and the value of the control information is initialized to 0 in FIG.
Next, the reconfiguration device 603 generates an interrupt to the MPU 601 (step S213). This process corresponds to S203 in FIG.
At this time, the contents of the stack data when the process of P401 in FIG. 14 is executed are as shown in FIG. 16A. Similarly, the contents of the stack data when the process of P402 is executed are as shown in FIG. 17A.

  The MPU 601 activates an interrupt handler by an interrupt issued from the reconfiguration device 603 (step S201). This process is started by an operating system or the like that operates on the MPU 601. For example, the function P301 in FIG. 9 is registered in advance as a process for an interrupt from the reconfiguration device 603. Accordingly, the MPU 601 activates the function P301 as an interrupt handler in response to the interrupt signal from the interrupt controller 602. That is, the MPU 601 starts executing the processing included in the execution binary 15 in response to the interrupt signal from the interrupt controller 602. Thereafter, the MPU 601 executes processing included in the server program 13 based on the execution binary 15.

Next, the MPU 601 clears the interrupt to the MPU 601 (step S202). This process corresponds to P302 in FIG.
Next, the MPU 601 reads the function ID from the stack data (step S203). This process corresponds to P303 in FIG.
Next, the MPU 601 selects a user-defined function to be executed (step S204). This process corresponds to P304 in FIG. For example, when the function ID read from the stack data is 1, the program after P305 is executed.

Next, the MPU 601 reads out an argument required for the user-defined function from the stack data (step S205). This process corresponds to P306 or P310 in FIG.
Next, the MPU 601 executes a user-defined function (P100 or P101) using the argument read from the stack data (step S206). This processing corresponds to P307 or P311 in FIG.

At this time, when the process of P402 in FIG. 14 is executed, the MPU 601 outputs the execution result to the output device 611 via the input / output interface 608. For example, the execution result is output as shown in FIG.
Next, the MPU 601 writes the return value and return argument of the executed user-defined function in the stack data (step S207). This process corresponds to P308 in FIG.

Next, the MPU 601 updates the stack data control information (step S208). This process corresponds to P312 in FIG. 9, and the value of the control information is updated to 1 in FIG.
At this time, the contents of the stack data when the process of P401 in FIG. 14 is executed are as shown in FIG. 16B. Similarly, the contents of the stack data when the process of P402 is executed are as shown in FIG. 17B.

A series of processes of the server program 13 started by the interrupt handler is finished here.
On the other hand, the reconfigurable device 603 that generated an interrupt to the MPU 601 in step S213 polls the control information of the stack data at regular intervals, and waits until the control information is changed (step S214). This process corresponds to P204 in FIG.

  When the control information is changed in step S208, the reconfiguration device 603 continues to operate, reads the return value and return argument from the stack data, and sets them as the return value and return argument of the user-defined function. This process corresponds to P208 in FIG. Then, the reconfigurable device 603 ends the user-defined function process and returns to the caller process (step S215).

  As described above, according to the present embodiment, in the information processing apparatus, the reconfiguration device 603 can activate a user-defined function designed in advance that operates on the arithmetic processing apparatus 601 via the bus line. I can do it. According to this, by preparing a process to be executed by the reconfiguration device 603 with a user-defined function, the process can be executed by the arithmetic processing device 601 instead. Even if there is a process that can not be executed by the reconfiguration device 603 but can be executed by the arithmetic processing unit 601, it can be replaced by the reconfiguration device 603 by preparing the process with a user-defined function. And can be executed by the arithmetic processing unit 601. Here, if there is a function shared by multiple programs, such as system calls and global functions, prepare that function as a user-defined function or prepare a user-defined function that includes that function. The function can also be used in the reconstruction device 603. That is, it is possible to use the processing shared by the arithmetic processing device 601 from the reconstruction device 603 as well.

  Here, as described as the background art, various processes have been implemented in the reconfigurable device. For this reason, if a common resource such as a system call provided by the operating system can also be used from the reconfigurable device, the convenience of designing the processing contents in the reconfigurable device can be improved. it can. However, it is difficult to mount an operating system on the reconfigurable device described in Patent Documents 1 to 6 and Non-Patent Document 1. This is because enormous computational resources are required to implement the operating system on the reconfigurable device. This is the same even if the location to be mounted on the reconfigurable device is limited to only a part of the functions provided by the operating system. Some of the functions provided by the operating system include, for example, memory management and standard input / output. On the other hand, according to the present embodiment, the reconfigurable device 603 can execute a system call for controlling the shared memory 607 and the input / output interface 608 connected to the bus line with a small number of computing resources. That is, the function provided by the operating system operating on the arithmetic processing device 601 can be used from the reconfiguration device 603.

  Here, when the shared memory 607 is used from the reconfiguration device 603 via the bus access device 605, it is necessary to avoid the area that is used by the MPU 601 and should not be accessed from the reconfiguration device 603. Therefore, there is a problem that extra control is required to access other areas. On the other hand, according to the present embodiment, as described above, a system call for accessing the shared memory 607 from the reconfigurable device 603 can be executed via the arithmetic processing unit 601. As a result, the reconfigurable device 603 can access the shared memory 607 under the management of the operating system executed by the MPU 601. Therefore, the reconfiguration device 603 does not need to perform extra control when accessing the shared memory 607.

  Although the present invention has been described with reference to the exemplary embodiments, the present invention is not limited to the above. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the invention.

  For example, in this embodiment, the program design support system 1 distributes the functions to the program generation device 10, the compilation device 14, and the behavioral synthesis device 18, but all or two of these devices are distributed. It is good also as a structure which implement | achieves a function with one apparatus. The same applies to each device in the program generation device 10.

In addition, at least one of the function extraction device 101, the server program generation device 104, and the client library generation device 105 in the program generation device 10 may be provided outside the program generation device 10.
Further, target data such as a function ID, control information, an argument, a return value, and a return argument may be passed between the MPU 601 and the reconfigurable device 603 via the shared memory 607.

  The program design support system 1 according to the present invention described above supplies a computer with a storage medium storing a program for realizing the functions of the above-described embodiments, and the computer or the CPU or MPU included in the computer executes the program. By doing so, it is possible to configure.

  Further, the program and the execution binary 15 can be stored using various types of non-transitory computer readable media and supplied to the computer. Non-transitory computer readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic recording media (for example, flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (for example, magneto-optical disks), CD-ROMs (Read Only Memory), CD-Rs, CD-R / W, semiconductor memory (for example, mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM), flash ROM, RAM (Random Access Memory)) are included. The program may also be supplied to the computer by various types of transitory computer readable media.

  Examples of transitory computer readable media include electrical signals, optical signals, and electromagnetic waves. The temporary computer-readable medium can supply the program to the computer via a wired communication path such as an electric wire and an optical fiber, or a wireless communication path.

  Further, when the computer executes the program that realizes the functions of the above-described embodiment, not only the functions of the above-described embodiment are realized, but also the computer is operating on the basis of the instructions of this program. A case where the functions of the above-described embodiment are realized in cooperation with an operating system or application software is also included in the embodiment of the invention.

  Further, when the functions of the above-described embodiment are realized by performing all or part of the processing of the program by a function expansion board inserted into the computer or a function expansion unit connected to the computer, the present invention may be implemented. It is included in the form.

  A part or all of the above-described embodiment can be described as in the following supplementary notes, but is not limited thereto.

(Supplementary Note 1) An arithmetic processing device that executes a program including a predetermined process, and an output request signal that requests execution of the program to the arithmetic processing device, and a process that is used in the predetermined process A reconfigurable device having information, and the arithmetic processing unit activates the program in response to an execution request signal output from the reconfigurable device, reads the processing information from the reconfigurable device, and An information processing apparatus that executes the process.

(Supplementary Note 2) The program includes a function for executing the predetermined process, the processing information is an argument of the function, and the program sets an argument read from the reconfigurable device as the function. The information processing apparatus according to appendix 1, which executes the function.

(Supplementary Note 3) The program includes a plurality of the functions, the reconfigurable device has function specifying information for specifying the function, and the program reads the function specifying information from the reconfigurable device and reads the function The information processing apparatus according to attachment 2, wherein the function specified by the function specifying information is executed.

(Supplementary Note 4) When the program executes the function, the program outputs a return value of the function, and the reconfiguration device acquires a return value output from the program of the arithmetic processing unit. The information processing apparatus described.

(Supplementary Note 5) The reconfigurable device further includes a storage unit that stores the function specifying information, the argument, and the return value, and the reconfigurable device specifies the function when executing the function The function specifying information and the argument of the function to be stored are stored in the storage unit, and the program reads the function specifying information and the argument stored in the storage unit and outputs the return value and stores it in the storage unit The information processing apparatus according to attachment 4.

(Supplementary note 6) The arithmetic processing unit executes an operating system and executes the program on the operating system, and the predetermined processing includes execution of a system call of the operating system. The information processing apparatus according to any one of 1 to 5.

(Supplementary Note 7) The information processing apparatus further includes an interrupt controller that outputs an interrupt signal to the arithmetic processing unit, and the reconfiguration device outputs the execution request signal to the interrupt controller, and the interrupt controller Outputs an interrupt signal to the arithmetic processing unit in response to the execution request signal output from the reconfigurable device, and the arithmetic processing unit outputs the program in response to the interrupt signal output from the interrupt controller. The information processing apparatus according to any one of supplementary notes 1 to 6, wherein the information processing apparatus is activated.

(Supplementary note 8) The information processing apparatus according to supplementary note 5, wherein the storage unit is a storage element included in the reconstruction device.

(Supplementary note 9) The reconfiguration device outputs an execution request signal for requesting execution of a program including a predetermined process, and the arithmetic processing unit outputs the program according to the execution request signal output from the reconfiguration device. An information processing method for starting processing, reading processing information used in the predetermined processing from the reconfigurable device, and executing processing of the processing.

(Additional remark 10) Based on the 1st source program containing a predetermined process, it is used for the production | generation of the circuit information of a reconfigurable device, and makes the said reconfigurable device output the execution request signal which requests | requires execution of the said predetermined process Based on the execution request signal output from the reconfigurable device and used to generate an execution program executed by the arithmetic processing unit based on the first source program and a library generation unit that generates a library including processing A source program generation unit that generates a second source program including a process for causing the arithmetic processing device to read processing information used in the predetermined process from the reconfigurable device and executing the predetermined process; Design support system with

(Supplementary Note 11) The first source program includes a plurality of the functions, and the design support system identifies the function and the function for each of the plurality of functions based on the first source program. A function correspondence information generation unit that generates function correspondence information in association with the function identification information to be performed, and the library generation unit identifies the function when executing the function based on the function correspondence information. The source program generating unit reads the function specifying information from the reconfiguring device to the arithmetic processing unit based on the function correspondence information. Including a process for executing the function specified by the read function specifying information in the second source program, Design support system according to the serial 10.

(Supplementary Note 12) The design support system generates circuit information for generating circuit information of the reconfigurable device based on the library generated by the library generating unit and an operation level description indicating the operation of the reconfigurable device. The design according to appendix 10 or 11, further comprising: a compiling unit that generates an execution program to be executed by the arithmetic processing unit based on the second source program generated by the source program generating unit Support system.

(Supplementary note 13) When executed in response to the execution request signal output from the reconfigurable device, the processing information used in the predetermined processing is read from the reconfigurable device, and the read processing information is used. And a program for causing the arithmetic processing unit to execute processing for executing the predetermined processing.

  This application claims the priority on the basis of Japanese application Japanese Patent Application No. 2010-206659 for which it applied on September 15, 2010, and takes in those the indications of all here.

1 Program design support system
2 Design support system 6 Target system
7 Information processing apparatus 10 Program generation apparatus
11 User-defined function programs
12 Target system information
13 Server program
14 Compile device
15 Execution binary
16 Client library
17 Behavior level description
18 Behavioral synthesis device
19 Circuit information
21 Library generator 22 Source program generator 25 First source program 26 Second source program 27 Library 30 Input device
40 Output device
50 Network device 71 Arithmetic processing device 72, 603 Reconfiguration device
101 function extractor
103 Function list
104 Server program generation device
105 Client library generation device
200 CPU
201 Main memory
202 storage medium
203 data storage device
204 Main memory control interface unit
205 Storage medium control interface unit
206 Data storage control interface unit
207 Input control interface unit
208 Output control interface unit
209 Network control interface part
601 MPU
602 Interrupt controller
604 reading device
605 bus access device
606 writing device
607 shared memory
608 I / O interface
609 Network interface
610 input device
611 Output device
612 network
613 bus line
2000 bus
6030, 6031, 6032 Memory element

The present invention relates to an information processing apparatus, it relates to an information processing method, design support system, and programs.

An object of the present invention, in order to solve the above problems, reconfigurable devices processing information processing apparatus capable of executing replaced by the processing unit, information processing method, a design support system and program Is to provide.

Program according to the fourth embodiment of the present invention, when executed in response to the execution signal output from the reconfigurable device, the process of reading processing information the use in a given process from the reconstruction device a program for executing a process of executing the predetermined processing by using the read processing information to the processing unit.

According to each aspect of the present invention described above, the information processing apparatus can be performed in an alternate processing of the reconstruction device processor, information processing method, it is possible to provide a design support system and programs.

Claims (10)

An arithmetic processing unit that executes a program including predetermined processing;
A reconfiguration device that outputs processing request signals for requesting execution of the program to the arithmetic processing unit, and has processing information used in the predetermined processing;
The arithmetic processing unit starts the program in response to an execution request signal output from the reconfigurable device, reads the processing information from the reconfigurable device, and executes the predetermined process.
Information processing device. The program includes a function for executing the predetermined process,
The processing information is an argument of the function,
The program sets an argument read from the reconfigurable device in the function and executes the function.
The information processing apparatus according to claim 1. The program includes a plurality of the functions,
The reconstruction device has function specifying information for specifying the function;
The program reads the function specifying information from the reconfigurable device and executes a function specified by the read function specifying information.
The information processing apparatus according to claim 2. When the program executes the function, it outputs a return value of the function,
The reconstruction device acquires a return value output from the program of the arithmetic processing unit;
The information processing apparatus according to claim 3. The reconfigurable device further comprises storage means for storing the function specifying information, the argument, and the return value,
The reconfigurable device stores function specifying information for specifying the function and an argument of the function in the storage unit when executing the function,
The program reads the function specifying information and the argument stored in the storage unit, outputs the return value, and stores it in the storage unit.
The information processing apparatus according to claim 4. The arithmetic processing unit executes an operating system and executes the program on the operating system,
The predetermined processing includes execution of a system call of the operating system.
The information processing apparatus according to any one of claims 1 to 5. The reconfigurable device outputs an execution request signal for requesting execution of a program including predetermined processing,
The arithmetic processing unit activates the program in response to an execution request signal output from the reconstruction device, reads processing information used in the predetermined processing from the reconstruction device, and performs processing of the processing Run,
Information processing method. A library that includes a process that is used to generate circuit information of a reconfigurable device based on a first source program that includes a predetermined process, and that causes the reconfigurable device to output an execution request signal that requests execution of the predetermined process Library generating means for generating
Based on the first source program, it is used to generate an execution program to be executed by the arithmetic processing device, and the arithmetic processing device sends the execution device to the arithmetic processing device in response to an execution request signal output from the reconfiguring device. A design support system comprising: source program generation means for generating a second source program including processing for reading processing information used in predetermined processing and executing the predetermined processing. The first source program includes a plurality of the functions,
The design support system generates function correspondence information that associates the function with function specifying information for specifying the function for each of the plurality of functions based on the first source program. Further comprising generating means,
The library generation means includes, in the library, a process for causing the reconfigurable device to hold function specifying information for specifying the function when executing the function based on the function correspondence information.
The source program generation unit is configured to cause the arithmetic processing unit to read the function specifying information from the reconfigurable device based on the function correspondence information, and to execute a function specified by the read function specifying information. Included in the second source program;
The design support system according to claim 8. A process of reading processing information used in a predetermined process from the reconfiguration device when executed in response to an execution request signal output from the reconfiguration device;
A process of executing the predetermined process using the read process information;
A non-transitory computer-readable medium storing a program for causing an arithmetic processing unit to execute the program.

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