JPWO2009139366A1 - substrate - Google Patents
substrate Download PDFInfo
- Publication number
- JPWO2009139366A1 JPWO2009139366A1 JP2010511976A JP2010511976A JPWO2009139366A1 JP WO2009139366 A1 JPWO2009139366 A1 JP WO2009139366A1 JP 2010511976 A JP2010511976 A JP 2010511976A JP 2010511976 A JP2010511976 A JP 2010511976A JP WO2009139366 A1 JPWO2009139366 A1 JP WO2009139366A1
- Authority
- JP
- Japan
- Prior art keywords
- metal
- deposited
- substrate
- substrate according
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 96
- 229910052751 metal Inorganic materials 0.000 claims abstract description 174
- 239000002184 metal Substances 0.000 claims abstract description 172
- 239000000203 mixture Substances 0.000 claims abstract description 41
- 150000001875 compounds Chemical class 0.000 claims abstract description 24
- 239000000463 material Substances 0.000 claims abstract description 20
- 238000010438 heat treatment Methods 0.000 claims abstract description 18
- 238000007772 electroless plating Methods 0.000 claims description 41
- 229910052759 nickel Inorganic materials 0.000 claims description 24
- 150000003839 salts Chemical class 0.000 claims description 19
- 239000000243 solution Substances 0.000 claims description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 18
- KRKNYBCHXYNGOX-UHFFFAOYSA-N citric acid Chemical compound OC(=O)CC(O)(C(O)=O)CC(O)=O KRKNYBCHXYNGOX-UHFFFAOYSA-N 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 14
- 239000002585 base Substances 0.000 claims description 13
- 229910021332 silicide Inorganic materials 0.000 claims description 12
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 12
- 239000007864 aqueous solution Substances 0.000 claims description 11
- 239000002253 acid Substances 0.000 claims description 9
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 8
- 150000002222 fluorine compounds Chemical class 0.000 claims description 8
- 238000001465 metallisation Methods 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 229920005591 polysilicon Polymers 0.000 claims description 8
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 claims description 6
- 229910052783 alkali metal Inorganic materials 0.000 claims description 6
- 150000001340 alkali metals Chemical class 0.000 claims description 6
- 239000003638 chemical reducing agent Substances 0.000 claims description 6
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 6
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- 229910021529 ammonia Inorganic materials 0.000 claims description 4
- 229910052802 copper Inorganic materials 0.000 claims description 4
- 239000003002 pH adjusting agent Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 239000007788 liquid Substances 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 28
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 47
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 33
- 229910052710 silicon Inorganic materials 0.000 description 33
- 239000010703 silicon Substances 0.000 description 33
- 239000010408 film Substances 0.000 description 30
- 238000007747 plating Methods 0.000 description 27
- 239000010409 thin film Substances 0.000 description 21
- 238000004544 sputter deposition Methods 0.000 description 7
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 6
- 239000003054 catalyst Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000003628 erosive effect Effects 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 229910017052 cobalt Inorganic materials 0.000 description 4
- 239000010941 cobalt Substances 0.000 description 4
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 4
- 238000011109 contamination Methods 0.000 description 4
- 229910052700 potassium Inorganic materials 0.000 description 4
- 229910052708 sodium Inorganic materials 0.000 description 4
- 239000011734 sodium Substances 0.000 description 4
- DGAQECJNVWCQMB-PUAWFVPOSA-M Ilexoside XXIX Chemical compound C[C@@H]1CC[C@@]2(CC[C@@]3(C(=CC[C@H]4[C@]3(CC[C@@H]5[C@@]4(CC[C@@H](C5(C)C)OS(=O)(=O)[O-])C)C)[C@@H]2[C@]1(C)O)C)C(=O)O[C@H]6[C@@H]([C@H]([C@@H]([C@H](O6)CO)O)O)O.[Na+] DGAQECJNVWCQMB-PUAWFVPOSA-M 0.000 description 3
- ZLMJMSJWJFRBEC-UHFFFAOYSA-N Potassium Chemical compound [K] ZLMJMSJWJFRBEC-UHFFFAOYSA-N 0.000 description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000005237 degreasing agent Methods 0.000 description 3
- 239000013527 degreasing agent Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 150000002815 nickel Chemical class 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- ACVYVLVWPXVTIT-UHFFFAOYSA-N phosphinic acid Chemical compound O[PH2]=O ACVYVLVWPXVTIT-UHFFFAOYSA-N 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 239000011591 potassium Substances 0.000 description 3
- 238000006467 substitution reaction Methods 0.000 description 3
- 238000004381 surface treatment Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical class [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- DHMQDGOQFOQNFH-UHFFFAOYSA-N Glycine Chemical compound NCC(O)=O DHMQDGOQFOQNFH-UHFFFAOYSA-N 0.000 description 2
- OFOBLEOULBTSOW-UHFFFAOYSA-N Malonic acid Chemical compound OC(=O)CC(O)=O OFOBLEOULBTSOW-UHFFFAOYSA-N 0.000 description 2
- PWHULOQIROXLJO-UHFFFAOYSA-N Manganese Chemical compound [Mn] PWHULOQIROXLJO-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000012298 atmosphere Substances 0.000 description 2
- RJTANRZEWTUVMA-UHFFFAOYSA-N boron;n-methylmethanamine Chemical compound [B].CNC RJTANRZEWTUVMA-UHFFFAOYSA-N 0.000 description 2
- -1 conventionally Inorganic materials 0.000 description 2
- 230000006378 damage Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000005238 degreasing Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011261 inert gas Substances 0.000 description 2
- 229910052748 manganese Inorganic materials 0.000 description 2
- 239000011572 manganese Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 2
- 229910021334 nickel silicide Inorganic materials 0.000 description 2
- LGQLOGILCSXPEA-UHFFFAOYSA-L nickel sulfate Chemical compound [Ni+2].[O-]S([O-])(=O)=O LGQLOGILCSXPEA-UHFFFAOYSA-L 0.000 description 2
- 229910000363 nickel(II) sulfate Inorganic materials 0.000 description 2
- PIBWKRNGBLPSSY-UHFFFAOYSA-L palladium(II) chloride Chemical compound Cl[Pd]Cl PIBWKRNGBLPSSY-UHFFFAOYSA-L 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- NROKBHXJSPEDAR-UHFFFAOYSA-M potassium fluoride Chemical compound [F-].[K+] NROKBHXJSPEDAR-UHFFFAOYSA-M 0.000 description 2
- 150000003377 silicon compounds Chemical class 0.000 description 2
- PUZPDOWCWNUUKD-UHFFFAOYSA-M sodium fluoride Chemical compound [F-].[Na+] PUZPDOWCWNUUKD-UHFFFAOYSA-M 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- XXSPKSHUSWQAIZ-UHFFFAOYSA-L 36026-88-7 Chemical compound [Ni+2].[O-]P=O.[O-]P=O XXSPKSHUSWQAIZ-UHFFFAOYSA-L 0.000 description 1
- 235000001674 Agaricus brunnescens Nutrition 0.000 description 1
- FEWJPZIEWOKRBE-JCYAYHJZSA-N Dextrotartaric acid Chemical compound OC(=O)[C@H](O)[C@@H](O)C(O)=O FEWJPZIEWOKRBE-JCYAYHJZSA-N 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910005540 GaP Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000004471 Glycine Substances 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910021586 Nickel(II) chloride Inorganic materials 0.000 description 1
- FEWJPZIEWOKRBE-UHFFFAOYSA-N Tartaric acid Natural products [H+].[H+].[O-]C(=O)C(O)C(O)C([O-])=O FEWJPZIEWOKRBE-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- MCMNRKCIXSYSNV-UHFFFAOYSA-N ZrO2 Inorganic materials O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 125000003178 carboxy group Chemical group [H]OC(*)=O 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 230000000977 initiatory effect Effects 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- QMMRZOWCJAIUJA-UHFFFAOYSA-L nickel dichloride Chemical compound Cl[Ni]Cl QMMRZOWCJAIUJA-UHFFFAOYSA-L 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 150000002941 palladium compounds Chemical class 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 235000003270 potassium fluoride Nutrition 0.000 description 1
- 239000011698 potassium fluoride Substances 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- HWEYZGSCHQNNEH-UHFFFAOYSA-N silicon tantalum Chemical compound [Si].[Ta] HWEYZGSCHQNNEH-UHFFFAOYSA-N 0.000 description 1
- SIGUVTURIMRFDD-UHFFFAOYSA-M sodium dioxidophosphanium Chemical compound [Na+].[O-][PH2]=O SIGUVTURIMRFDD-UHFFFAOYSA-M 0.000 description 1
- 235000013024 sodium fluoride Nutrition 0.000 description 1
- 239000011775 sodium fluoride Substances 0.000 description 1
- 229910001379 sodium hypophosphite Inorganic materials 0.000 description 1
- 238000001179 sorption measurement Methods 0.000 description 1
- 239000003381 stabilizer Substances 0.000 description 1
- 239000004094 surface-active agent Substances 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
- 239000011975 tartaric acid Substances 0.000 description 1
- 235000002906 tartaric acid Nutrition 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/1601—Process or apparatus
- C23C18/1603—Process or apparatus coating on selected surface areas
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/1601—Process or apparatus
- C23C18/1603—Process or apparatus coating on selected surface areas
- C23C18/1605—Process or apparatus coating on selected surface areas by masking
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/1601—Process or apparatus
- C23C18/1633—Process of electroless plating
- C23C18/1635—Composition of the substrate
- C23C18/1639—Substrates other than metallic, e.g. inorganic or organic or non-conductive
- C23C18/1642—Substrates other than metallic, e.g. inorganic or organic or non-conductive semiconductor
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/1601—Process or apparatus
- C23C18/1633—Process of electroless plating
- C23C18/1689—After-treatment
- C23C18/1692—Heat-treatment
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C18/00—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating
- C23C18/16—Chemical coating by decomposition of either liquid compounds or solutions of the coating forming compounds, without leaving reaction products of surface material in the coating; Contact plating by reduction or substitution, e.g. electroless plating
- C23C18/31—Coating with metals
- C23C18/32—Coating with nickel, cobalt or mixtures thereof with phosphorus or boron
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
Landscapes
- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Organic Chemistry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Inorganic Chemistry (AREA)
- Chemically Coating (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
本発明は、ゲート電極およびソース・ドレイン領域の抵抗を下げることができ、電流効率を上げることができる基板を提供することを目的とする。さらに、微細化が可能であり、煩雑な工程を必要とせずに製造可能である基板を提供することを目的とする。表面に周囲とは異なる組成の領域部分を有する基材の、特定の一つまたは複数の該組成の領域部分の表面に選択的に、金属を堆積し、熱処理を施して、金属が堆積した領域部分の一部または全てで当該金属と、金属が堆積した基材表面領域部分を構成する元素との化合物を形成してなる基板であり、金属が堆積した領域部分の一部で当該金属と、金属が堆積した基材表面領域部分を構成する元素との化合物を形成し、かつ堆積させた該金属の一部が未反応の金属として残ってなることが好ましい。It is an object of the present invention to provide a substrate that can reduce the resistance of the gate electrode and the source / drain regions and increase the current efficiency. Furthermore, it aims at providing the board | substrate which can be refined | miniaturized and can be manufactured without requiring a complicated process. A region where a metal is selectively deposited on the surface of one or more specific region portions of the composition of the substrate having a region portion having a composition different from the surroundings on the surface, and a heat treatment is performed to deposit the metal. It is a substrate formed by forming a compound of the metal and an element constituting the base material surface region portion where the metal is deposited in a part or all of the portion, and the metal in a part of the region portion where the metal is deposited, It is preferable that a compound is formed with an element constituting the substrate surface region where the metal is deposited, and a part of the deposited metal remains as an unreacted metal.
Description
本発明は、トランジスタ等の半導体デバイスに用いる基板に関する。 The present invention relates to a substrate used for a semiconductor device such as a transistor.
近年トランジスタ等の半導体デバイスにおいては、微細化が望まれている。
今までは、トランジスタのゲート長を短くしゲート絶縁膜を更に薄くすることにより微細化を図ってきたが、その限界が認識されるようになってきた。その限界を打ち破る技術として、（１）ゲート絶縁膜およびゲート電極向け新材料、（２）電子移動度を高める歪シリコン（ゲルマニウム）、（３）新規構造等が注目されている。In recent years, miniaturization is desired in semiconductor devices such as transistors.
Until now, miniaturization has been attempted by shortening the gate length of the transistor and further reducing the thickness of the gate insulating film, but the limitation has been recognized. Attention has been focused on technologies that break through these limitations: (1) new materials for gate insulating films and gate electrodes, (2) strained silicon (germanium) that increases electron mobility, and (3) new structures.
例えば上記（１）に関するゲート周りの新技術では、トランジスタにはソースとドレイン間を流れる電流がゲートに流れ込まないようにゲートの下にゲート絶縁膜と呼ぶ薄膜を形成している。その薄膜が薄いほどトランジスタが高速に動作することになるが、そのかわりゲートリーク電流も増大することになる。近年の微細化に伴いリーク電流の問題は顕著になりつつある。それを防ぐ方法として、（ａ）Ｈｉｇｈ−ｋ材料の採用、（ｂ）メタルゲートの採用、が考えられている。例えば、Ｈｉｇｈ−ｋ材料として、二酸化ジルコニウム、酸化ハフニウム、二酸化チタン、五酸化タンタルなどが検討されており、ゲートリーク電流が１／１０００に削減されることが確認されている。 For example, in the new technology around the gate related to the above (1), a thin film called a gate insulating film is formed under the gate so that current flowing between the source and drain does not flow into the gate. The thinner the thin film, the faster the transistor operates, but the gate leakage current increases instead. With the recent miniaturization, the problem of leakage current is becoming prominent. In order to prevent this, (a) adoption of a high-k material and (b) adoption of a metal gate are considered. For example, zirconium dioxide, hafnium oxide, titanium dioxide, tantalum pentoxide, and the like have been studied as high-k materials, and it has been confirmed that the gate leakage current is reduced to 1/1000.
一方、メタルゲートに関しては、従来のポリシリコンではなく抵抗が低いニッケルシリサイドやチタンナイトライド、タンタルシリコンナイトライドなどが検討されている。ゲート電極として抵抗が低いメタルゲートを用いることにより、ゲート抵抗とソース・ドレイン間の抵抗を低減できることになる。更に高機能化を図るためには、薄膜化が望まれている。 On the other hand, regarding metal gates, nickel silicide, titanium nitride, tantalum silicon nitride, and the like, which have low resistance, are being studied instead of conventional polysilicon. By using a metal gate having a low resistance as the gate electrode, the gate resistance and the resistance between the source and drain can be reduced. In order to further increase the functionality, it is desired to reduce the thickness.
一方、ソース・ドレインはショートチャネル効果抑制のため接合深さを浅くすることが推進され、接合深さを浅くすることによる抵抗値の増大が問題となっている。抵抗の増大は駆動電流を低下させる。このためソース・ドレインの抵抗を下げる必要がある。従来技術では、ソース・ドレインの抵抗を下げるため、高融点金属を堆積し、熱処理でシリサイドを形成するが、Ｓｉを消費するためソース・ドレイン接合深さ以上に厚いシリサイドを形成できない。 On the other hand, for the source / drain, it is promoted to reduce the junction depth in order to suppress the short channel effect, and there is a problem that the resistance value increases due to the reduction of the junction depth. Increasing the resistance decreases the drive current. For this reason, it is necessary to lower the resistance of the source / drain. In the prior art, a refractory metal is deposited to reduce the resistance of the source / drain, and silicide is formed by heat treatment. However, since the silicon is consumed, a silicide thicker than the source / drain junction depth cannot be formed.
また、従来トランジスタの製造プロセスにおいて、スパッタリングとエッチングを駆使して必要部に金属薄膜を形成するという方法が取られてきた。
いくつかの異なる組成領域部分から構成される基板の表面、例えばシリコンとシリコンオキサイドから構成される基板の表面の一部にシリサイドを形成する場合、従来はスパッタリング法などにより全面に金属を堆積して熱処理を施し、シリコンに接する領域部分のみシリサイド化し、未反応の金属を除去することにより、基板表面の一部を選択的にシリサイド化する工程がとられていた。しかし、この場合は、未反応の金属は除去せざるを得ず、選択的に残すことができず、シリサイド部を含む領域部分の抵抗値がシリサイド化した領域部分の抵抗値で決まる。このシリサイド化した領域部分をゲート電極とする場合、その抵抗値は低いことが望まれる。シリサイド化した領域部分を厚くすると抵抗値が下がるが、薄膜化が望まれ、それ以上抵抗値を下げることができなかった。また、このシリサイド化した領域部分をソース・ドレイン領域とする場合、ソース・ドレイン領域は接合深さが浅く、抵抗値が低いことが望まれる。接合深さより深くシリサイド層を形成するわけにはいかないため、ソース・ドレインの抵抗値をそれ以上下げることができなかった。Further, in the conventional transistor manufacturing process, a method of forming a metal thin film on a necessary portion by utilizing sputtering and etching has been taken.
When silicide is formed on the surface of a substrate composed of several different composition regions, for example, a part of the surface of a substrate composed of silicon and silicon oxide, conventionally, metal is deposited on the entire surface by sputtering or the like. A step of selectively silicidating a part of the substrate surface by applying heat treatment to silicidize only the region in contact with silicon and removing unreacted metal has been performed. However, in this case, unreacted metal must be removed and cannot be selectively left, and the resistance value of the region including the silicide portion is determined by the resistance value of the silicided region. When the silicided region is used as the gate electrode, it is desirable that the resistance value be low. When the silicided region is thickened, the resistance value decreases. However, a thin film is desired, and the resistance value cannot be further reduced. Further, when the silicided region is used as a source / drain region, it is desirable that the source / drain region has a shallow junction depth and a low resistance value. Since the silicide layer cannot be formed deeper than the junction depth, the resistance value of the source / drain could not be lowered any further.
このような問題点に対し、例えば特許文献１（米国特許出願公開第２００５／０２１２０５８号明細書）では、ゲート電極とソース・ドレイン領域を有するシリコン基板にスパッタリング等の物理的気相成長法（ＰＶＤ）法により一面に金属薄膜を形成し、熱処理によりシリコンに接する領域部分のみをシリサイド化し、未反応の金属薄膜を除去した後に、無電解めっきによりゲート電極とソース・ドレイン領域上に金属膜を形成し、ゲート電極、ソース・ドレイン領域の抵抗値を下げる方法が開示されている。この方法では、ＰＶＤ法により金属薄膜を形成していることから、選択性がなく、従ってシリサイド化後に不要な部分の金属薄膜を剥離することが必要である。また、その剥離工程で必要な部分の金属薄膜も剥離してしまうことになり、結果的に電極部のシリサイドした膜と金属膜の共存が不可能になっていた。 For example, in Patent Document 1 (US Patent Application Publication No. 2005/0212058), a physical vapor deposition method (PVD) such as sputtering is applied to a silicon substrate having a gate electrode and source / drain regions. ) Method to form a metal thin film on one side, silicidize only the region in contact with silicon by heat treatment, remove the unreacted metal thin film, and then form the metal film on the gate electrode and source / drain regions by electroless plating However, a method for reducing the resistance value of the gate electrode and the source / drain region is disclosed. In this method, since the metal thin film is formed by the PVD method, there is no selectivity, and therefore it is necessary to peel off the unnecessary portion of the metal thin film after silicidation. In addition, the metal thin film at a necessary portion in the peeling process is also peeled off. As a result, the silicided film and the metal film in the electrode portion cannot coexist.
また、近年、基板上に形成する金属薄膜を無電解めっきにて形成することが検討されている。
特許文献２（特開平２−６３１２９号公報）には、無電解めっきによるゲート電極の形成方法について開示されているが、ゲート電極の断面を増大させて電界効果トランジスタのゲート抵抗の低下を防ぐためゲート電極の形状をマッシュルーム型にしたことを特徴とするもので、めっきをしたくない場所にはレジストを使用している。In recent years, it has been studied to form a metal thin film formed on a substrate by electroless plating.
Patent Document 2 (Japanese Patent Application Laid-Open No. 2-63129) discloses a method for forming a gate electrode by electroless plating. In order to prevent the gate resistance of a field effect transistor from decreasing by increasing the cross section of the gate electrode. The gate electrode has a mushroom shape, and a resist is used where plating is not desired.
特許文献３（特開平３−１５５６２９号公報）には、集積回路の電極形成に無電解ニッケルめっきを用いることが開示されている。シリコンウェハー上に酸化シリコン膜を形成し、フォトリソグラフを用いて下地チタン膜を露出させ、塩化パラジウム水溶液によるチタン膜表面への触媒付与により１μｍ厚の無電解ニッケルめっき膜を形成することにより電極を形成する方法が開示されている。無電解ニッケルめっきを開始する触媒として塩化パラジウムを必要とし、形成した電極の膜厚が１μｍと厚い。 Patent Document 3 (Japanese Patent Laid-Open No. 3-155629) discloses the use of electroless nickel plating for electrode formation of an integrated circuit. A silicon oxide film is formed on a silicon wafer, the underlying titanium film is exposed using photolithography, and a 1 μm thick electroless nickel plating film is formed by applying a catalyst to the titanium film surface with an aqueous palladium chloride solution. A method of forming is disclosed. Palladium chloride is required as a catalyst for initiating electroless nickel plating, and the formed electrode is as thick as 1 μm.
特許文献４（特開２００５−３３６６００号公報）では、シリコン基板上にめっきをするために、フッ酸、フッ化アンモニウムと無電解めっき用触媒金属となるパラジウム化合物を含む水溶液に浸漬して触媒化後、無電解ニッケルめっきを行っており、触媒の付与が必要である。また、めっき選択性の発現が困難である。 In Patent Document 4 (Japanese Patent Laid-Open No. 2005-336600), in order to plate on a silicon substrate, it is catalyzed by dipping in an aqueous solution containing hydrofluoric acid, ammonium fluoride, and a palladium compound serving as a catalyst metal for electroless plating. Thereafter, electroless nickel plating is performed, and it is necessary to apply a catalyst. Moreover, it is difficult to express plating selectivity.
シリコンと酸化シリコン上のめっきの選択性については、非特許文献１（丹羽大介（Daisuke Niwa）他、エレクトロキミカ・アクタ（Electrochimica Acta） ４８（２００３）、ｐ．１２９５−１３００）にＳｉ上への選択無電解ニッケルめっきについて紹介している。１段目の核形成段階としては、還元剤が入っていないＮｉ塩水溶液を使用し、２段目の成膜工程においては、還元剤が入った水溶液を使用している。この方法によると、ＳｉとＳｉＯ2の共存する基板において、Ｓｉ上に選択的にニッケル膜を形成できることが示されている。For the selectivity of plating on silicon and silicon oxide, see Non-Patent Document 1 (Daisuke Niwa et al., Electrochimica Acta 48 (2003), p.1295-1300). Introduces selective electroless nickel plating. As the first nucleation stage, an Ni salt aqueous solution containing no reducing agent is used, and in the second stage film forming process, an aqueous solution containing a reducing agent is used. According to this method, it is shown that a nickel film can be selectively formed on Si in a substrate in which Si and SiO 2 coexist.
また、特許文献５（特許第３２３５５８３号公報）においても表面にシリコンの領域と酸化シリコンの領域を有するシリコン基板のシリコン上に無電解めっきにより選択的に金属膜を形成し、加熱処理しシリサイド化する半導体の製造方法が記載されている。シリサイド化する金属膜中にあらかじめ下地のシリコンにイオン注入した元素と同種の導電機構を有する不純物を含有させることにより、高い不純物濃度を有する微細なパターンにおいて、シリサイドを自己整合的に形成した後でもゲートや拡散層の抵抗を低減できるとしている。特許文献５では無電解めっきにより選択的に金属膜を形成できるとしているが、実際にはこの方法では無電解めっきにより選択的に金属膜を形成するのは困難である。即ち、無電解めっきにより選択的に金属膜を形成するために、シリコン上に選択的にＰｄ等の触媒を付与するとしているが、Ｐｄ吸着に選択性の問題があり、実際にＰｄを選択的に付着させるには非選択部分の保護など、何らかの手段が必要となり、煩雑な工程が必要となる。事実、前記特許文献５においても、非選択成長となった金属めっき膜は熱処理を行った後にウェットエッチングすることにより除去することが教示されている。 Also in Patent Document 5 (Japanese Patent No. 3235583), a metal film is selectively formed by electroless plating on silicon of a silicon substrate having a silicon region and a silicon oxide region on the surface, followed by heat treatment and silicidation. A semiconductor manufacturing method is described. Even after the silicide is formed in a self-aligned manner in a fine pattern having a high impurity concentration by including an impurity having a conductive mechanism similar to the element ion-implanted in the underlying silicon into the metal film to be silicided. The gate and diffusion layer resistance can be reduced. In Patent Document 5, a metal film can be selectively formed by electroless plating. However, in practice, it is difficult to selectively form a metal film by electroless plating. That is, in order to selectively form a metal film by electroless plating, a catalyst such as Pd is selectively applied on silicon. However, there is a problem of selectivity in Pd adsorption, and Pd is actually selected selectively. In order to make it adhere, some means, such as protection of a non-selection part, is needed, and a complicated process is needed. In fact, Patent Document 5 also teaches that the non-selective growth metal plating film is removed by wet etching after heat treatment.
本発明は、ゲート電極およびソース・ドレイン領域の抵抗を下げることができ、電流効率を上げることができる基板を提供することを目的とする。
さらに、微細化が可能であり、煩雑な工程を必要とせずに製造可能である基板を提供することを目的とする。It is an object of the present invention to provide a substrate that can reduce the resistance of the gate electrode and the source / drain regions and increase the current efficiency.
Furthermore, it aims at providing the board | substrate which can be refined | miniaturized and can be manufactured without requiring a complicated process.
本発明者らはかかる状況を鑑み、被めっき材の材質により選択性を発現できる無電解めっき法に着目し、表面に異なる組成の領域部分を有する基材において、特定の一つまたは複数の組成の領域部分の表面に、当該表面を大きく粗すことなく選択的に金属を堆積し、熱処理を施して、金属が堆積した領域部分の一部または全てで当該金属と、金属が堆積した基材表面領域部分を構成する元素との化合物を形成してなる基板とすることにより、煩雑な工程を必要とせず、微細化が可能であり、このような基板を用いることにより、トランジスタにおいてゲート電極およびソース・ドレイン領域の抵抗を下げることができることを見出し本発明に至った。
即ち、本発明は以下のとおりである。In view of such a situation, the present inventors focused on an electroless plating method capable of expressing selectivity depending on the material of a material to be plated, and in a substrate having a region portion having a different composition on the surface, specific one or more compositions The metal is selectively deposited on the surface of the region portion without greatly roughening the surface, and heat treatment is performed, so that the metal and the base material on which the metal is deposited are partially or all of the region portion where the metal is deposited. By using a substrate formed by forming a compound with an element constituting the surface region portion, a complicated process is not required, and miniaturization is possible. By using such a substrate, a gate electrode and a transistor can be formed in a transistor. The inventors have found that the resistance of the source / drain regions can be lowered, and have reached the present invention.
That is, the present invention is as follows.
（１）表面に周囲とは異なる組成の領域部分を有する基材の、特定の一つまたは複数の該組成の領域部分の表面に選択的に、金属を堆積し、熱処理を施して、金属が堆積した領域部分の一部または全てで当該金属と、金属が堆積した基材表面領域部分を構成する元素との化合物を形成してなる基板。
（２）前記基板が、金属が堆積した領域部分の一部で当該金属と、金属が堆積した基材表面領域部分を構成する元素との化合物を形成し、かつ堆積させた該金属の一部が未反応の金属として残ってなる前記（１）記載の基板。(1) A metal is selectively deposited on the surface of a specific one or a plurality of region portions having the composition different from the surroundings on the surface, and heat treatment is performed. A substrate formed by forming a compound of the metal and an element constituting the base material surface region portion where the metal is deposited on a part or all of the deposited region portion.
(2) The substrate forms a compound of the metal and an element constituting the base material surface region portion where the metal is deposited in a part of the region where the metal is deposited, and a portion of the deposited metal The substrate according to (1), wherein is left as an unreacted metal.
（３）前記基板にさらに金属を堆積して、初期に選択的に金属を堆積した基板表面領域部分の範囲を超えて、金属堆積部を延伸させることにより、互いに離れた初期に金属を堆積した基板表面領域部分どうしをさらに堆積した金属堆積部で接続させてなる前記（１）または（２）に記載の基板。 (3) The metal was further deposited on the substrate, and the metal was deposited at an early stage away from each other by extending the metal deposition part beyond the range of the substrate surface region where the metal was selectively deposited initially. The substrate according to (1) or (2), wherein the substrate surface region portions are further connected by a deposited metal deposition portion.
（４）前記選択的に金属が堆積する基材表面領域部分の組成が、単結晶シリコン、ポリシリコン、化合物半導体、金属、金属のケイ化物のいずれかである前記（１）〜（３）のいずれかに記載の基板。
（５）前記選択的に金属が堆積しない基材表面領域部分の組成が、ケイ素の酸化物、窒化物、炭化物、ホウ化物のいずれかである前記（１）〜（４）のいずれかに記載の基板。
（６）前記初期に選択的に堆積する金属、及びさらに延伸させるために堆積する金属が、Ｃｏ、Ｎｉ、Ｃｕ、またはそれらの合金、もしくはそれぞれを順に重ねて堆積したものである前記（１）〜（５）のいずれかに記載の基板。(4) The composition of the substrate surface region where the metal is selectively deposited is any one of single crystal silicon, polysilicon, compound semiconductor, metal, and metal silicide. The board | substrate in any one.
(5) The composition according to any one of (1) to (4), wherein the composition of the substrate surface region portion where the metal is not selectively deposited is any one of silicon oxide, nitride, carbide, and boride. Board.
(6) The metal that is selectively deposited in the initial stage and the metal that is deposited for further stretching is Co, Ni, Cu, or an alloy thereof, or one obtained by sequentially stacking each of them. The substrate according to any one of to (5).
（７）前記選択的に堆積する金属が無電解めっきにより堆積されてなる前記（１）〜（６）のいずれかに記載の基板。
（８）前記無電解めっきが、フッ素化合物、還元剤、及び金属塩を含有し、ｐＨ調整剤としてアンモニアを用い、ｐＨ６以上としてなる無電解めっき液を用いてなる前記（７）記載の基板。(7) The substrate according to any one of (1) to (6), wherein the selectively deposited metal is deposited by electroless plating.
(8) The substrate according to (7), wherein the electroless plating contains a fluorine compound, a reducing agent, and a metal salt, uses ammonia as a pH adjuster, and uses an electroless plating solution having a pH of 6 or more.
（９）前記無電解めっき液が、さらにポリカルボン酸またはその塩を含有させてなる前記（８）記載の基板。
（１０）前記ポリカルボン酸またはその塩が、クエン酸またはその塩である前記（９）記載の基板。(9) The substrate according to (8), wherein the electroless plating solution further contains polycarboxylic acid or a salt thereof.
(10) The substrate according to (9), wherein the polycarboxylic acid or a salt thereof is citric acid or a salt thereof.
（１１）前記フッ素化合物が、フッ化アンモニウムである前記（８）〜（１０）のいずれかに記載の基板。
（１２）前記無電解めっき液が、アルカリ金属を含有しない前記（８）〜（１１）のいずれかに記載の基板。(11) The substrate according to any one of (8) to (10), wherein the fluorine compound is ammonium fluoride.
(12) The substrate according to any one of (8) to (11), wherein the electroless plating solution does not contain an alkali metal.
（１３）前記無電解めっき液の金属塩の金属がＮｉである前記（８）〜（１２）のいずれかに記載の基板。
（１４）前記無電解めっき液で金属が堆積する基材表面領域部分が単結晶シリコンまたはポリシリコンである前記（８）〜（１３）のいずれかに記載の基板。
（１５）前記無電解めっき液で堆積させた金属の厚みが２００ｎｍ以下である前記（８）〜（１４）のいずれかに記載の基板。(13) The substrate according to any one of (8) to (12), wherein the metal of the metal salt of the electroless plating solution is Ni.
(14) The substrate according to any one of (8) to (13), wherein a base material surface region where metal is deposited by the electroless plating solution is single crystal silicon or polysilicon.
(15) The substrate according to any one of (8) to (14), wherein the metal deposited with the electroless plating solution has a thickness of 200 nm or less.
（１６）前記基板が、特定の一つまたは複数の組成の領域部分の表面に選択的に、金属を堆積する前に、アルカリ性水溶液で前処理されてなる前記（１）〜（１５）のいずれかに記載の基板。 (16) Any of the above (1) to (15), wherein the substrate is pretreated with an alkaline aqueous solution before selectively depositing a metal on the surface of a region portion having a specific composition or a plurality of specific components. The substrate according to crab.
（１７）前記（２）〜（１６）のいずれかに記載の基板を用い、選択的に堆積させた金属の一部が未反応の金属として残してなる部分を電極として備えることを特徴とする半導体素子。 (17) The substrate according to any one of (2) to (16) is provided, and a portion formed by leaving a part of the selectively deposited metal as an unreacted metal is provided as an electrode. Semiconductor element.
本発明によれば、表面に周囲とは異なる組成の領域部分を有する基材表面の、特定の一つまたは複数の該組成の領域部分の表面に選択的に、金属を堆積し、熱処理を施して、金属が堆積した領域部分の一部で当該金属と、金属が堆積した基材表面領域部分を構成する元素との化合物を形成し、堆積させた該金属の一部を未反応の金属として残した基板は、トランジスタ等の半導体素子に用いた場合、堆積させた該金属の一部を未反応の金属として残した部分を電極とすることにより、ゲート電極およびソース・ドレイン領域の抵抗値を下げることができ、電流効率を上げることが可能な基板となる。 According to the present invention, a metal is selectively deposited on the surface of a specific one or a plurality of region portions having the composition different from the surrounding region on the surface, and heat treatment is performed. And forming a compound of the metal and an element constituting the base material surface region where the metal is deposited in a part of the region where the metal is deposited, and using the deposited part of the metal as an unreacted metal When the remaining substrate is used for a semiconductor element such as a transistor, the portion where the deposited metal is left as an unreacted metal is used as an electrode, so that the resistance value of the gate electrode and the source / drain region is reduced. The substrate can be lowered and current efficiency can be increased.
特にトランジスタの電極作製において、シリコンとシリコンオキサイドが共存する状態で、特定の無電解ニッケルめっき液を用いると、シリコン上に選択的にニッケル薄膜を形成できる。また、めっき膜と被めっき物の界面も平坦であり、密着性も良好である。
無電解めっきにより、シリコンとシリコンオキサイドが共存する状態で、シリコン上に選択的にニッケル薄膜形成できることにより、従来の選択性のないスパッタ法と比較して成膜後の不要部の剥離工程を必要としないことから、プロセス上のメリットが大きい。
また、ソース・ドレイン接合深さと未反応の金属層の厚さを調整することにより、抵抗値を調整することができ、未反応の金属層の厚さを厚くすることにより低抵抗化できる。In particular, when producing a transistor electrode, if a specific electroless nickel plating solution is used in a state where silicon and silicon oxide coexist, a nickel thin film can be selectively formed on the silicon. In addition, the interface between the plating film and the object to be plated is flat and has good adhesion.
Electroless plating can selectively form a nickel thin film on silicon in the state where silicon and silicon oxide coexist, thus requiring an unnecessary part peeling process after film formation compared to the conventional non-selective sputtering method. Therefore, the process advantage is great.
Further, the resistance value can be adjusted by adjusting the source / drain junction depth and the thickness of the unreacted metal layer, and the resistance can be lowered by increasing the thickness of the unreacted metal layer.
本発明の、表面に周囲とは異なる組成の領域部分を有する基材表面の、特定の一つまたは複数の組成の領域部分の表面に選択的に、金属を堆積してなる基板を図面を用いて模式的に説明する。
図１（ａ）は、表面に異なる組成１〜４の領域部分を有する基材の一例であり、図１（ｂ）は、特定の一つまたは複数の組成として組成２、３にのみ選択的に金属を堆積させた基板の一例である。A substrate obtained by selectively depositing a metal on the surface of a region portion having a specific composition or a plurality of components on the surface of a substrate having a region portion having a composition different from the surroundings on the surface of the present invention is described with reference to the drawings. This will be described schematically.
FIG. 1 (a) is an example of a substrate having a region portion of different compositions 1 to 4 on the surface, and FIG. 1 (b) is selective only to the compositions 2 and 3 as one or more specific compositions. 2 is an example of a substrate on which a metal is deposited.
図２及び図３に、この基板に熱処理を施した場合の一例を示す。前記金属が堆積した基板を熱処理することにより、金属との接触面から、金属と金属が堆積した基材表面領域部分を構成する元素との化合物が形成される。この際、接触面から離れた側の金属は未反応で残っても良く、また、金属と金属が堆積した基材表面領域部分を構成する元素との化合物が形成されない金属領域部分を有していても良い。 FIG. 2 and FIG. 3 show an example when the substrate is subjected to heat treatment. By heat-treating the substrate on which the metal is deposited, a compound of the metal and an element constituting the substrate surface region portion on which the metal is deposited is formed from the contact surface with the metal. At this time, the metal on the side away from the contact surface may remain unreacted, and has a metal region portion where a compound of the metal and the element constituting the substrate surface region portion on which the metal is deposited is not formed. May be.
図２においては、組成２上に堆積した金属が全てが、組成２の領域部分を構成する元素との化合物を形成してなる。また、組成２において、金属と、組成２を構成する元素との化合物を形成してなる領域が一部であり、接触面から離れた側の金属が未反応で残っている例を図３に示す。図２、図３においては、組成３上の金属は、組成３を構成する元素との化合物を形成していないが、金属が堆積した全ての領域部分で、全面又は一部が金属化合物を形成していても良い。未反応の金属を選択的に残すことにより、この領域部分の抵抗値を下げることができるので、未反応の金属を残すことが好ましい。 In FIG. 2, all the metal deposited on the composition 2 forms a compound with an element constituting the region portion of the composition 2. FIG. 3 shows an example in which, in composition 2, a region formed by forming a compound of a metal and an element constituting composition 2 is a part, and the metal on the side away from the contact surface remains unreacted. Show. 2 and 3, the metal on the composition 3 does not form a compound with the elements constituting the composition 3, but the entire surface or a part of the metal deposits forms a metal compound in all regions where the metal is deposited. You may do it. By selectively leaving unreacted metal, the resistance value in this region can be lowered, so it is preferable to leave unreacted metal.
図４は初期に選択的に堆積した金属の上にさらに金属を堆積させ、金属堆積部を延長させ、互いに離れた初期に堆積した金属領域部分どうしを、さらに堆積した金属堆積部で接続させた場合の一例を示したものである。
図４においては、熱処理を施す前にさらに金属を堆積しているが、さらに金属を堆積させるのは、熱処理を施した後でもよい。FIG. 4 shows that metal is further deposited on the metal selectively deposited initially, the metal deposition portion is extended, and portions of the initially deposited metal regions that are separated from each other are connected by the further deposited metal deposition portion. An example of the case is shown.
In FIG. 4, the metal is further deposited before the heat treatment, but the metal may be further deposited after the heat treatment.
本発明における表面に異なる組成の領域部分を有する基材としては、例えば、トランジスタ（ＭＯＳ型トランジスタ）に用いる基材が挙げられ、表面に単結晶シリコン、ポリシリコン、化合物半導体、金属、金属のケイ化物、ケイ素の酸化物、窒化物、炭化物、ホウ化物等の組成の領域部分を有する基材が挙げられる。このうち金属が選択的に堆積する組成としては、シリコン、ポリシリコン、化合物半導体、金属、金属のケイ化物等であり、金属が堆積しない組成としてはケイ素の酸化物、窒化物、炭化物、ホウ化物であることが好ましい。上記化合物半導体としては、ＩｎＰ、ＧａＡｓ、ＧａＰ、ＧａＮ、ＩｎＡｓ等が挙げられ、金属としてはニッケル、コバルト等が挙げられ、金属のケイ化物としては、ニッケルシリサイド、コバルトシリサイド等が挙げられる。
例えば、表面にシリコンとシリコンオキサイドの領域部分を有する基材は、シリコンウェハーを酸化して表面にシリコンオキサイド膜を形成し、エッチング等によりシリコンオキサイド膜の必要部を残すことにより得ることができる。Examples of the base material having a region having a different composition on the surface in the present invention include base materials used for transistors (MOS type transistors), and the surface includes single crystal silicon, polysilicon, compound semiconductor, metal, and metal silicon. And a substrate having a region portion having a composition such as a nitride, a silicon oxide, a nitride, a carbide, or a boride. Among these, the composition in which metal is selectively deposited is silicon, polysilicon, compound semiconductor, metal, metal silicide, etc., and the composition in which metal is not deposited is silicon oxide, nitride, carbide, boride. It is preferable that Examples of the compound semiconductor include InP, GaAs, GaP, GaN, and InAs. Examples of the metal include nickel and cobalt. Examples of the metal silicide include nickel silicide and cobalt silicide.
For example, a substrate having a silicon and silicon oxide region portion on the surface can be obtained by oxidizing a silicon wafer to form a silicon oxide film on the surface and leaving a necessary portion of the silicon oxide film by etching or the like.
特定の一つまたは複数の組成の領域部分に選択的に金属を堆積させる方法としては、例えば、無電解めっき方法、レジストでパターニングし保護した後スパッタリングしたり（リフトオフ）、スパッタリングした後レジストでパターニングし保護してエッチングして不要部分を削除したりする方法等が挙げられる。
これらの方法の中で、無電解めっきにより選択的に金属を堆積させることが煩雑な工程を含まないので好ましい。例えば、少なくともシリコンとシリコンオキサイドの領域部分を有する基材に、特定の無電解めっき液を用いてめっきを行うことにより、シリコンオキサイドの領域部分には金属を堆積させずに、シリコンの領域部分に選択的に金属を堆積させることができる。Examples of a method of selectively depositing metal on a region having a specific composition or a plurality of components include, for example, an electroless plating method, sputtering after patterning and protecting with a resist (lift-off), and patterning with resist after sputtering. For example, there is a method of removing unnecessary portions by protecting and etching.
Among these methods, it is preferable to selectively deposit metal by electroless plating because it does not involve complicated steps. For example, by performing plating using a specific electroless plating solution on a substrate having at least a silicon and silicon oxide region portion, a metal is not deposited on the silicon oxide region portion, but the silicon region portion is deposited. A metal can be selectively deposited.
上記表面に異なる組成の領域部分を有する基材の特定の一つまたは複数の組成の領域部分の表面に、無電解めっき方法で金属を堆積させる際の無電解めっき液としては、例えば、フッ素化合物、還元剤、及び金属塩を含有し、ｐＨ調整剤としてアンモニアを用い、ｐＨ６以上とした水溶液が好ましい。 As an electroless plating solution for depositing a metal by an electroless plating method on the surface of one or more specific region regions of a substrate having a region portion having a different composition on the surface, for example, a fluorine compound An aqueous solution containing a reducing agent and a metal salt, using ammonia as a pH adjusting agent, and having a pH of 6 or more is preferable.
フッ素化合物としては、フッ化アンモニウム、フッ化カリウム、フッ化ナトリウム等を用いることができるが、フッ化アンモニウムが好ましい。
還元剤としては、ホスフィン酸を用いることにより、Ｎａ、Ｋを含まない液とすることができるので好ましい。また、ジメチルアミンボラン（ＤＭＡＢ）も好ましく用いることができる。もちろんホスフィン酸ナトリウムなどの塩も用いることができる。As the fluorine compound, ammonium fluoride, potassium fluoride, sodium fluoride and the like can be used, but ammonium fluoride is preferable.
As the reducing agent, it is preferable to use phosphinic acid because a liquid containing no Na or K can be obtained. Further, dimethylamine borane (DMAB) can also be preferably used. Of course, a salt such as sodium phosphinate can also be used.
金属塩としては、コバルト、銅、ニッケル、それらの合金等の塩が挙げられ、ニッケル塩が好ましい。ニッケル塩としては、一般的な無電解ニッケルめっき液に使用される水溶性ニッケル塩を使用することができる。例えば硫酸ニッケル、塩化ニッケル、次亜リン酸ニッケル、などが挙げられる。
Ｓｉ上ではめっき時に交換反応が生じるとＳｉ基板が５０ｎｍ程度侵食され、ボイドが発生する。このめっき時に侵食におけるボイド発生がなく界面を平坦とするためにはアンモニアによりｐＨ６以上に調整すること、及びフッ素化合物の共存が必要となる。ｐＨは６〜１０が好ましく、７〜９がより好ましい。これによりＳｉの侵食が少なく、置換・還元めっきが可能となる。Examples of the metal salt include salts of cobalt, copper, nickel, alloys thereof, and the like, and nickel salts are preferable. As the nickel salt, a water-soluble nickel salt used in a general electroless nickel plating solution can be used. Examples thereof include nickel sulfate, nickel chloride, nickel hypophosphite, and the like.
On Si, when an exchange reaction occurs during plating, the Si substrate is eroded by about 50 nm and voids are generated. In order to eliminate the generation of voids due to erosion during the plating and to make the interface flat, it is necessary to adjust the pH to 6 or higher with ammonia and the coexistence of a fluorine compound. The pH is preferably 6-10, more preferably 7-9. Thereby, there is little erosion of Si and substitution / reduction plating becomes possible.
本発明の無電解めっき液には、必要に応じてポリカルボン酸またはその塩を加えることができる。ポリカルボン酸またはその塩としては、クエン酸またはその塩が好ましい。クエン酸等の分子内に複数個のカルボキシル基を有するポリカルボン酸を加えることによりシリコン面が平滑となる。ポリカルボン酸は、シリコンに吸着するためシリコンとニッケル等の金属の置換反応を温和にするために、局部的に置換反応が進まず、結果的に平坦なシリコンとめっき膜の界面にすることができると考えられる。ただし、添加量が多すぎると速度が速く安定性が不安となる。 A polycarboxylic acid or a salt thereof can be added to the electroless plating solution of the present invention as necessary. As the polycarboxylic acid or a salt thereof, citric acid or a salt thereof is preferable. By adding polycarboxylic acid having a plurality of carboxyl groups in the molecule such as citric acid, the silicon surface becomes smooth. Since polycarboxylic acid is adsorbed to silicon, the substitution reaction between silicon and metal such as nickel is moderated, so that the substitution reaction does not proceed locally, resulting in a flat silicon-plated film interface. It is considered possible. However, if the amount added is too large, the speed is high and the stability becomes uneasy.
その他必要に応じて酒石酸、グリシン、マロン酸等の安定剤、反応促進剤、界面活性剤などを含有することができるが、ナトリウムやカリウムなどのアルカリ金属を含んでいないことが望ましい。半導体デバイスではナトリウムやカリウムなどのアルカリ金属を含むものは汚染の原因となり、リーク電流の発生や金属汚染による酸化膜破壊が生じるので好ましくない。 In addition, stabilizers such as tartaric acid, glycine, and malonic acid, reaction accelerators, surfactants, and the like can be contained as necessary, but it is desirable that alkali metals such as sodium and potassium are not included. Of the semiconductor devices, those containing alkali metals such as sodium and potassium are not preferable because they cause contamination and cause leakage current and oxide film destruction due to metal contamination.
これらのめっき浴の成分は、通常用いられている濃度の範囲で用いることができる。例えば、ホスフィン酸は０．０１〜１ｍｏｌ／Ｌ、好ましくは０．０５〜０．５ｍｏｌ／Ｌ、フッ素化合物は０．１〜５ｍｏｌ／Ｌ、好ましくは０．５〜２ｍｏｌ／Ｌ、金属塩は０．０１〜０．５ｍｏｌ／Ｌ、好ましくは０．０５〜０．２ｍｏｌ／Ｌ、ポリカルボン酸は０．０２〜１ｍｏｌ／Ｌ、好ましくは０．１〜０．４ｍｏｌ／Ｌ含有することが好ましい。 The components of these plating baths can be used in a range of concentrations usually used. For example, phosphinic acid is 0.01 to 1 mol / L, preferably 0.05 to 0.5 mol / L, fluorine compound is 0.1 to 5 mol / L, preferably 0.5 to 2 mol / L, and metal salt is 0. 0.01 to 0.5 mol / L, preferably 0.05 to 0.2 mol / L, and polycarboxylic acid is contained in an amount of 0.02 to 1 mol / L, preferably 0.1 to 0.4 mol / L.
めっき方法としては、前記基材を、前処理として、ｐＨ１２以上のアルカリ水溶液により脱脂処理を行った後、上記無電解めっき液を用いて無電解めっきを行う。このときめっき液の温度は５０〜９０℃が好ましく、６０〜８０℃がより好ましい。また、めっき時間は０.５〜５分、好ましくは１〜３分である。
本発明のめっき方法により、シリコン上に２００ｎｍ以下の薄膜を形成することができる。さらには１００ｎｍ以下の薄膜とすることもでき、微細化が可能である。As a plating method, as a pretreatment, the substrate is degreased with an alkaline aqueous solution having a pH of 12 or more, and then electroless plating is performed using the electroless plating solution. At this time, the temperature of the plating solution is preferably 50 to 90 ° C, more preferably 60 to 80 ° C. The plating time is 0.5 to 5 minutes, preferably 1 to 3 minutes.
By the plating method of the present invention, a thin film of 200 nm or less can be formed on silicon. Further, it can be a thin film of 100 nm or less, and can be miniaturized.
前処理としては、アルカリ水溶液により脱脂処理を行うことが好ましい。フッ酸系やマンガン系のエッチャントではなくアルカリ水溶液を用いることにより、酸化膜の剥離や損傷を与えることがないため良好なシリコンオキサイドとシリコンの選択性を発現することが可能となる。従来のフッ素系やマンガン系のエッチャントを用いると、選択的めっき薄膜を形成することが難しい。脱脂処理に用いるアルカリ水溶液としては、リン酸系のアルカリ脱脂剤が好ましい。半導体デバイスではナトリウムやカリウムなどのアルカリ金属を含むものは汚染の原因となり、リーク電流の発生や金属汚染による酸化膜破壊が生じるのでこれらのアルカリ金属を含むアルカリを用いるのは好ましくない。リン酸系のアルカリ脱脂剤としては、例えば建浴でｐＨ１２．０〜１２．５である日鉱金属株式会社製クリーナーＳＴを好ましく用いることができる。
また、基材を予めアルカリ水溶液で前処理することにより、選択的にめっき薄膜を形成することができると同時に、めっき膜の均一性が良好となる。As pretreatment, it is preferable to perform a degreasing treatment with an alkaline aqueous solution. By using an alkaline aqueous solution instead of a hydrofluoric acid-based or manganese-based etchant, the oxide film is not peeled off or damaged, so that it is possible to express good selectivity between silicon oxide and silicon. When a conventional fluorine-based or manganese-based etchant is used, it is difficult to form a selective plating thin film. As the alkaline aqueous solution used for the degreasing treatment, a phosphoric acid alkaline degreasing agent is preferable. In semiconductor devices, those containing alkali metals such as sodium and potassium cause contamination, and the generation of leakage current and destruction of the oxide film due to metal contamination occur. Therefore, it is not preferable to use alkalis containing these alkali metals. As the phosphoric acid-based alkaline degreasing agent, for example, a cleaner ST manufactured by Nikko Metal Co., Ltd. having a pH of 12.0 to 12.5 in a bath can be preferably used.
Moreover, by pre-treating the base material in advance with an alkaline aqueous solution, a plated thin film can be selectively formed, and at the same time, the uniformity of the plated film is improved.
無電解めっきによる選択性の発現は、従来の選択性がないスパッタ法と比較して成膜後の不要部の剥離工程を必要としないことから、プロセス上のメリットは大きい。 The development of selectivity by electroless plating has a great process advantage because it does not require a separation step of unnecessary portions after film formation as compared with a sputtering method without conventional selectivity.
選択的に金属を堆積させた後に行う、熱処理としては、金属が堆積した領域部分の一部又は全てで当該金属と、金属が堆積した基材表面領域部分を構成する元素との化合物を形成する温度でよく、例えば、不活性ガス雰囲気中、１０００℃で数秒から数十分間行えばよく、反応の程度により、より低温の３００〜８００℃で行ってもよい。
堆積した金属との化合物を形成する基材表面領域部分の組成としては、単結晶シリコン、ポリシリコン、金属、金属のケイ化物等が挙げられる。また、基材表面領域部分の組成が、化合物半導体の場合は、金属との化合物を形成しにくく、金属は未反応で残る。堆積させた金属の一部を未反応の金属として残した部分をトランジスタのゲート電極として用いることにより、ゲート電極の抵抗値を下げることができる。従って、目的によって残す金属の量を調整することにより、ゲート電極の抵抗値を調整することができる。As the heat treatment performed after the metal is selectively deposited, a compound of the metal and an element constituting the substrate surface region portion where the metal is deposited is formed in a part or all of the region where the metal is deposited. The temperature may be sufficient. For example, the reaction may be performed at 1000 ° C. for several seconds to several tens of minutes in an inert gas atmosphere.
Examples of the composition of the substrate surface region portion that forms a compound with the deposited metal include single crystal silicon, polysilicon, metal, metal silicide, and the like. Moreover, when the composition of the substrate surface region is a compound semiconductor, it is difficult to form a compound with a metal, and the metal remains unreacted. By using a portion where a part of the deposited metal is left as an unreacted metal as the gate electrode of the transistor, the resistance value of the gate electrode can be lowered. Therefore, the resistance value of the gate electrode can be adjusted by adjusting the amount of metal left depending on the purpose.
ソース電極やドレイン電極がゲート電極と同じ素材を使用している時は、同時に選択的に金属を堆積させ、電極を形成しても構わない。熱処理をして、金属が堆積した領域部分の一部で該金属と、金属が堆積した基材表面領域部分を構成する元素との化合物を形成し金属の一部を未反応の金属として残すことにより、ソース・ドレイン電極の抵抗値を下げることができる。目的によって前記金属と金属が堆積した基材表面領域部分を構成する元素との化合物を形成した部分（ソース・ドレイン接合深さ）と未反応の金属層の厚さを調整することにより、抵抗値を調整することができ、未反応の金属層の厚さを厚くすることにより低抵抗化できる。 When the same material as the gate electrode is used for the source electrode and the drain electrode, the electrode may be formed by selectively depositing metal at the same time. Heat treatment is performed to form a compound of the metal and an element constituting the base material surface region where the metal is deposited in a part of the region where the metal is deposited, and leave a part of the metal as an unreacted metal. Thus, the resistance value of the source / drain electrodes can be lowered. The resistance value is adjusted by adjusting the thickness of the unreacted metal layer and the portion (source / drain junction depth) where the compound of the metal and the element constituting the substrate surface region where the metal is deposited is formed according to the purpose. The resistance can be reduced by increasing the thickness of the unreacted metal layer.
前記初期に金属を堆積した基板表面領域部分に、更に金属を堆積させ、金属堆積領域部分を延伸させ、互いに離れた初期に金属を堆積した基板の表面どうしを、更に堆積した金属堆積部で接続させる方法としては、無電解めっき方法が挙げられる。無電解めっきの時間を長くとり、側方への膜成長を利用することにより、互いに離れた初期に金属を堆積した基板の表面どうしを接続することができる。無電解めっき方法により更に堆積する金属としては、初期に選択的に堆積する金属と同様な金属、即ち、コバルト、ニッケル、銅、またはそれらの合金、もしくはそれぞれを順に重ねて堆積したものが挙げられる。 The metal is further deposited on the substrate surface region where the metal is initially deposited, the metal deposition region is extended, and the surfaces of the substrates on which the metal is initially deposited are separated from each other by the further deposited metal deposition portion. Examples of the method include electroless plating. By taking a long electroless plating time and utilizing lateral film growth, it is possible to connect the surfaces of the substrates on which metal is deposited at an early stage apart from each other. Examples of the metal that is further deposited by the electroless plating method include the same metals as those selectively deposited at the beginning, that is, cobalt, nickel, copper, or alloys thereof, or those obtained by sequentially stacking each other. .
以下、実施例に基づき本発明を詳述する。
実施例１
不純物濃度調整等をしたシリコンウェハー上に１０００℃で１時間乾燥酸素により酸化してシリコンオキサイド（ＳｉＯ2）膜を形成し、フォトエッチングにより必要部のみを残し、それ以外は除去した。シリコンとシリコンオキサイドの組成の領域部分を有するシリコンウェハーを、リン酸系のアルカリ脱脂剤（日鉱金属株式会社製クリーナーＳＴ）に６０℃で３分間浸漬し、下記組成の無電解ニッケルめっきを用いて無電解めっきを行い、シリコン上にのみ選択的にニッケル薄膜を形成した。選択的にニッケル薄膜を形成した基板を図５に示す。無電解めっきによるニッケル薄膜厚は８０ｎｍであり、めっき界面の侵食度も良好であった。次に４００℃で３０分間不活性ガス雰囲気中で熱処理を施してニッケルとシリコンの化合物を形成した。熱処理後、４０ｎｍがシリサイド化していた。
めっき液組成
硫酸ニッケル ０．０８ｍｏｌ／Ｌ
クエン酸 ０．１ｍｏｌ／Ｌ
フッ化アンモニウム ０．２５ｍｏｌ／Ｌ
ホスフィン酸 ０．２ｍｏｌ／Ｌ
ｐＨ ８．０
ｐＨ調整剤 ＮＨ4ＯＨ
浴温度 ７０℃
浸漬時間 ３分間
界面の侵食度 良好Hereinafter, the present invention will be described in detail based on examples.
Example 1
A silicon oxide (SiO 2 ) film was formed by oxidation with dry oxygen at 1000 ° C. for 1 hour on a silicon wafer adjusted for impurity concentration, etc., and only the necessary portions were left by photoetching, and the others were removed. A silicon wafer having a region portion having a composition of silicon and silicon oxide is immersed in a phosphoric acid alkaline degreasing agent (cleaner ST manufactured by Nikko Metal Co., Ltd.) at 60 ° C. for 3 minutes, and electroless nickel plating having the following composition is used. Electroless plating was performed to selectively form a nickel thin film only on silicon. A substrate on which a nickel thin film is selectively formed is shown in FIG. The nickel thin film thickness by electroless plating was 80 nm, and the erosion degree of the plating interface was also good. Next, heat treatment was performed in an inert gas atmosphere at 400 ° C. for 30 minutes to form a nickel and silicon compound. After the heat treatment, 40 nm was silicided.
Plating solution composition Nickel sulfate 0.08mol / L
Citric acid 0.1 mol / L
Ammonium fluoride 0.25 mol / L
Phosphinic acid 0.2mol / L
pH 8.0
pH adjuster NH 4 OH
Bath temperature 70 ° C
Immersion time 3 minutes Interface erosion is good
実施例２
めっき時間を１分間とした以外は、実施例１と同様の操作を行った。実施例１と同様にシリコン上にのみ選択的にニッケル薄膜が形成され、熱処理によりニッケルとシリコンの化合物が形成された。無電解めっきによるニッケル薄膜は、６０ｎｍであり、めっき界面の侵食度も良好であった。Example 2
The same operation as in Example 1 was performed except that the plating time was 1 minute. Similar to Example 1, a nickel thin film was selectively formed only on silicon, and a nickel and silicon compound was formed by heat treatment. The nickel thin film by electroless plating was 60 nm, and the erosion degree of the plating interface was also good.
Claims (17)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2008127836 | 2008-05-15 | ||
| JP2008127836 | 2008-05-15 | ||
| PCT/JP2009/058811 WO2009139366A1 (en) | 2008-05-15 | 2009-05-12 | Substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPWO2009139366A1 true JPWO2009139366A1 (en) | 2011-09-22 |
Family
ID=41318733
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2010511976A Withdrawn JPWO2009139366A1 (en) | 2008-05-15 | 2009-05-12 | substrate |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JPWO2009139366A1 (en) |
| TW (1) | TW201001648A (en) |
| WO (1) | WO2009139366A1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR3002545B1 (en) * | 2013-02-22 | 2016-01-08 | Alchimer | PROCESS FOR FORMING A METAL SILICIDE USING A SOLUTION CONTAINING GOLD IONS AND FLUOR IONS |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5124176A (en) * | 1974-08-21 | 1976-02-26 | New Nippon Electric Co | Handotaisochino denkyokukeiseiho |
| JPH04180573A (en) * | 1990-11-14 | 1992-06-26 | Nippon Hyomen Kagaku Kk | Method for applying ni plating to resin molded type magnet and ni plating bath |
| JP2003073843A (en) * | 2001-08-28 | 2003-03-12 | Hiroshima Pref Gov | Electroless nickel plating method for magnesium alloy material |
| JP4559818B2 (en) * | 2004-04-30 | 2010-10-13 | アルプス電気株式会社 | Electroless plating method for silicon substrate and metal layer forming method on silicon substrate |
| SE0403042D0 (en) * | 2004-12-14 | 2004-12-14 | Polymer Kompositer I Goeteborg | Improved stabilization and performance of autocatalytic electroless process |
-
2009
- 2009-05-12 WO PCT/JP2009/058811 patent/WO2009139366A1/en active Application Filing
- 2009-05-12 JP JP2010511976A patent/JPWO2009139366A1/en not_active Withdrawn
- 2009-05-13 TW TW98115780A patent/TW201001648A/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| TW201001648A (en) | 2010-01-01 |
| WO2009139366A1 (en) | 2009-11-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3600541B2 (en) | Method of forming ohmic contacts for thin film transistors | |
| JP5669780B2 (en) | Manufacturing method of semiconductor device | |
| KR100966384B1 (en) | Nickel silicide method and structure | |
| JP3394927B2 (en) | Method for forming metal silicide layer | |
| WO1999010916A2 (en) | Copper electroless deposition on a titanium-containing surface | |
| JPH07161659A (en) | Semiconductor device and its manufacture | |
| US20070087573A1 (en) | Pre-treatment method for physical vapor deposition of metal layer and method of forming metal silicide layer | |
| JP6115684B2 (en) | Semiconductor device and method for manufacturing semiconductor device | |
| JP3888330B2 (en) | Method for manufacturing silicon carbide semiconductor device | |
| JP2012222074A (en) | Method for forming electrodes on silicon carbide semiconductor device | |
| WO2009139366A1 (en) | Substrate | |
| JP2001015735A (en) | Semiconductor device and manufacture thereof | |
| JP2010171327A (en) | Semiconductor device manufacturing method | |
| CN105529253A (en) | Semiconductor device formation method | |
| JP5399308B2 (en) | Pretreatment liquid for electroless plating on semiconductor wafer, electroless plating method, and semiconductor device | |
| WO2010113715A1 (en) | Method of producing semiconductor device, and semiconductor device | |
| JP2002217129A (en) | Method for manufacturing silicon carbide semiconductor device | |
| JP7464152B2 (en) | Semiconductor device and its manufacturing method | |
| JP3258934B2 (en) | Improved method for producing self-aligned silicides | |
| KR100577020B1 (en) | Forming method of semiconductor device for improvement of removing residu and thermal stability | |
| JP2966418B2 (en) | Method of forming wiring contact | |
| JP2000031093A (en) | Fabrication of semiconductor device | |
| KR100528796B1 (en) | Method of manufacturing inductor in a semiconductor device | |
| KR100541704B1 (en) | Method of manufacture semiconductor device having structure of metal salicide | |
| JP2010192735A (en) | Semiconductor element and manufacturing method therefor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20120807 |