JPWO2009096413A1 - Voltage-controlled oscillator, phase-locked loop circuit, clock / data recovery circuit, and control method - Google Patents

Abstract

A voltage controlled oscillator capable of suppressing fluctuations in VCO gain at the time of band switching is provided. A voltage controlled oscillator (VCO) according to the present invention is a voltage controlled oscillator having first frequency variable means to which a loop control voltage is applied and second frequency variable means, and the second frequency variable means. And a reference potential generating means for outputting a voltage dependent on the frequency band switching signal, and the output voltage of the reference potential generating means is applied by the loop control voltage of the first frequency variable means. It is characterized by being applied to a terminal different from the terminal to be applied.

Description

  The present invention relates to a voltage controlled oscillator (VCO) used in a microwave / millimeter wave band, and more particularly to a voltage controlled oscillator operating in a multiband.

  First, a voltage controlled oscillator (VCO) related to the present invention will be described with reference to FIG. FIG. 1 is a circuit diagram showing an example of a differential VCO operating in multiband.

  The VCO shown in FIG. 1 includes a power supply terminal 1, output terminals 2a and 2b, a loop control terminal 3, frequency band switching terminals 41, 42 and 43, cross-coupled NMOS transistors 5a and 5b, cross-coupled PMOS transistors 6a and 6b, an inductor 7 , Variable capacitance elements 8 a and 8 b, switching capacitance units 13 a and 13 b, and output buffer 16.

  The switching capacitors 13a and 13b are configured to include switching capacitors 111a, 112a, 113a, 111b, 112b, and 113b, and switch transistors 121a, 122a, 123a, 121b, 122b, and 123b.

  The output buffer 16 includes output transistors 14a and 14b and output resistors 15a and 15b.

  In addition, the part comprised by the variable capacitance elements 8a and 8b will be referred to as variable capacitance units 10a and 10b.

The capacitance values C ₁ , C ₂ , and C ₃ of the switching capacitors 111a, 112a, 113a, 111b, 112b, and 113b are usually set to different values. The frequency band switching signals V _SW1 , V _SW2 , and V _SW3 input to the frequency band switching terminals 41, 42, and 43 are set to binary values of High and Low, and High = VDD (power supply voltage) and Low = 0. Often done. In this example, the case of 3 bits is shown, but the number of bits is arbitrarily set as necessary.

  Next, the operation of the VCO shown in FIG. 1 will be described.

  The cross-coupled portion formed by the cross-coupled NMOS transistors 5a and 5b and the cross-coupled portion formed by the cross-coupled PMOS transistors 6a and 6b generate a negative resistance. This negative resistance compensates for the loss generated in other parts of the circuit with the oscillation frequency, thereby realizing a sustained oscillation operation.

The oscillation frequency can be approximately expressed by the following (Equation 1) as a function of the control voltage _vCNT .

The frequency f (v _CNT0 ) when the loop control voltage v _CNT is the center voltage v _CNT0 will be referred to as the center frequency. Here, C _f represents the contribution of parasitic capacitance components in portions other than the variable capacitance portions 10a and 10b, such as the cross-coupled transistors 5a, 5b, 6a, and 6b. C _SW represents the capacity of the switching capacitor units 13a and 13b, and can be set to eight values from 0 to (C ₁ + C ₂ + C ₃ ) by input signals to the frequency band switching terminals 41, 42, and 43. It is. However, in order to simplify the description, the capacitances of the switch transistors 121a, 122a, 123a, 121b, 122b, and 123b are ignored. Due to this change in _CSW , the center frequency becomes discretely variable, and multiband operation is possible. At this time, the VCO gain can be expressed by the following (Equation 2).

  As a technical document filed prior to the present invention, a parallel circuit of a first variable capacitance element and a first switching capacitor section, and a series circuit of a second variable capacitor element and a second switching capacitor section are used. There is a document disclosing the configuration of a multiband VCO (see, for example, Patent Document 1).

In addition, a voltage regulator circuit that performs voltage conversion on the output signal of the charge pump circuit is inserted in the PLL loop, and the voltage conversion coefficient of this voltage regulator circuit is changed according to the VCO frequency band switching signal. Is disclosed (for example, see Patent Document 2).
JP 2007-267353 A JP 2005-31690 A

Note that the gain of the VCO shown in FIG. 1 is given by (Equation 2) described above. When the center frequency is changed by setting the input signal (frequency band switching signal) to the frequency band switching terminals 41, 42, and 43 to perform multi-banding, C _SW in the denominator [·] among the components of the VCO gain Only changes, the other elements remain unchanged.

Therefore, the VCO gain fluctuates as the center frequency changes (with band switching). When the C _SW is increased and the center frequency is decreased according to the above (Equation 1), the VCO gain is decreased according to the above (Equation 2).

Conversely, when C _SW is decreased and the center frequency is increased according to (Equation 2) described above, the VCO gain increases according to (Equation 1) described above. Therefore, the relationship between the center frequency and the VCO gain is as shown in FIG.

  The VCO gain is a parameter that has a strong influence on the loop characteristics of the PLL and CDR. If the VCO gain fluctuates depending on the center frequency, the PLL characteristic configured using this VCO fluctuates depending on the operating frequency, and the CDR characteristic fluctuates depending on the operating speed. . Therefore, it becomes difficult to realize a PLL that operates in a multiband and a CDR that operates at a multi-bit rate.

  Further, according to the technique disclosed in Patent Document 1, it is possible to suppress fluctuations in VCO gain associated with frequency band switching. However, the circuit configuration of the portion that strongly influences the high frequency characteristics, such as an increase in the number of variable capacitance elements and switching capacitance elements, becomes complicated, and there is a problem that the occupied area increases and the designability deteriorates.

  Further, according to the technique disclosed in Patent Document 2, it is possible to suppress the gain fluctuation of the entire loop due to frequency band switching. However, the method for compensating the gain variation of the VCO with the characteristics of the other blocks still has problems such as complicated loop design and reduced versatility of the VCO. In addition, a complicated circuit configuration is required to realize the voltage adjustment circuit, and there are problems in terms of power consumption and chip area.

  The present invention has been made in view of the above circumstances, and is a voltage-controlled oscillator, a phase-locked loop circuit, a clock / data recovery circuit, and a clock / data recovery circuit capable of suppressing fluctuations in VCO gain at the time of band switching, which are the problems described above. An object is to provide a control method.

  In order to achieve this object, the present invention has the following features.

<Voltage controlled oscillator>
The voltage controlled oscillator according to the present invention is:
A voltage controlled oscillator having first frequency variable means to which a loop control voltage is applied, and second frequency variable means,
Reference potential generating means for controlling the frequency band switching signal of the second frequency variable means and outputting a voltage depending on the frequency band switching signal,
The output voltage of the reference potential generating means is applied to a terminal different from the terminal to which the loop control voltage of the first frequency variable means is applied.

The voltage controlled oscillator according to the present invention is
A voltage controlled oscillator having first frequency variable means to which a loop control voltage is applied, and second frequency variable means,
Reference potential generating means for controlling the frequency band switching signal of the second frequency variable means and outputting a voltage depending on the frequency band switching signal,
The sum of the output voltage of the reference potential generating means and the loop control voltage is applied to the terminal of the first frequency variable means.

<Phase lock loop circuit>
The phase-locked loop circuit according to the present invention is
It has the voltage controlled oscillator described above.

<Clock and data recovery circuit>
In addition, the clock data recovery circuit according to the present invention includes:
It has the voltage controlled oscillator described above.

<Control method>
Further, the control method according to the present invention includes:
A control method of a voltage controlled oscillator having a first frequency variable means to which a loop control voltage is applied, a second frequency variable means, and a reference potential generating means,
The reference potential generating means outputting a voltage depending on a frequency band switching signal of the second frequency variable means;
Controlling the output voltage of the reference potential generating means to be applied to a terminal different from the terminal to which the loop control voltage of the first frequency variable means is applied.

Further, the control method according to the present invention includes:
A control method of a voltage controlled oscillator having a first frequency variable means to which a loop control voltage is applied, a second frequency variable means, and a reference potential generating means,
The reference potential generating means outputting a voltage depending on a frequency band switching signal of the second frequency variable means;
Controlling the sum of the output voltage of the reference potential generating means and the loop control voltage to be applied to the terminal of the first frequency variable means.

  According to the present invention, it is possible to suppress fluctuations in VCO gain at the time of band switching.

[First embodiment]
FIG. 3 is a configuration diagram of a voltage controlled oscillator (VCO) in the first embodiment.

  The VCO of this embodiment includes a power supply terminal 1, output terminals 2a and 2b, a loop control terminal 3, frequency band switching terminals 41, 42 and 43, cross-coupled NMOS transistors 5a and 5b, cross-coupled PMOS transistors 6a and 6b, an inductor 7 , Variable capacitors 8a and 8b, capacitors 9a and 9b, switching capacitors 13a and 13b, output buffer 16, reference potential generation circuit 22, and RF cutoff circuit 25.

  The switching capacitors 13a and 13b are configured to include switching capacitors 111a, 112a, 113a, 111b, 112b, and 113b, and switch transistors 121a, 122a, 123a, 121b, 122b, and 123b.

  The output buffer 16 includes output transistors 14a and 14b and output resistors 15a and 15b.

  In addition, the part comprised by the variable capacitive element 8a and the capacitive element 9a, the variable capacitive element 8b, and the capacitive element 9b will be called the variable capacitive parts 10a and 10b.

Reference potential generating circuit 22 includes a resistor 17,18,191,192,193 and switch transistors 201, 202 and 203, and configured to have, and outputs the reference potential _{v r} to the reference potential output point 21.

  The RF cutoff circuit 25 includes transmission lines 23a and 23b and a grounding capacitor 24.

The capacitance values C ₁ , C ₂ , and C ₃ of the switching capacitors 111a, 112a, 113a, 111b, 112b, and 113b are usually set to different values. The input signals V _SW1 , V _SW2 , and V _SW3 to the frequency band switching terminals 41, 42, and 43 are normally set to two values of High and Low, and High = VDD (power supply voltage) and Low = 0. There are many cases. In this example, the case of 3 bits is shown, but the number of bits is arbitrarily set as necessary.

  Next, the operation of the VCO of this embodiment will be described.

  The cross-coupled portion formed by the cross-coupled NMOS transistors 5a and 5b and the cross-coupled portion formed by the cross-coupled PMOS transistors 6a and 6b generate a negative resistance. This negative resistance compensates for the loss generated in other parts of the circuit with the oscillation frequency, thereby realizing a sustained oscillation operation.

  The output buffer 16 functions to set the output level and output amplitude to appropriate values and to block the influence of an external circuit on the VCO oscillation frequency. However, the configuration of the buffer circuit is arbitrary, and the buffer circuit itself is not an essential requirement of the present invention.

  The RF cut-off circuit 25 sets the electrical length of the transmission lines 23a and 23b to ¼ wavelength at the oscillation frequency, thereby leaking RF power from the connection point between the variable capacitive element 8a (8b) and the capacitive element 9a (9b). And the influence of the reference potential generating circuit 22 on the RF characteristics of the VCO is avoided. Use of a low-loss transmission line has an effect of preventing deterioration of phase noise. However, the VCO in the present embodiment is used by changing the oscillation frequency by the frequency band switching signal and the loop control voltage.

  The electrical length can be ¼ wavelength only at one of the frequencies. However, since the frequency range to be used is not so large in many cases, the above function is maintained in the frequency range to be used if one wavelength is set to ¼ wavelength. Note that the electrical length is not limited to ¼ wavelength. For example, the electrical length can be a wavelength in a range of ± 20% of the ¼ wavelength. If operation in a larger frequency range is required, the RF cutoff circuit 25 may be changed to a wider band configuration.

The capacitance value C _v of the variable capacitance elements 8a and 8b depends on both the loop control voltage v _CNT and the reference potential v _r and can be written as C _v (v _CNT , v _r ). If the capacitance values of the variable capacitance units 10a and 10b are C _vm , the following (Equation 3) is obtained.

Here, the impedance of the RF cutoff circuit 25 viewed from the connection point between the variable capacitance element 8a (8b) and the capacitance element 9a (9b) is assumed to be sufficiently large in the considered frequency band, and the influence is ignored. . C _vm is a monotonically increasing function of C _v . The rate of change for the loop control voltage v _CNT of the capacitance of the variable capacitance unit, the center voltage v _0, and becomes the following (Equation 4).

  The oscillation frequency is approximately (Equation 5) below.

The frequency f (v _CNT0 ) when the loop control voltage v _CNT is the center voltage v _CNT0 will be referred to as the center frequency. That is, the center frequency is expressed by the following (Equation 6).

Here, C _f represents the contribution of parasitic capacitance components in portions other than the variable capacitance portions 10a and 10b, such as the cross-coupled transistors 5a, 5b, 6a, and 6b. C _SW represents the capacity of the switching capacitors 13a and 13b, and 8 from 0 to (C ₁ + C ₂ + C ₃ ) depending on the input signals (frequency switching signals) to the frequency band switching terminals 41, 42, and 43. It can be set to one value. However, for simplification of description, the capacitances of the switch transistors 121a, 122a, 123a, 121b, 122b, and 123b are ignored. Due to this change in _CSW , the center frequency becomes discretely variable, and multiband operation is possible. At this time, the VCO gain is expressed by the following (Equation 7).

  Here, the capacitance-voltage characteristic (CV characteristic) of the first variable capacitance element will be described.

  FIG. 4 shows an example of CV characteristics of an accumulation mode varactor used as a variable capacitance element in a CMOS (Complementary Metal Oxide Semiconductor) process.

  As shown in FIG. 4, the CV characteristic shows a good linearity over a wide capacitance value range. In the description of the operation of this embodiment, it is assumed that the linear portion of the CV characteristic is used. However, this premise is for simplifying the explanation and is not an essential requirement of the present invention. Therefore, the variable capacitor used is not limited to the above.

Figure 5 is a capacitance of the variable capacitance element when changing the reference voltage v _r - in which the voltage characteristic shown schematically. As shown in FIG. 5, v when changing the _r capacity - voltage characteristic moves parallel to the right and left. At this time, the value of C _v at v _CNT = v ₀ changes, while the slope (the rate of change of C _v with respect to v _CNT ∂C _v / ∂v _CNT | _{vCNT = v 0} ) is held constant.

In the present embodiment, input signals (frequency band switching signals), V _SW1 , V _SW2 , V _SW3 , to the frequency band switching terminals 41, 42, and 43 are input to the reference potential generation circuit 22 and interlocked with the frequency band switching. Thus, the reference potential v _r is changed. Specifically, v _r is reduced when lowering the center frequency increase C _SW, to have a mechanism such as v _r is increased when increasing the center frequency to reduce the C _SW to the reference potential generating circuit 22.

At this time, a mechanism for suppressing the VCO gain fluctuation will be qualitatively described. Here, a case where v _r is simultaneously decreased when C _SW is increased will be described. The reverse case can be explained in the same manner.

First, when v _r is decreased, the value of C _v is decreased as shown in FIG. At this time, the capacitance value C _vm of the variable capacitance section 10a or 10b is reduced by (Equation 3).

Next, the rate of change of C _vm given by (Equation 4) with respect to the loop control voltage v _CNT will be considered. As described above, while decreases Cv in the denominator [·], the rate of change with respect to _{v CNT} of _{C v} as shown in FIG. _{5 (∂C v / ∂v CNT |} vCNT = v0) is held constant The Therefore, ∂C _vm / ∂v _CNT | _{vCNT = v 0} increases.

Next, consider the center frequency given by (Equation 6). Although C _vm in the denominator [·] decreases and C _SW increases, it moves in the opposite direction, but this is designed to exceed the effect of increasing C _SW . That is, (C _vm + C _SW ) increases, and as a result, the center frequency decreases. Finally, consider the VCO gain given by (Equation 7).

As (C _vm + C _SW ) in the denominator [·] increases, ∂C _vm / ∂v _CNT | _{vCNT = v 0} also increases. Therefore, it can be seen that VCO gain fluctuations can be suppressed by offsetting the effects of these two increases.

In fact, for each of the eight states (V _SW1 , V _SW2 , V _SW3 ), there is an optimum reference potential v _r that suppresses the VCO gain fluctuation. Schematically illustrates this optimum v _r by a dotted line in FIG.

Reference potential generating circuit 22, an approximation of the optimum reference potential _{v r} on the state of each _{(V SW1, V SW2, V} SW3) shown in FIG. 6, to generate a reference potential output point 21. The reference potential _{v r} in accordance with _{(V SW1, V SW2, V} SW3), the different values of the following (Equation 8).

Here, G _i = 1 / R _i (i = 1, 2) and g _j = 1 / r _j (j = 1, 2, 3). In addition, Δ _j = 1 when V _SWj is high, and Δ _j = 0 when _{j is} low (j = 1, 2, 3). The resistance _{values, R i (i = 1,2)} , by choosing r j (j = 1,2,3) to an appropriate value, an approximation of the optimum value of _{v r} indicated by the dotted line in FIG. 6 It can occur in each state (solid line in FIG. 6).

  The effect of VCO gain fluctuation suppression was confirmed by circuit simulation. FIG. 3 is a graph showing fluctuations in VCO gain when the center frequency is changed by switching the setting of the frequency switching signal to eight stages for the VCO of this embodiment shown in FIG. 3 and the related VCO shown in FIG. 7 shows.

  The simulation was performed by the harmonic balance method (harmonic balance method). Assuming 40Gbps optical communication system applications, the center frequency range was designed to cover 39.8GHz (OC-768), 43.01GHz (OUT-3), and 44.57GHz (10GbE × 4).

  It can be seen that the VCO of this embodiment shown in FIG. 3 can suppress the VCO gain fluctuation accompanying the center frequency control to about 1/19 compared to the related VCO shown in FIG.

<Operation and effect of this embodiment>
As described above, the VCO according to the present embodiment can suppress the fluctuation of the VCO gain when the center frequency is controlled. In addition, the VCO according to the present embodiment can achieve the above-described object with almost no complication of the circuit configuration of the portion having a strong influence on the high-frequency characteristics. Therefore, the VCO of the present embodiment is particularly suitable when applied to an ultrahigh frequency band such as a millimeter wave band.

[Second Embodiment]
Next, a second embodiment will be described.

  FIG. 8 is a configuration diagram of the VCO in the second embodiment. The same parts as those of the VCO of the first embodiment shown in FIG.

  In the VCO of the first embodiment, frequency band switching is performed with 3 bits, but the number of bits can be arbitrarily set. In the VCO of this embodiment, the configuration is generally shown for the case of k bits (k is an arbitrary natural number).

  In the VCO of this embodiment shown in FIG. 8, both of the switching capacitor units 13a and 13b and the reference potential generation circuit 22 are k bits.

[Third embodiment]
Next, a third embodiment will be described.

  FIG. 9 is a configuration diagram of a VCO according to the third embodiment. The same parts as those of the VCO of the first embodiment shown in FIG.

  In the VCO of the first embodiment, the generation of negative resistance is a complementary type using both NMOS and PMOS cross-coupled transistors.

  However, the VCO of this embodiment shown in FIG. 9 can be applied to a VCO using an arbitrary negative resistance generation circuit. As an example of the VCO of this embodiment, a negative resistance generation circuit is configured by NMOS cross-coupled transistors 5a and 5b (NMOS type), and a current source 26 is provided between the power supply terminal 1 and the inductors 7a and 7b. Shows the configuration.

[Fourth Embodiment]
Next, a fourth embodiment will be described.

  FIG. 10 is a configuration diagram of a VCO according to the fourth embodiment. The same parts as those of the VCO of the first embodiment shown in FIG.

  In the VCO of the first embodiment, the switching capacitors 13a and 13b are configured by switching capacitors 111a, 112a, 113a, 111b, 112b, and 113b, and switch transistors 121a, 122a, 123a, 121b, 122b, and 123b. .

  The VCO according to this embodiment shown in FIG. 10 includes PMOS transistors 271a, 272a, 273a, 271b, 272b, and 273b. As described above, the switching capacitors 13a and 13b can be configured by various elements that can change the capacitance values discretely by the frequency band switching signal.

[Fifth Embodiment]
Next, a fifth embodiment will be described.

  FIG. 11 is a configuration diagram of a VCO according to the fifth embodiment. The same parts as those of the VCO of the first embodiment shown in FIG.

  In the VCO of the present embodiment shown in FIG. 11, the switch transistors of the switching capacitors 13a and 13b and the switch transistor of the reference potential generation circuit 22 are shared. As a result, the reference potential generating circuit 22 is composed of only resistive elements. Among these, the resistors 191, 192, and 193 are connected to the switch transistors in the switching capacitors 13 a and 13 b, and their termination conditions are switched between open and ground. Thus, by sharing the switch transistor, the number of elements can be reduced.

[Sixth Embodiment]
Next, a sixth embodiment will be described.

  FIG. 12 is a configuration diagram of a VCO according to the sixth embodiment. The same parts as those of the VCO of the first embodiment shown in FIG.

In the VCO of the present embodiment shown in FIG. 12, the variable capacitance units 10a and 10b are configured only by the variable capacitance elements 8a and 8b, respectively. Further, the transmission line 23 of the RF cutoff circuit 25 is one. An adder circuit 28 is connected to the connection point of the variable capacitance elements 8a and 8b. This adder circuit 28, a loop control voltage v _CNT supplied from the loop control terminal 3, two reference potentials v _r supplied from the reference potential generating circuit 22 via the RF cutoff circuit 25 is input, the sum ( v _CNT + v _r ) is output to the connection point of the variable capacitance elements 8a and 8b.

  Next, the operation of the VCO of this embodiment will be described.

Figure 13 shows the variable capacitance element 8a, the relationship between the capacitance value _{C v} and the loop control voltage _{v CNT} of 8b. As shown in FIG. 13, as in the first embodiment, when changing the v _r, capacitance - voltage characteristic moves parallel to the transverse direction. Therefore, the same principle as that described in the first embodiment, it is possible to control the VCO gain according to the value of v _r. Therefore, by appropriately selecting the parameters of the reference potential generation circuit 22, it is possible to suppress VCO gain fluctuations associated with frequency band switching.

[Seventh Embodiment]
Next, a seventh embodiment will be described.

  FIG. 14 is a block diagram of a phase-locked loop (PLL) circuit according to the seventh embodiment, and shows an application example of the VCO according to the present embodiment.

  A voltage controlled oscillator 29 in FIG. 14 represents the VCO shown in any one of FIGS. 3, 8, 9, 10, 11, and 12. The output of the VCO shown in any one of FIG. 3, FIG. 8, FIG. 9, FIG. 10, FIG. 11 and FIG. 12 is a differential output. These are collectively shown as 2.

  The PLL circuit of this embodiment shown in FIG. 14 includes a voltage controlled oscillator 29, a reference clock signal input terminal 30, a clock signal output terminal 31, a phase comparator 32, a loop filter 33, and a frequency divider 34. To do.

  By changing the frequency band switching signal input to the frequency band switching terminals 41, 42 and 43, the center frequency band of the VCO can be switched. As a result, the PLL circuit of this embodiment operates in a plurality of frequency bands. Is possible. At this time, since the VCO gain is kept constant, the PLL loop gain is also kept constant. Therefore, it is possible to ensure optimum PLL operation in a plurality of operating frequency bands.

  In the above description, it is assumed that the gains of the constituent blocks other than the VCO do not depend on the operating frequency band. However, there is a case where the gain of a configuration block other than the VCO (for example, the phase comparator 32) varies depending on the operating frequency band. In such a case, a specific VCO gain fluctuation (relationship between the VCO gain and the center frequency) is required to keep the gain of the entire loop constant. Even in this case, it is possible to approximately create a relationship between an arbitrary VCO gain and a center frequency by setting parameters of the reference potential generating circuit 22.

[Eighth embodiment]
Next, an eighth embodiment will be described.

  FIG. 15 is a block diagram of a clock and data recovery (CDR) circuit according to the eighth embodiment, showing an application example of the VCO according to the present embodiment.

  A voltage controlled oscillator 29 in FIG. 15 represents the VCO shown in any one of FIGS. 3, 8, 9, 10, 11, and 12.

  The CDR circuit of the present embodiment shown in FIG. 15 includes a voltage controlled oscillator 29, a phase comparator 32, a loop filter 33, a data signal input terminal 35, a reproduction clock signal output terminal 36, a reproduction data signal output terminal 37, a delay circuit 38, A flip-flop circuit 39 is provided.

  The center frequency band of the VCO can be switched by changing the frequency band switching signal input to the frequency band switching terminals 41, 42, 43. As a result, the CDR circuit of this embodiment operates at a plurality of bit rates. Is possible. At this time, since the VCO gain is kept constant, the loop gain is also kept constant. Therefore, it is possible to ensure optimum CDR operation in a plurality of operating frequency bands.

  In the above description, it is assumed that the gains of the constituent blocks other than the VCO do not depend on the operating frequency band. However, there is a case where the gain of a configuration block other than the VCO (for example, the phase comparator 32) varies depending on the operating frequency band. In such a case, a specific VCO gain fluctuation (relationship between the VCO gain and the center frequency) is required to keep the gain of the entire loop constant. Even in this case, it is possible to approximately create a relationship between an arbitrary VCO gain and the center frequency by setting parameters of the reference potential generation circuit 22.

[Ninth Embodiment]
Next, a ninth embodiment will be described.

  FIG. 16 is a block diagram of a clock and data recovery (CDR) circuit according to the ninth embodiment, showing an application example of the VCO according to the present embodiment.

  A voltage controlled oscillator 29 in FIG. 16 represents the VCO shown in any one of FIGS. 3, 8, 9, 10, 11, and 12.

  The same parts as those in the CDR of the eighth embodiment shown in FIG. 15 are denoted by the same reference numerals.

  A bit rate detection circuit 40 is added to the CDR circuit of this embodiment shown in FIG. The bit rate detection circuit 40 detects the bit rate of the input data signal and outputs a frequency band switching signal to the frequency band switching terminals 41, 42, and 43 based on the detection result. That is, since the center frequency of the VCO is automatically set according to the input signal bit rate, it can be applied to systems having different input signal bit rates without adjustment. Furthermore, the present invention can be applied to a system in which the input signal bit rate changes with time. At this time, the VCO gain fluctuation is also automatically suppressed.

  The above-described embodiment is a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above-described embodiment alone, and various modifications are made without departing from the gist of the present invention. Implementation is possible.

  For example, in the above-described embodiment, the differential VCO has been described. However, the present embodiment can also be applied to a single-phase VCO.

  In the above-described embodiment, the configuration using the transmission line as the RF cutoff circuit has been described. However, the configuration is not limited to this configuration, and for example, a configuration using a resistor or the like is also possible.

  In the above-described embodiment, the example in which the transistor is used as the switch element has been described. However, other switch elements can be used.

  In the above-described embodiment, an example in which a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is used as an active element has been shown. However, a MESFET (Metal Semiconductor Field Effect Transistor), a HEMT (High Electron Mobility Transistor), a bipolar transistor, and the like Even in the case where is used, it is possible to realize the same configuration.

  Further, in the above-described embodiment, the design example in which the variation of the VCO gain is suppressed as much as possible is shown. However, specific VCO gain fluctuations (relationship between VCO gain and center frequency) may be required from the requirements of the PLL loop in which the VCO is used. Even in such a case, if this embodiment is used, it is possible to approximately create a relationship between an arbitrary VCO gain and a center frequency by setting parameters of the reference potential generation circuit 22.

  In addition, the control operation in each device configuring the VCO in the present embodiment described above can be executed using hardware, software, or a combined configuration of both.

  In the case of executing processing using software, it is possible to install and execute a program in which a processing sequence is recorded in a memory in a computer incorporated in dedicated hardware. Alternatively, the program can be installed and executed on a general-purpose computer capable of executing various processes.

  For example, the program can be recorded in advance on a hard disk or ROM (Read Only Memory) as a recording medium. Alternatively, the program can be stored (recorded) temporarily or permanently in a removable recording medium. Such a removable recording medium can be provided as so-called package software. Examples of the removable recording medium include a floppy (registered trademark) disk, a CD-ROM (Compact Disc Read Only Memory), an MO (Magneto optical) disk, a DVD (Digital Versatile Disc), a magnetic disk, and a semiconductor memory.

  The program is installed in the computer from the removable recording medium as described above. In addition, it is wirelessly transferred from the download site to the computer. In addition, it is transferred to the computer via a network by wire.

  In addition, the VCO in this embodiment not only performs processing in time series according to the processing operation described in the above embodiment, but also the processing capability of the apparatus that performs the processing, or in parallel or individually as necessary. It is also possible to construct to execute processing.

  As is clear from the above description, the voltage controlled oscillator (VCO) of this embodiment has the following characteristics.

  The VCO of the present embodiment is a VCO that has a second frequency variable means separately from the first frequency variable means to which the loop control voltage is applied, and performs a multiband operation. Then, there is a reference potential generating means in which two resistance elements are connected in series, and one or more sets of circuits in which the resistance elements and the switch elements are connected in series are connected in parallel at the connection point of the two resistance elements. And configure. The switch element in the reference potential generating means is controlled by the frequency band switching signal of the second frequency variable means, and as a result, the output voltage of the reference potential generating means that depends on the frequency band switching signal is The frequency variable means is applied to a terminal different from the terminal to which the loop control voltage is applied.

  In addition, the VCO of the present embodiment is a VCO that has a second frequency variable means separately from the first frequency variable means to which the loop control voltage is applied, and performs a multiband operation. Then, there is a reference potential generating means in which two resistance elements are connected in series, and one or more sets of circuits in which the resistance elements and the switch elements are connected in series are connected in parallel at the connection point of the two resistance elements. And configure. Then, the switching element in the reference potential generating means is controlled by the frequency band switching signal of the second frequency variable means, and as a result, the output voltage and loop control of the reference potential generating means which depends on the frequency band switching signal. The sum with the voltage is applied to the terminal of the first frequency variable means.

  In addition, the VCO of the present embodiment is a VCO that has a second frequency variable means separately from the first frequency variable means to which the loop control voltage is applied, and performs a multiband operation. Then, two resistance elements are connected in series, and a reference potential generating means is provided in which one or more resistance elements are connected in parallel at the connection point of the two resistance elements. Then, the resistance element connected in parallel is connected to the switch element included in the second frequency variable means, and as a result, the output voltage of the reference potential generating means that depends on the frequency band switching signal is the first voltage. The frequency variable means is applied to a terminal different from the terminal to which the loop control voltage is applied.

  In addition, the VCO of the present embodiment is a VCO that has a second frequency variable means separately from the first frequency variable means to which the loop control voltage is applied, and performs a multiband operation. Then, two resistance elements are connected in series, and a reference potential generating means is provided in which one or more resistance elements are connected in parallel at the connection point of the two resistance elements. Then, the resistance element connected in parallel is connected to the switch element included in the second frequency variable means, and as a result, the output voltage and the loop control voltage of the reference potential generating means which depends on the frequency band switching signal. Is added to the terminal of the first frequency variable means.

  Thus, the VCO of the present embodiment is a VCO that has two frequency variable means and performs a multi-band operation, has a reference potential generating means composed of a resistor and a switch element, and the switch element is Control is performed by a frequency switching signal for performing center frequency control. Control of the center frequency by applying the output voltage of the reference potential generating means depending on the frequency switching signal to the terminal on the opposite side to the side to which the loop control voltage of the variable capacitance element is applied via the RF cutoff circuit. It becomes possible to suppress the fluctuation of the VCO gain associated with.

  In addition, the VCO according to the present embodiment can achieve the above object with almost no complication of the circuit configuration of the portion having a strong influence on the high frequency characteristics. Therefore, the VCO of the present embodiment is particularly suitable for application to an ultrahigh frequency band such as a millimeter wave band.

  This application claims priority based on Japanese Patent Application No. 2008-019736 filed on January 30, 2008, the entire disclosure of which is incorporated herein.

  The present invention is applicable to a voltage controlled oscillator (VCO) operating in a multiband.

It is a figure which shows the circuit structural example of the voltage control oscillator (VCO) relevant to this invention. It is a conceptual diagram which shows the relationship between VCO gain and center frequency in VCO relevant to this invention. It is a figure which shows the circuit structural example of the voltage control oscillator (VOC) in 1st Embodiment. It is a graph which shows the capacity | capacitance versus voltage characteristic of a variable capacitance element. It is a schematic diagram which shows the capacity | capacitance versus voltage characteristic of a variable capacitance element. It is a schematic diagram for demonstrating operation | movement of VCO of this embodiment. It is the graph which showed the circuit simulation result for demonstrating the effect of VCO of this embodiment. It is a figure which shows the circuit structural example of VCO in 2nd Embodiment. It is a figure which shows the circuit structural example of VCO in 3rd Embodiment. It is a figure which shows the circuit structural example of VCO in 4th Embodiment. It is a figure which shows the circuit structural example of VCO in 5th Embodiment. It is a figure which shows the circuit structural example of VCO in 6th Embodiment. It is a schematic diagram which shows the capacity | capacitance versus voltage characteristic of a variable capacitance element. It is a figure which shows the circuit structural example in 7th Embodiment. It is a figure which shows the circuit structural example in 8th Embodiment. It is a figure which shows the circuit structural example in 9th Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Power supply terminal 2, 2a, 2b Output terminal 3 Loop control terminal 41, 42, 43, 4k Frequency band switching terminal 5a, 5b Cross coupling NMOS transistor 6a, 6b Cross coupling PMOS transistor 7, 7a, 7b Inductor 8a, 8b Variable capacitance Element 9a, 9b Capacitance element 10a, 10b Variable capacitance part 111a, 112a, 113a, 11ka, 111b, 112b, 113b, 11kb Switching capacitance element 121a, 122a, 123a, 12ka, 121b, 122b, 123b, 12kb Switch transistor 13a, 13b Switching capacitor 14a, 14b Output transistor 15a, 15b Output resistor 16 Output buffer 17, 18, 191, 192, 193, 19k Resistor 201, 202, 203, 20k Switch transistor 21 Reference potential output point 22 Reference potential generation circuit 23, 23a, 23b Transmission line 24 Ground capacitance 25 RF cutoff circuit 26 Current source 271a, 272a, 273a, 271b, 272b, 273b PMOS transistor 28 Addition circuit 30 Reference clock signal input terminal 31 Clock signal output terminal 32 Phase comparator 33 Loop filter 34 Frequency divider 35 Data signal input terminal 36 Playback clock signal output terminal 37 Playback data signal output terminal 38 Delay circuit 39 Flip-flop circuit 40 Bit rate detection circuit

Claims (20)

A voltage controlled oscillator having first frequency variable means to which a loop control voltage is applied, and second frequency variable means,
Reference potential generating means for controlling the frequency band switching signal of the second frequency variable means and outputting a voltage depending on the frequency band switching signal,
The voltage controlled oscillator, wherein an output voltage of the reference potential generating means is applied to a terminal different from a terminal to which a loop control voltage of the first frequency variable means is applied. A voltage controlled oscillator having first frequency variable means to which a loop control voltage is applied, and second frequency variable means,
Reference potential generating means for controlling the frequency band switching signal of the second frequency variable means and outputting a voltage depending on the frequency band switching signal,
The voltage controlled oscillator, wherein a sum of an output voltage of the reference potential generating means and a loop control voltage is applied to a terminal of the first frequency variable means.   3. The voltage according to claim 2, wherein the sum of the output voltage of the reference potential generating means and the loop control voltage is generated by inputting the output voltage of the reference potential generating means and the loop control voltage to the adding means. Controlled oscillator.   The voltage-controlled oscillator according to any one of claims 1 to 3, wherein the first frequency variable means includes a variable capacitance element.   5. The voltage controlled oscillator according to claim 1, wherein the second frequency variable means includes a capacitive element and a switch element. 6.   6. The voltage controlled oscillator according to claim 5, wherein the switch element comprises a transistor.   5. The voltage controlled oscillator according to claim 1, wherein the second frequency variable means includes a transistor or a variable capacitance element. 6.   8. The reference potential generating means includes a resistance element and a switch element, and the switch element is controlled by a frequency band switching signal of the second frequency variable means. The voltage controlled oscillator according to any one of claims.   In the reference potential generating means, a first resistance element and a second resistance element are connected in series, and a resistance element and a switch element are connected to a connection point between the first resistance element and the second resistance element. 9. The voltage controlled oscillator according to claim 8, wherein one or more sets of circuits connected in series are connected in parallel.   6. The reference potential generating means comprises at least one resistance element, and at least one of the resistance elements is connected to a switch element included in the second frequency variable means. Or the voltage controlled oscillator of 6.   In the reference potential generating means, a first resistance element and a second resistance element are connected in series, and one or more resistance elements are provided at a connection point between the first resistance element and the second resistance element. 11. The voltage controlled oscillator according to claim 10, wherein the voltage controlled oscillator is connected in parallel, and the resistance element connected in parallel is connected to a switch element included in the second frequency variable means.   12. The voltage controlled oscillator according to claim 1, further comprising: a high-frequency signal blocking unit between the reference potential generating unit and the first and second frequency variable units. .   13. The voltage controlled oscillator according to claim 12, wherein the high frequency signal blocking means includes a transmission line and a grounded capacitor.   14. The voltage controlled oscillator according to claim 13, wherein the electrical length of the transmission line is about ¼ wavelength at an arbitrary operating frequency.   15. The voltage controlled oscillator according to claim 1, wherein the voltage controlled oscillator is a differential voltage controlled oscillator.   The voltage controlled oscillator according to claim 1, wherein the voltage controlled oscillator is a single-phase voltage controlled oscillator.   A phase-locked loop circuit comprising the voltage-controlled oscillator according to claim 1.   A clock / data recovery circuit comprising the voltage controlled oscillator according to claim 1. A control method of a voltage controlled oscillator having a first frequency variable means to which a loop control voltage is applied, a second frequency variable means, and a reference potential generating means,
The reference potential generating means outputting a voltage depending on a frequency band switching signal of the second frequency variable means;
And a step of controlling the output voltage of the reference potential generating means to be applied to a terminal different from the terminal to which the loop control voltage of the first frequency variable means is applied. Method. A control method of a voltage controlled oscillator having a first frequency variable means to which a loop control voltage is applied, a second frequency variable means, and a reference potential generating means,
The reference potential generating means outputting a voltage depending on a frequency band switching signal of the second frequency variable means;
And a step of controlling so that the sum of the output voltage of the reference potential generating means and the loop control voltage is applied to the terminal of the first frequency variable means.

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