JPWO2009066342A1 - Binary search circuit and method - Google Patents

Abstract

The binary search circuit 36 searches the comparison target data by the binary search from the first database 50 storing the data arranged in ascending order or descending order. When the search target range of the first database 50 is divided into 2n pieces, the control circuit 36Z compares the comparison target data x and the data of the search target range 1 / 2n, ..., (2n-1) / 2n Is input to each of the 2n-1 comparison circuits 36A to 36O, and as a first step, 2n1 to which data at a position of 1 / 2n1, ..., (2n1-1) / 2n1 of the search target range is input -The range is determined by one comparison circuit, and as the second stage, 2n2- is input as the data of the position of 1 / 2n2, ..., (2n2-1) / 2n2 of the range determined in the first stage The range is determined by one comparison circuit, and thereafter, the search is repeated n times by repeating until the Nth stage (where n1 +... + NN = n).

Description

  The present invention relates to a data processing technique, and more particularly to a binary search circuit and method for searching data from a database by a binary search method.

  With the development of the Internet infrastructure and the widespread use of communication terminals such as mobile phone terminals, personal computers, and VoIP (Voice over Internet Protocol) telephone terminals, the number of Internet users is increasing explosively. Under such circumstances, security problems such as computer viruses, hacking, and spam mails are becoming obvious, and a technique for appropriately controlling communication is required. With the improvement of the communication environment, the amount of communication has become enormous, and the need for a communication control device that processes large volumes of data at high speed is increasing.

FIG. 1 shows a configuration of a conventional communication control apparatus 1. The conventional communication control device 1 includes a communication control unit 2 on the reception side, a packet processing unit 3, and a communication control unit 4 on the transmission side. The communication control units 2 and 4 include PHY processing units 5a and 5b that perform processing on the physical layer of the packet, and MAC processing units 6a and 6b that perform processing on the MAC layer of the packet, respectively. The packet processing unit 3 includes a protocol processing unit that performs processing according to a protocol, such as an IP processing unit 7 that performs IP (Internet Protocol) protocol processing and a TCP processing unit 8 that performs TCP (Transport Control Protocol) protocol processing. And an AP processing unit 9 that performs application layer processing. The AP processing unit 9 performs processing such as filtering according to the data included in the packet.
JP-A-4-180425

  In the conventional communication control apparatus 1, the packet processing unit 3 is realized by software using a CPU that is a general-purpose processor and an OS that runs on the CPU. However, with such a configuration, the performance of the communication control device 1 depends on the performance of the CPU, and there is a limit to the implementation of a communication control device that can process a large-capacity packet at high speed. For example, in the case of a 64-bit CPU, the maximum amount of data that can be processed simultaneously at a time is 64 bits, and there has been no communication control device having higher performance.

  In this way, even if the infrastructure such as an optical communication network is widespread and the data communication speed between nodes has been dramatically improved, the processing speed of the communication control device becomes the rate-determining and its ability is fully demonstrated. It is the actual situation that has not been made. Therefore, there is a strong demand to quickly realize a communication control device that is as fast as possible.

  The present invention has been made in view of such circumstances, and an object thereof is to provide a technique for realizing high-speed database search.

One embodiment of the present invention relates to a binary search circuit. This binary search circuit is a circuit for searching for comparison target data by a binary search from a database storing data arranged in ascending or descending order, and compares the data read from the database with the comparison target data 2 ⁿ -1 comparison circuits and a control circuit that controls the comparison circuit, and the control circuit divides the search target range of the database into 2 ⁿ pieces, ^{1/2 n,} 2/2 n of said search range, ^..., and the data of the position of the (2 n -1) / ^{2 n,} is input to each of the ² n -1 comparison circuits, First, as a first stage, 2 ⁿ¹ −1 comparisons in which data at positions of 1/2 ⁿ¹ , ^{2/2 n1} ,..., (2 ⁿ¹ −1) / 2 ⁿ¹ of the search target range are input. Before circuit Comparison target data, the search range to determine one to belongs of the ranges divided in 2 ⁿ¹ pieces, followed, in a second stage, 1/2 n2 range determined in the first ^step, 2 / 2 ⁿ² ,..., (2 ⁿ² −1) / 2 The comparison target data is converted into the 2 ^{n1 + n2} search target ranges by 2 ⁿ² −1 comparison circuits to which data at the position of ⁿ² is input. It is determined which of the divided ranges it belongs to, and thereafter, in the same manner, by repeating up to the Nth stage (where n1 + n2 +... + NN = n), n times of searches are executed. When the comparison target data is not searched, a position of ½ ⁿ , 2/2 ⁿ ,..., (2 ⁿ −1) / 2 ⁿ newly determined in the Nth stage Of the 2 ⁿ -1 comparison circuits And the next n searches are executed.

  The binary search circuit uses the output signal indicating the comparison result of the m-th (1 ≦ m <N) -stage comparison circuit to determine the data in the range determined in the m-th stage among the next (m + 1) -th comparison circuits. A trigger circuit that generates a trigger signal that causes the comparison circuit to input the comparison to be input to the (m + 1) -th stage comparison circuit may be further provided.

When the output signal indicating a different comparison result is output from an adjacent comparison circuit among the 2 ^m −1 comparison circuits in the m-th stage, the trigger circuit is configured to store the data input to the comparison circuits. The trigger signal may be input to the (m + 1) -th stage comparison circuit to which data in the range is input.

In the m-th (1 ≦ m <N) stage, the 2 ^m −1 comparison circuits may perform the comparison in parallel.

Binary search circuit may comprise a 2 ⁿ -1 one of said database connected to each of the comparator circuit, the control circuit, 1/2 n, ^2/2 n of said search ^range, ... The data at the position (2 ⁿ -1) / 2 ⁿ may be input in parallel from the database connected to each comparison circuit.

Another aspect of the present invention relates to a binary search method. In this binary search method, when the search target range of the database storing data arranged in ascending or descending order is divided into 2 ⁿ pieces, the comparison target data and 1/2 ^{n of the} search target range, 2/2 ⁿ ,..., (2 ⁿ −1) / 2 ⁿ position data is input to each of the 2 ⁿ −1 comparison circuits, and as a first step, 1/2 of the search target range. ⁿ¹ , ^{2/2 n1} ,..., (2 ⁿ¹ −1) / 2 The data to be compared is ^divided into two search target ranges by 2 ⁿ¹ −1 comparison circuits to which data at the position of ⁿ¹ is input. ^A step of determining which of the ranges divided into ⁿ¹ pieces and a second stage include 1/2 ⁿ² , ^{2/2 n2} ,... (2 ⁿ² − 1) / 2 ⁿ 2 ^where data at position ⁿ² is input ^{In the same} manner as the step of determining which of the ² 1 -1 comparison circuits the comparison target data belongs to the range obtained by dividing the search target range into 2 ^{n1 + n2} , and thereafter, the Nth stage (where n1 + n2 + ... + NN = n) by repeating the search for n times, and when the comparison target data is not searched in the n times of search, it is newly determined in the Nth stage. , ^N 2, 2/2 ⁿ ,..., (2 ⁿ −1) / 2 ⁿ is input to each of the 2 ⁿ −1 comparison circuits, and the next n Performing a batch of searches.

  It should be noted that any combination of the above-described constituent elements and a conversion of the expression of the present invention between a method, an apparatus, a system, a recording medium, a computer program, etc. are also effective as an aspect of the present invention.

  ADVANTAGE OF THE INVENTION According to this invention, the technique which implement | achieves a high-speed binary search can be provided.

It is a figure which shows the structure of the conventional communication control apparatus. It is a figure which shows the structure of the communication control apparatus which concerns on embodiment. It is a figure which shows the structure of a packet processing circuit. It is a figure which shows the structure of a position detection circuit. It is a figure which shows another example of a position detection circuit. It is a figure which shows another example of a position detection circuit. It is a figure which shows the internal data of a 1st database. It is a figure which shows another example of the internal data of a 1st database. It is a figure which shows another example of the internal data of a 1st database. It is a figure which shows another example of an index circuit. It is a figure which shows the structure of the comparison circuit contained in a binary search circuit. It is a figure which shows the structure of a binary search circuit. It is a figure which shows another example of the internal data of a 1st database. It is a figure which shows the example of the internal data of a 2nd database. It is a figure which shows another example of the internal data of a 2nd database. It is a figure which shows another structural example of a binary search circuit. It is a figure which shows another example of a structure of a binary search circuit.

Explanation of symbols

  10 communication control device, 20 packet processing circuit, 30 search circuit, 32 position detection circuit, 33 comparison circuit, 34 index circuit, 35 comparison circuit, 36 binary search circuit, 36A to 36O comparison circuit, 37 negation circuit, 38A, 38B exclusive Logical OR circuit, 36Z control circuit, 40 processing execution circuit, 50 first database, 60 second database.

  FIG. 2 shows a configuration of a communication control apparatus which is an example of the data processing apparatus of the present invention. The communication control device 10 according to the present embodiment is a packet processing unit configured by dedicated hardware using a wired logic circuit instead of the packet processing unit realized by software including a CPU and an OS in the conventional communication control device. A circuit 20 is provided. Rather than processing communication data with an OS and software that run on a CPU that is a general-purpose processing circuit, a dedicated hardware circuit for processing communication data is provided, thereby limiting the performance limit caused by the CPU, OS, etc. It is possible to overcome and realize a communication control device with high processing capability.

  For example, when searching for whether or not the data included in the packet includes reference data that is a criterion for filtering in order to perform packet filtering or the like, the communication data and the reference data are compared using the CPU. However, only 64 bits can be compared at a time, and even if it is attempted to improve the processing speed, there is a problem that the performance of the CPU reaches a peak. In the CPU, it is necessary to repeat the process of reading 64 bits from the communication data into the memory, comparing with the reference data, and then reading the next 64 bits into the memory. Time is rate limiting and processing speed is limited.

  On the other hand, in the present embodiment, a dedicated hardware circuit configured by a wired logic circuit is provided to compare communication data and reference data. This circuit includes a plurality of comparators provided in parallel to enable comparison of data lengths longer than 64 bits, for example, a data length of 1024 bits. In this way, by providing dedicated hardware, a large number of bit matching operations can be executed in parallel at the same time. The communication control apparatus 1 using a conventional CPU can process 1024 bits at a time, which can process only 64 bits at a time, and can dramatically improve the processing speed. If the number of comparators is increased, the processing capability is improved, but the cost and size also increase. Therefore, an optimum hardware circuit may be designed in consideration of desired processing performance, cost, size, and the like.

  Further, since the communication control apparatus 10 of the present embodiment is configured by dedicated hardware using a wired logic circuit, an OS (Operating System) is not required. For this reason, there is no need for OS installation, bug handling, version upgrade, and the like, and costs and man-hours for management and maintenance can be reduced. Unlike CPUs that require general-purpose functions, unnecessary functions are not included, so unnecessary resources are not used, and cost reduction, circuit area reduction, and processing speed improvement can be expected. . Furthermore, unlike conventional communication control devices that use an OS, it does not have an extra function, so it is unlikely that security holes will occur, and is resistant to attacks from malicious third parties via the network. Is excellent.

  The conventional communication control apparatus 1 processes a packet by software premised on a CPU and an OS, receives all data of the packet, performs protocol processing, and passes the data to the application. On the other hand, in the communication control apparatus 10 according to the present embodiment, since processing is performed by a dedicated hardware circuit, it is not necessary to start processing after receiving all the data of the packet. If received, the process can be started at an arbitrary time without waiting for the reception of subsequent data. For example, position detection processing in a position detection circuit described later can be started when position specifying data for specifying the position of comparison target data is received. As described above, since various processes can be executed in a floating manner without waiting for reception of all data, the time required to process packet data can be shortened.

  FIG. 3 shows the internal configuration of the packet processing circuit. The packet processing circuit 20 includes first databases 50A, 50B, and 50C that store reference data serving as a reference for determining the contents of processing to be performed on communication data (collectively, “first database 50”). And a search circuit 30 that searches whether the received communication data includes reference data by comparing the communication data with the reference data, and the search result by the search circuit 30 and the communication data. The second database 60 that stores the contents of the processing to be executed in association with each other, the processing execution circuit 40 that processes the communication data based on the search result by the search circuit 30 and the conditions stored in the second database 60. Including.

  When the search circuit 30 divides the reference data stored in the first database 50 into three or more ranges, the position detection circuit 32 detects the position of the comparison target data to be compared with the reference data from the communication data. An index circuit 34 that is an example of a determination circuit that determines to which of the ranges the comparison target data belongs; a binary search circuit 36 that searches for reference data that matches the comparison target data in the determined range; including. Although any search technique can be used as a method for searching the comparison target data from the reference data, the binary search method is used in the present embodiment. In the present embodiment, as will be described later, since an improved binary search method is used, three first databases 50 are provided for this purpose. The same reference data is stored in the first databases 50A, 50B, and 50C.

  FIG. 4 shows the internal configuration of the position detection circuit. The position detection circuit 32 includes a plurality of comparison circuits 33a to 33f for comparing the position specifying data for specifying the position of the comparison target data with the communication data. Here, six comparison circuits 33a to 33f are provided, but the number of comparison circuits may be arbitrary as will be described later. Communication data is input to each of the comparison circuits 33a to 33f with a predetermined data length, for example, shifted by 1 byte. In the plurality of comparison circuits 33a to 33f, the position specifying data to be detected and the communication data are compared in parallel at the same time.

  In the present embodiment, as an example for explaining the operation of the communication control apparatus 10, a character string “No. ##” included in the communication data is detected, and a number “ “##” is compared with the reference data, and the case where the packet is allowed to pass if it matches the reference data and the packet is discarded if it does not match will be described.

  In the example of FIG. 4, in order to detect the position specifying data “No.” for specifying the position of the number “####” from the communication data, the communication data “01No. 361. Each character is shifted and input to the comparison circuits 33a to 33f. That is, the comparison circuit 33a has "01N", the comparison circuit 33b has "1No", the comparison circuit 33c has "No.", the comparison circuit 33d has "o." . 3 ”and“ 36 ”are input to the comparison circuit 33f. Here, the comparison circuits 33a to 33f simultaneously perform comparison with the position specifying data “No.”. Thereby, the comparison circuit 33c matches, and it is detected that the character string “No.” exists in the third character from the head of the communication data. In this way, it is detected that numerical data that is comparison target data exists after the position specifying data “No.” detected by the position detection circuit 32.

  If similar processing is performed by the CPU, first, the character string “01N” is compared with “No.”, and then the character string “1No” is compared with “No.”. Since it is necessary to execute comparison processing one by one, improvement in detection speed cannot be expected. On the other hand, in the communication control apparatus 10 according to the present embodiment, by providing a plurality of comparison circuits 33a to 33f in parallel, simultaneous parallel comparison processing that cannot be performed by the CPU becomes possible, and the processing speed is remarkably increased. Can be improved. As the number of comparison circuits increases, the number of positions that can be compared simultaneously increases, so the detection speed also improves.However, considering the cost, size, etc., a sufficient number of comparison circuits are required to obtain the desired detection speed. What is necessary is just to provide.

  The position detection circuit 32 may be used not only for detecting position specifying data but also for detecting a character string for general use. Further, not only the character string but also the position specifying data may be detected in bit units.

  FIG. 5 shows another example of the position detection circuit. In the example illustrated in FIG. 5, when the position specifying data is shorter than the data length of each of the comparison circuits 33 a to 33 f provided in the position detecting circuit 32, predetermined data such as “ "00H" or "01H" is padded. For communication data to be compared with the position specifying data, only the same data length as the position specifying data is extracted, and then the same data as the data padded in the position specifying data is padded. At this time, in order not to modify the communication data itself, the communication data may be copied as a work, and the copied data may be processed and input to the comparison circuits 33a to 33f. Thereby, the position detection circuit 32 can be used for general purposes regardless of the data length of the position specifying data.

  FIG. 6 shows still another example of the position detection circuit. In the example shown in FIG. 6, as in the example shown in FIG. 5, predetermined data is padded after the position specifying data, but this data is treated as a wild card. In other words, when data that is a wild card is input, the comparison circuits 33a to 33f determine that the data to be compared matches unconditionally. Thereby, the position detection circuit 32 can be used for general purposes regardless of the data length of the position specifying data.

  FIG. 7 shows an example of internal data of the first database. The first database 50 stores reference data serving as a reference for determining processing contents such as packet filtering, routing, switching, and replacement, sorted in ascending or descending order according to some sort condition. In the example of FIG. 7, 1000 pieces of reference data are stored.

  When the reference data stored in the first database 50 is divided into three or more ranges 52a to 52d, the index circuit 34 determines to which of the ranges the comparison target data belongs. In the example of FIG. 7, 1000 pieces of reference data are divided into four ranges 52 a to 52 d, each having 250 pieces. The index circuit 34 includes a plurality of comparison circuits 35a to 35c that compare the reference data at the boundary of the range with the comparison target data. By comparing the comparison target data with the boundary reference data simultaneously in parallel by the comparison circuits 35a to 35c, it is possible to determine in which range the comparison target data belongs by one comparison process.

  The boundary reference data input to the comparison circuits 35 a to 35 c of the index circuit 34 may be set by a device provided outside the communication control device 10, or the reference data at a predetermined position in the first database 50 is previously stored. You may make it input automatically. In the latter case, even if the first database 50 is updated, the reference data at a predetermined position in the first database 50 is automatically input to the comparison circuits 35a to 35c. Processing can be executed.

  As described above, when a binary search is executed by the CPU, a plurality of comparisons cannot be executed at the same time. However, in the communication control device 10 of the present embodiment, a plurality of comparison circuits 35a to 35c are provided in parallel. Thus, simultaneous parallel processing can be performed, and the search speed can be remarkably improved.

When the range is determined by the index circuit 34, the binary search circuit 36 executes a search by the binary search method. The binary search circuit 36 further divides the range determined by the index circuit 34 into 2 ⁿ pieces, and compares the reference data at the boundary position with the comparison target data to determine which range the data belongs to. . The binary search circuit 36 includes a plurality of, for example, 1024 comparators in this embodiment for comparing the reference data and the comparison target data in bit units, and simultaneously executes 1024-bit bit matching. When it is determined which of the ^2n- divided ranges it belongs, the range is further divided into ²ⁿ , the reference data at the boundary position is read, and compared with the comparison target data. Thereafter, this process is repeated to further limit the range, and finally, reference data that matches the comparison target data is searched.

  The operation will be described in more detail using the example described above. “361” is input as comparison target data to the comparison circuits 35a to 35c of the index circuit 34, and reference data “378” at the boundary between the ranges 52a and 52b is input to the comparison circuit 35a as reference data. The reference data “704” at the boundary between the ranges 52b and 52c is input to 35b, and the reference data “937” at the boundary between the ranges 52c and 52d is input to the comparison circuit 35c. The comparison circuits 35a to 35c perform comparison at the same time, and it is determined that the comparison target data “361” belongs to the range 52a. Thereafter, the binary search circuit 36 searches whether or not the comparison target data “361” exists in the reference data.

  FIG. 8 shows another example of internal data of the first database. In the example shown in FIG. 8, the number of reference data is less than the number of data that can be held in the first database 50, here 1000. At this time, the first database 50 stores the reference data in descending order from the last data position. Then, 0 is stored in the remaining data. As a database loading method, data is placed from the back of the loading area without placing data from the beginning, and if there is a space at the beginning of the loading area, all the space is zero-suppressed, so the database is always full. The search time for binary search can be made constant. Further, when “0” is read as the reference data during the search, the binary search circuit 36 can determine the range without performing the comparison and can proceed to the next comparison because the comparison result is self-explanatory. Thereby, the search speed can be improved.

  In the software processing by the CPU, when the reference data is stored in the first database 50, the reference data is stored in ascending order from the first data position. For example, the maximum value is stored in the remaining data. In this case, the comparison process as described above cannot be omitted in the binary search. The comparison technique described above is realized by configuring the search circuit 30 with a dedicated hardware circuit.

  FIG. 9 shows still another example of internal data of the first database. In the example shown in FIG. 9, the reference data is not equally divided into three or more ranges, but the number of reference data belonging to the range is uneven, such as 500 for the range 52a and 100 for the range 52b. It has become. These ranges may be set according to the distribution of the appearance frequency of the reference data in the communication data. That is, the ranges may be set so that the sum of the appearance frequencies of the reference data belonging to the respective ranges is substantially the same. Thereby, search efficiency can be improved. The reference data input to the comparison circuits 35a to 35c of the index circuit 34 may be changeable from the outside. Thereby, a range can be set dynamically and search efficiency can be optimized.

  FIG. 10 shows another example of the index circuit. In the example shown in FIGS. 7 to 9, the index circuit 34 uses the three comparison circuits 35 a to 35 c to determine which of the four ranges 52 a to 52 d of the first database 50 belongs to the comparison target data. In the example of FIG. 10, the index circuit 34 is provided with four comparison circuits 35d to 35g for determining whether or not the comparison target data is included in each of the four ranges 52a to 52d. For example, the comparison circuit 35d receives the 0th reference data, the 250th reference data, and the comparison target data in the first database 50, and compares each reference data with the comparison target data. Thus, it is determined whether or not the reference data is included in the range 52a. The comparison results of the respective comparison circuits 35d to 35g are input to the determination circuit 35z, and the determination circuit 35z outputs in which range the reference data is included. The comparison circuits 35d to 35g may output whether or not the reference data is included between the two input reference data, and may be any one of larger than the range, included in the range, and smaller than the range. May be output. If it is determined that the comparison target data is not included in any of the ranges 52a to 52d, it can be seen that the comparison target data does not exist in the first database 50. The search can be terminated.

  FIG. 11 shows a configuration of a comparison circuit included in the binary search circuit. As described above, the comparison circuit included in the binary search circuit 36 includes 1024 comparators 36a, 36b,. Each of the comparators 36a, 36b,... Receives the reference data 54 and the comparison target data 56 one bit at a time, and compares them. The internal configurations of the comparison circuits 35a to 35c of the index circuit 34 are the same. In this way, by executing the comparison process with a dedicated hardware circuit, a large number of comparison circuits can be operated in parallel and a large number of bits can be compared simultaneously, so that the comparison process can be speeded up. .

  FIG. 12 shows the configuration of the binary search circuit. The binary search circuit 36 includes comparison circuits 36A, 36B, and 36C including the 1024 comparators 36a, 36b,... Shown in FIG. 11, and a control circuit 36Z that controls these comparison circuits.

  In the conventional binary search method, first, data at a position half the search target range of a database in which data is arranged in ascending or descending order is read and compared with comparison target data. When the data is arranged in ascending order, if the comparison target data is smaller, the comparison target data exists in the first half of the search target range, so the second time uses the first half as the search target range, that is, the first Data at a position ¼ of the search target range is read and compared with the comparison target data. On the other hand, if the comparison target data is larger, the comparison target data exists in the latter half of the search target range. Therefore, in the second time, the second half is set as the search target range, that is, 3/4 of the first search target range. The data at the position is read and compared with the comparison target data. In this way, the search target range is narrowed by half and finally reaches the target data.

  In this embodiment, since three comparison circuits for binary search are provided, when comparing the data at the half position of the search target range with the comparison target data for the first search. At the same time, the comparison target data is compared with the data at the 1/4 and 3/4 positions of the search target range for the second search. Thereby, since the search for 2 times can be performed at once, the time which reads data from a database can be shortened. Also, by operating the three comparison circuits in parallel at the same time, the number of comparisons can be reduced to half and the time required for the search can be shortened.

In the example of FIG. 12, three comparison circuits are provided in order to perform two searches simultaneously. In general, in order to perform n searches in parallel at the same time, 2 ⁿ −1 comparison circuits are provided. What is necessary is just to provide. The control circuit 36Z inputs data at positions of 1/2 ⁿ , 2/2 ⁿ ,..., (2 ⁿ −1) / 2 ^{n in} the search target range to each of the 2 ⁿ −1 comparison circuits. They are operated in parallel at the same time and compared with the data to be compared. The control circuit 36Z acquires the comparison results of the respective comparison circuits and determines whether comparison target data has been searched. If any of the comparison circuits outputs a signal indicating that the data match, the control circuit 36Z determines that the comparison target data has been searched and ends the binary search. If no match signal is output, the next search is performed. If the data to be compared exists in the database, it should exist in a range where the comparison results of 2 ⁿ −1 comparison circuits are inverted. For example, when 15 comparison circuits are provided, if the data at the 5/16 position is smaller than the comparison target data and the data at the 6/16 position is larger than the comparison target data, 5/16 to 6 / The comparison target data is in the range between 16. Therefore, the control circuit 36Z acquires the comparison results of the respective comparison circuits, determines the range in which the comparison results are inverted as the next search target range, ½ ^{n of} the determined next search target range, 2 ⁿ ,..., (2 ⁿ −1) / 2 ⁿ position data is input to each comparison circuit.

  In the present embodiment, three first databases 50 are provided, and the first database 50A is connected to the comparison circuit 36A and supplies data at a position of 1/4 of the search target range to the comparison circuit 36A. The second database 50B is connected to the comparison circuit 36B and supplies data at a position 2/4 of the search target range to the comparison circuit 36B, and the first database 50C is connected to the comparison circuit 36C and 3/4 of the search target range. The data at the position is supplied to the comparison circuit 36C. As a result, data can be simultaneously read out in parallel to the respective comparison circuits, so that the time required for reading data can be further shortened and the binary search can be speeded up.

  As the number of comparison circuits increases, the search speed improves. However, in consideration of cost, size, etc., a sufficient number of comparison circuits may be provided to obtain a desired search speed. Although it is preferable to provide as many first databases as the number of comparison circuits, in consideration of cost, size, etc., the databases may be shared by several comparison circuits.

  FIG. 13 shows still another example of internal data of the first database. The first database 50 shown in FIG. 13 stores URLs of contents to be filtered. The data stored in the first database 50 may include predetermined data recognized as a wild card, for example, “00H” or “01H”. In the example shown in FIG. 13, “http: //www.xx.xx/*********” is recognized as “*********” as a wild card and compared. In the devices 36a, 36b,..., It is determined that they match regardless of the comparison target data. Therefore, all the character strings starting with “http: //www.xx.xx/” are detected by the binary search circuit 36. Thereby, for example, it is possible to easily perform processing for filtering all the contents under the domain “http: //www.xx.xx/”.

  FIG. 14 shows an example of internal data of the second database. The second database 60 includes a search result column 62 for storing a search result by the search circuit 30 and a processing content column 64 for storing the content of processing to be executed on communication data, and corresponds the search result to the processing content. Hold it. In the example of FIG. 14, a condition is set in which when the reference data is included in the communication data, the packet is allowed to pass, and when the reference data is not included, the packet is discarded. The process execution circuit 40 searches the second database 60 for process contents based on the search result, and executes the process on the communication data. The processing execution circuit 40 may also be realized by a wired logic circuit.

  FIG. 15 shows another example of internal data of the second database. In the example of FIG. 15, the processing content is set for each reference data. When packet replacement is performed, replacement destination data may be stored in the second database 60. When packet routing or switching is performed, information on the route may be stored in the second database 60. The process execution circuit 40 executes processes such as filtering, routing, switching, and replacement stored in the second database 60 according to the search result by the search circuit 30. As shown in FIG. 15, when setting the processing content for each reference data, the first database 50 and the second database 60 may be integrated.

  FIG. 16 shows another configuration example of the binary search circuit. In the example illustrated in FIG. 16, 15 comparison circuits 36 </ b> A to 36 </ b> O are provided in order to execute four searches at a time. The control circuit 36Z simultaneously receives data at positions 1/16, 2/16,..., 15/16 of the search target range from the first database 50 connected to each of the 15 comparison circuits 36A to 36O. They are read out in parallel and input to the comparison circuits 36A to 36O. Further, the comparison target data x is input to each of the comparison circuits 36A to 36O.

  First, as a first step, the control circuit 36Z uses the three comparison circuits 36A, 36B, and 36C to which the data of the positions 4/16, 8/16, and 12/16 of the search target range are input, as the comparison target data. It is determined which x belongs to the range obtained by dividing the search target range into four. Subsequently, as the second stage, the comparison target data x is searched by three comparison circuits to which data at positions 1/4, 2/4, and 3/4 of the range determined in the first stage is input. It is determined which of the ranges obtained by dividing the target range into 16 pieces.

  The binary search circuit 36 receives data in the range determined in the first stage from the output signals indicating the comparison results of the first stage comparison circuits 36A, 36B, and 36C among the next second stage comparison circuits 36D to 36O. Is further provided with a negation circuit 37 and exclusive OR circuits 38A and 38B as a trigger circuit that generates a trigger signal that causes the comparison circuit to input the comparison to be input to the second-stage comparison circuits 36D to 36O. Yes. Here, the comparison circuits 36A to 36O output “1” when the comparison target data x is larger than the reference data, and output “0” when it is smaller.

  First, a trigger signal is input to the first stage comparison circuits 36A, 36B, and 36C, and the comparison is executed in parallel at the same time. If the output of the comparison circuit 36A is “0”, the comparison target data x belongs to the range of 0/16 to 4/16 of the search target range of the first database 50, and therefore the reference data of that range is input. The trigger signal “1” is input to the comparison circuits 36D, 36E, and 36F through the negative circuit 37. Thereby, only the comparison circuits 36D, 36E, and 36F to which the reference data at the positions 1/16, 2/16, and 3/16 of the search target range are input are activated among the comparison circuits 36D to 36O in the second stage. At the same time, the second stage comparison is performed in parallel. When the comparison target data x belongs to the range of 4/16 to 16/16 of the search target range, the output of the comparison circuit 36A becomes “1”, so that “0” is output from the negative circuit 37, A trigger signal is not input to the comparison circuits 36D, 36E, and 36F.

  If the output of the comparison circuit 36A is “1” and the output of the comparison circuit 36B is “0”, the comparison target data x belongs to the range of 4/16 to 8/16 of the search target range. The trigger signal “1” is input to the comparison circuits 36G, 36H, and 36I to which the reference data is input via the exclusive OR circuit 38A. Thereby, only the comparison circuits 36G, 36H, and 36I to which the reference data at the positions of 5/16, 6/16, and 7/16 of the search target range are input are activated among the comparison circuits 36D to 36O in the second stage. At the same time, the second stage comparison is performed in parallel. When the comparison target data x does not belong to the range of 4/16 to 8/16 of the search target range, the outputs of the comparison circuits 36A and 36B are the same, so that the exclusive OR circuit 38A receives “0”. Is output, and no trigger signal is input to 36G, 36H, and 36I.

  If the output of the comparison circuit 36B is “1” and the output of the comparison circuit 36C is “0”, the comparison target data x belongs to the range of 8/16 to 12/16 of the search target range. The trigger signal “1” is input to the comparison circuits 36J, 36K, and 36L to which the reference data is input via the exclusive OR circuit 38B. Thereby, only the comparison circuits 36J, 36K, and 36L to which the reference data of the positions 9/16, 10/16, and 11/16 of the search target range are input are activated among the comparison circuits 36D to 36O in the second stage. At the same time, the second stage comparison is performed in parallel. When the comparison target data x does not belong to the range of 8/16 to 12/16 of the search target range, the outputs of the comparison circuits 36B and 36C are the same, so that the exclusive OR circuit 38B receives “0”. Is output, and no trigger signal is input to 36J, 36K, and 36L.

  If the output of the comparison circuit 36C is “1”, the comparison target data x belongs to the range of 12/16 to 16/16 of the search target range, and therefore the comparison circuit 36M to which the reference data of that range is input. , 36N, 36O, the output signal of the comparison circuit 36C is input as the trigger signal “1”. Thereby, only the comparison circuits 36M, 36N, and 36O to which the reference data of the positions 13/16, 14/16, and 15/16 of the search target range are input among the second-stage comparison circuits 36D to 36O are activated. At the same time, the second stage comparison is performed in parallel. When the comparison target data x belongs to the range of 0/16 to 12/16 of the search target range, the output of the comparison circuit 36C becomes “0”, so that a trigger signal is input to 36M, 36N, and 36O. Not.

  In this way, in the example shown in FIG. 16, four searches can be executed by a two-stage comparison process. When the comparison target data x is not searched in the four searches, the control circuit 36Z newly sets 1/16, 2/16,..., 15/16 of the range determined in the second stage. Is input to each of the 15 comparison circuits 36A to 36O, and the next four searches are executed.

  In this way, the comparison circuit for performing the search for n times is hierarchized into a plurality of stages, and after the second stage, only the comparison circuits in the range determined up to the previous stage are operated, thereby reducing power consumption. Can be made.

In the example of FIG. 16, 15 comparison circuits are provided to perform four searches simultaneously, but in general, 2 ⁿ −1 comparison circuits are used to perform n searches simultaneously. May be provided. Control circuit 36Z is, when dividing a search range of the first database 50 to ^{the 2 n,} the compared data x, ^{1/2 n,} 2/2 n the search range, · · ·, ^{(2 n} - 1) / ² and ⁿ of the location of the ^data, it is input to each of the ² n -1 comparison circuits. First, as a first stage, 2 ⁿ¹ −1 comparison circuits to which data at positions of 1/2 ⁿ¹ , ^{2/2 n1} ,..., (2 ⁿ¹ −1) / 2 ⁿ¹ of the search target range are input. Thus, it is determined whether the comparison target data x belongs to a range obtained by dividing the search target range into 2 ⁿ¹ pieces. Subsequently, as the second step, ^{1/2 n2,} 2/2 n2 ranges determined in the first ^{stage, ···, (2 n2 -1)} / 2 2 data of the position is input ^{n2 n2} It is determined by the one comparison circuit whether the comparison target data x belongs to the range obtained by dividing the search target range into 2 ^{n1 + n2} . In the same manner, n times of searches are executed by repeating until the Nth stage (where n1 + n2 +... + NN = n). If the comparison target data x is not searched in the n searches, a new value of 1/2 ⁿ , 2/2 ⁿ ,..., (2 ⁿ −1) / Data of 2 ⁿ positions are input to each of 2 ⁿ −1 comparison circuits, and the next n searches are executed.

In this case, the trigger circuit has an output signal indicating the comparison result of the m-th (1 ≦ m <N) -stage comparison circuit, within the range determined in the m-th stage among the next (m + 1) -th comparison circuits. A trigger signal that causes the comparison circuit to which data is input to perform comparison is generated and input to the (m + 1) th comparison circuit. Specifically, among the 2 ^m -1 comparison circuits in the m-th stage, when an output signal indicating a different comparison result is output from an adjacent comparison circuit, the data input to the comparison circuits The trigger signal may be input to the (m + 1) -th stage comparison circuit to which data in the range between them is input. In addition, in the (m + 1) -th stage comparison circuit to which the data of the minimum range and the maximum range among the 2 ^m ranges determined in the m-th stage are input, 2 ^m −1 pieces in the m-th stage are included. Of these comparison circuits, a trigger signal may be input according to the comparison result of the comparison circuit to which the minimum and maximum reference data are input.

  FIG. 17 shows still another configuration example of the binary search circuit. In the example shown in FIG. 17, the binary search circuit 36 uses three comparison circuits 36 </ b> A to 36 </ b> C to which of the ranges obtained by dividing the comparison target data x into four search target ranges of the first database 50. However, in the example of FIG. 17, four comparison circuits 36 </ b> P to 36 </ b> S are provided for determining whether or not the comparison target data x is included in each of the four ranges. For example, the reference data at the position 0/16 of the search target range of the first database 50, the reference data at the position 4/16, and the comparison target data x are input to the comparison circuit 36P. By comparing the reference data and the comparison target data x, it is determined whether or not the reference data is included in the range of 0/16 to 4/16 of the search target range. When included in the range, the trigger signal is input from the comparison circuit 36P to the comparison circuits 36D, 36E, and 36F to which the data included in the range is input as reference data. Thereby, in the second stage, only the comparison circuit in the range determined in the first stage performs the comparison, so that the power consumption can be reduced.

In the example shown in FIG. 16 and FIG. 17, out of 2 ⁿ −1 comparison circuits for performing n searches at a time, 1/2 ⁿ¹ , ^{2/2 n1,. n1} -1) / 2 The 2 ⁿ¹ -1 comparison circuits to which the data at the position ⁿ¹ are input are the first-stage comparison circuits. However, the present invention is not limited to this, and the comparison circuit to which data at an arbitrary position is input May be a first-stage comparison circuit. In short, a plurality of comparison circuits may be hierarchized so that only the comparison circuits in the range determined up to the previous stage are operated.

  The first database and the second database are rewritable from the outside. By exchanging these databases, various data processing and communication control can be realized using the same communication control device 10. In addition, two or more databases storing reference data to be searched may be provided to perform multi-stage search processing. At this time, two or more databases that store search results and processing contents in association with each other may be provided to realize more complicated conditional branching. As described above, when a plurality of databases are provided to perform multi-stage search, a plurality of position detection circuits 32, index circuits 34, binary search circuits 36, etc. may be provided.

  The data used for the comparison described above may be compressed by the same compression logic. In comparison, if the comparison source data and the comparison destination data are compressed by the same method, the same comparison as usual is possible. As a result, the amount of data loaded at the time of comparison can be reduced. If the amount of data to be loaded is reduced, the time required to read data from the memory is reduced, so that the overall processing time can also be reduced. Further, since the amount of the comparator can be reduced, it is possible to contribute to downsizing, weight reduction, and cost reduction of the apparatus. The data used for the comparison may be stored in a compressed form, or may be compressed after being read from the memory and before the comparison.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. is there.

  The present invention can be used in a binary search circuit that searches data from a database.

Claims (6)

A circuit for searching comparison target data by a binary search from a database storing data arranged in ascending or descending order,
2 ⁿ −1 comparison circuits for comparing the data read from the database with the comparison target data;
A control circuit for controlling the comparison circuit,
When the search target range of the database is divided into 2 ⁿ pieces, the control circuit divides the comparison target data and 1/2 ^{n of the} search target range, 2/2 ⁿ , ..., (2 ⁿ -1 ) / 2 ⁿ position data is input to each of the 2 ⁿ −1 comparison circuits,
First, as a first stage, 2 ⁿ¹ −1 comparisons in which data at positions of 1/2 ⁿ¹ , ^{2/2 n1} ,..., (2 ⁿ¹ −1) / 2 ⁿ¹ of the search target range are input. A circuit determines whether the comparison target data belongs to a range obtained by dividing the search target range into 2 ⁿ¹ pieces. Subsequently, as a second step, 1 / of the range determined in the first step is determined. 2 ⁿ² , ^{2/2 n2} ,..., (2 ⁿ² −1) / 2 The data of the comparison target data is converted into the search target range by 2 ⁿ² −1 comparison circuits to which data at the position of ⁿ² is input. 2 It is determined which of the range divided into ^{n1 + n2} belongs, and thereafter, in the same manner, by repeating to the Nth stage (where n1 + n2 +... + NN = n), n times of searches are performed,
If the comparison target data is not searched in the n searches, a new range of 1/2 ⁿ , 2/2 ⁿ ,..., (2 ⁿ −1) ) / 2 A binary search circuit characterized in that data at position ⁿ is input to each of the 2 ⁿ −1 comparison circuits and the next n searches are executed.   From the output signal indicating the comparison result of the mth (1 ≦ m <N) stage comparison circuit, the data in the range determined in the mth stage among the next (m + 1) th stage comparison circuits is input. The binary search circuit according to claim 1, further comprising a trigger circuit that generates a trigger signal for causing the comparison circuit to perform comparison and inputs the trigger signal to the (m + 1) -th stage comparison circuit. When the output signal indicating a different comparison result is output from an adjacent comparison circuit among the 2 ^m −1 comparison circuits in the m-th stage, the trigger circuit is configured to store the data input to the comparison circuits. 3. The binary search circuit according to claim 2, wherein the trigger signal is input to a (m + 1) -th stage comparison circuit to which data in a range between them is input. 4. The binary search circuit according to claim 1, wherein in the m-th (1 ≦ m <N) stage, 2 ^m −1 comparison circuits simultaneously perform comparison in parallel. Comprising 2 ⁿ -1 databases connected to each of the comparison circuits;
Wherein the control ^{circuit, 1/2} n, 2/2 n of said search range, ^..., parallel data of the position of the ^{(2 n -1) / 2 n} , from a database that is connected to the comparison circuits 5. The binary search circuit according to claim 1, wherein the binary search circuit is inputted. When dividing a search range of the database that stores the data aligned in ascending or descending order 2 ⁿ pieces, the compared data, 1/2 n, ^2/2 n of said search range, ^..., ( 2 ⁿ −1) / 2 ⁿ position data is input to each of 2 ⁿ −1 comparison circuits;
As a first stage, 2 ⁿ¹ −1 comparator circuits to which data at positions of 1/2 ⁿ¹ , ^{2/2 n1} ,..., (2 ⁿ¹ −1) / 2 ⁿ¹ of the search target range are input. Determining whether the comparison target data belongs to a range obtained by dividing the search target range into 2 ⁿ¹ pieces;
As a second step, the ^1/2 n2 of the determined range in the first ^{step, 2/2 n2, ···,} (2 n2 -1) / 2 n2 position data is input ² n2 -1 Determining whether the comparison target data belongs to a range obtained by dividing the search target range into 2 ^{n1 + n2} pieces by a plurality of comparison circuits;
Thereafter, in the same manner, a step of executing n searches by repeating up to the Nth stage (where n1 + n2 +... + NN = n),
If the comparison target data is not searched in the n searches, a new range of 1/2 ⁿ , 2/2 ⁿ ,..., (2 ⁿ −1) ) / a 2 ⁿ data location, is input to each of the 2 ⁿ -1 comparison circuits, performing a search for the next n times,
A binary search method comprising:

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