JPWO2008153065A1 - Semiconductor light emitting device and manufacturing method thereof - Google Patents

Abstract

Luminous efficiency can be improved by optimizing the number of pairs of active quantum multiple quantum well (MQW) layers for efficient recombination of electrons and holes in the active layer.
The n-type semiconductor layer 2, the p-type semiconductor layer 4, the barrier layers 311 to 31n, 310 made of GaN, and In _x Ga _1-x N are arranged between the n-type semiconductor layer 2 and the p-type semiconductor layer 4. And an active layer 3 containing In having a multiple quantum well structure with well layers 321 to 32n made of (0 <x <1), the number of pairs of MQW layers is 6 to 11, and from the n-type semiconductor layer 2 Electron overflow to the p-type semiconductor layer 4, diffusion of the p-type dopant from the p-type semiconductor layer 4 to the well layers 321 to 32 n, and diffusion of the n-type dopant from the n-type semiconductor layer 2 to the active layer 3 can be suppressed. Semiconductor light emitting device and manufacturing method thereof.

Description

  The present invention relates to a semiconductor light emitting device and a manufacturing method thereof, and more particularly to a semiconductor light emitting device including a quantum well structure and an n-type semiconductor layer doped with an n-type dopant and a manufacturing method thereof.

A semiconductor light emitting element made of a group III nitride semiconductor is used for a light emitting diode (LED). Examples of group III nitride semiconductors include aluminum nitride (AlN), gallium nitride (GaN), and indium nitride (InN). A typical group III nitride semiconductor is represented by Al _x In _y Ga _1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1).

  A semiconductor light emitting device using a group III nitride semiconductor includes, for example, an n-type group III nitride semiconductor layer (n-type semiconductor layer), an active layer (light-emitting layer), and a p-type group III nitride on a substrate. It has a structure in which a series semiconductor layer (p-type semiconductor layer) is laminated in this order. Then, light generated by recombination of holes supplied from the p-type semiconductor layer and electrons supplied from the n-type semiconductor layer in the active layer is output to the outside (see, for example, Patent Document 1). .

  As the active layer, a multi-quantum well (MQW) structure in which a plurality of well layers (well layers) are sandwiched between barrier layers (barrier layers) having a larger band gap than the well layers can be employed. (For example, refer to Patent Document 2).

In addition, examples in which the p-type semiconductor layer is formed in a two-layer structure or a three-layer structure for the purpose of reducing the forward voltage (Vf) and improving the light emission efficiency are also disclosed (for example, Patent Document 3 and Patent). Reference 4).
Japanese Patent Laid-Open No. 10-284802 JP 2004-55719 A Japanese Patent No. 3250438 Japanese Patent No. 331466

  In the conventional structure, 4 to 5 pairs of MQW are used. In this case, electrons supplied from the n-type semiconductor layer jump over the active layer and flow to the p-type semiconductor layer. At this time, holes supplied from the p-type semiconductor layer recombine with electrons before reaching the active layer, and the hole concentration reaching the active layer is reduced. Thereby, the brightness | luminance of LED will reduce. In order to prevent this, a structure in which a p-type AlGaN layer having a large band gap is inserted in front of the p-type semiconductor layer is used. However, when aluminum (Al) is introduced, it becomes difficult to form p-type, and the resistance value increases.

  In the semiconductor light emitting device using the group III nitride semiconductor, the p-type dopant doped in the p-type semiconductor layer disposed on the active layer is formed during the p-type semiconductor layer forming step and the subsequent manufacturing steps. Diffusion from the p-type semiconductor layer to the active layer. When the p-type dopant diffused in the active layer reaches the well layer, there is a problem that the brightness of light generated in the active layer is lowered and the quality of the semiconductor light emitting device is deteriorated.

  In the semiconductor light emitting device in which the active layer is directly disposed on the n-type semiconductor layer, electrons supplied from the n-type semiconductor layer to the active layer reach the p-type semiconductor layer disposed immediately above the active layer, and the p-type There is a case where a phenomenon of recombination with holes in the semiconductor layer (hereinafter referred to as “electron overflow”) occurs. In that case, since light emission by recombination in the p-type semiconductor layer is inefficient, there is a problem that the luminance of light output from the semiconductor light emitting element is lowered and the quality of the semiconductor light emitting element is deteriorated. Further, in the manufacturing process of the semiconductor light emitting device, there has been a problem that the n-type dopant doped in the n-type semiconductor layer diffuses into the active layer and the luminance of the output light is lowered.

  In view of the above problems, the present invention optimizes the number of MQW pairs in the active layer for efficiently recombining electrons supplied from the n-type semiconductor layer and holes supplied from the p-type semiconductor layer in the active layer. A semiconductor light emitting device with improved luminous efficiency is provided.

  The present invention provides a semiconductor light emitting device capable of suppressing diffusion of a p-type dopant from a p-type semiconductor layer to a well layer, and a method for manufacturing the same.

  The present invention provides a semiconductor light emitting device capable of suppressing the overflow of electrons from an n-type semiconductor layer to a p-type semiconductor layer and the diffusion of an n-type dopant from the n-type semiconductor layer to the active layer.

According to one aspect of the present invention for achieving the above object, an n-type nitride semiconductor layer, a p-type nitride semiconductor layer, the n-type nitride semiconductor layer, and the p-type nitride semiconductor An active layer containing In having a multiple quantum well structure of a barrier layer made of GaN and a well layer made of In _x Ga _1-x N (0 <x <1). A semiconductor light emitting device that is a semiconductor light emitting device having 6 to 11 pairs of quantum well layers is provided.

According to another aspect of the present invention, an n-type semiconductor layer and an active layer having a stacked structure in which a barrier layer and a well layer having a smaller band gap than that of the barrier layer are alternately arranged on the n-type semiconductor layer. And a p-type semiconductor layer including a p-type dopant disposed on the active layer, and the film thickness of the final barrier layer of the uppermost layer of the stacked structure of the active layer is greater than the distance by which the final barrier layer of the p-type dopant is diffused The thickness of the p-type dopant in the final barrier layer is gradually decreased from the first main surface of the final barrier layer in contact with the p-type semiconductor layer along the film thickness direction of the final barrier layer, and is opposed to the first main surface. A semiconductor light emitting device having a p-type dopant concentration of less than 1 × 10 ¹⁶ cm ^{−3 on the} surface is provided.

  According to another aspect of the invention, an n-type semiconductor layer doped with an n-type dopant, a block layer disposed on the n-type semiconductor layer and doped with an n-type dopant at a lower concentration than the n-type semiconductor layer, There is provided a semiconductor light emitting device comprising an active layer disposed on a block layer and a p-type semiconductor layer disposed on the active layer.

  According to another aspect of the present invention, an active layer is formed by alternately stacking a barrier layer and a well layer having a smaller band gap than the barrier layer on the n-type semiconductor layer, and forming an n-type semiconductor layer. And a step of forming a p-type semiconductor layer including a p-type dopant on the active layer, and diffusing the final barrier layer of the active layer in contact with the p-type semiconductor layer into the final barrier layer of the p-type dopant. A method for manufacturing a semiconductor light emitting device having a larger thickness is provided.

  According to the semiconductor light emitting device of the present invention, the number of MQW pairs in the active layer for efficiently recombining electrons supplied from the n-type semiconductor layer and holes supplied from the p-type semiconductor layer in the active layer is optimized. , Luminous efficiency can be improved.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor light-emitting device which can suppress the spreading | diffusion of the p-type dopant from a p-type semiconductor layer to a well layer, and its manufacturing method can be provided.

  ADVANTAGE OF THE INVENTION According to this invention, the semiconductor light-emitting device which can suppress the overflow of the electron from an n-type semiconductor layer to a p-type semiconductor layer and the spreading | diffusion of the n-type dopant from an n-type semiconductor layer to an active layer can be provided.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional structure diagram of a semiconductor light emitting device according to a first embodiment of the present invention, where (a) a schematic cross-sectional structure diagram of a semiconductor light emitting device portion, and (b) an enlarged schematic view of an active layer portion. FIG. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional structure diagram of a semiconductor light-emitting device according to a modification of the first embodiment of the present invention, where (a) a schematic cross-sectional structure diagram of a semiconductor light-emitting device portion and (b) an enlarged active layer portion. FIG. 1 is a schematic cross-sectional structure diagram formed up to a p-side electrode and an n-side electrode of a semiconductor light emitting element according to a first embodiment of the present invention. The figure which shows the relationship between the light emission output and the number of quantum well pairs in the semiconductor light-emitting device concerning the 1st Embodiment of this invention. FIG. 3 is a schematic diagram of a band structure for explaining a light emission phenomenon in the MQW layer in the semiconductor light emitting device according to the first embodiment of the present invention. In the semiconductor light emitting device according to the first embodiment of the present invention, the band structure for explaining the light emission phenomenon in the MQW layer, (a) a schematic diagram of the band structure when the MQW layer is 5 pairs, (b) ) A schematic diagram of a band structure when the MQW layer is 8 pairs, and (c) a schematic diagram of a band structure when the MQW layer is 12 pairs. (A) The figure explaining temperature distribution at the time of forming the p-type semiconductor layer (41-44) of a four-layer structure in the semiconductor light-emitting device concerning the 1st Embodiment of this invention, (b) Hydrogen gas flow (C) The figure explaining another condition of hydrogen gas flow, (d) The figure explaining still another condition of hydrogen gas flow, (e) The further another condition of hydrogen gas flow Illustration to explain. (A) The figure explaining the temperature distribution at the time of forming the p-type semiconductor layer (41-44) of a four-layer structure in the semiconductor light-emitting device concerning the 1st Embodiment of this invention, (b) Nitrogen gas flow The figure explaining the conditions of (c) The figure explaining the conditions of ammonia gas flow. The schematic diagram which shows the structural example of the semiconductor light-emitting device which concerns on the 2nd Embodiment of this invention. The graph which shows the example of p-type dopant density | concentration distribution in the last barrier layer of the semiconductor light-emitting device concerning the 2nd Embodiment of this invention. (A) It is an example of the last barrier layer and p-type semiconductor layer of the semiconductor light-emitting device concerning the 2nd Embodiment of this invention, The structural drawing of a p-type semiconductor layer, (b) Mg concentration distribution of a p-type semiconductor layer FIG. The graph which shows the relationship between the film thickness of the last barrier layer of the semiconductor light-emitting device concerning the 2nd Embodiment of this invention, and light emission output. The figure which shows the gas flow pattern in the crystal growth of the active layer of the semiconductor light-emitting device concerning the 2nd Embodiment of this invention. The schematic diagram which shows the structural example of the semiconductor light-emitting device concerning the 3rd Embodiment of this invention. The schematic diagram which shows the structural example of the active layer of the semiconductor light-emitting device concerning the 3rd Embodiment of this invention. The graph which shows the relationship between Si density | concentration of the block layer of the semiconductor light-emitting device concerning the 3rd Embodiment of this invention, and light emission output. The figure which shows the gas flow pattern in the crystal growth of the active layer of the semiconductor light-emitting device concerning the 3rd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... N-type semiconductor layer 3 ... Active layer 4 ... P-type semiconductor layer 5 ... Oxide electrode 6 ... Buffer layer 7 ... Block layer 31 ... Barrier layer (GaN layer)
32 ... Well layer (InGaN layer)
41 ... first nitride semiconductor layer 42 ... second nitride semiconductor layer 43 ... third nitride semiconductor layer 44 ... fourth nitride semiconductor layer 100 ... p-side electrode 200 ... n-side electrode 310 ... final barrier Layers 311-31n ... Barrier layers 321-32n ... Well layers

  Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic and different from the actual ones. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  Further, the embodiment described below exemplifies an apparatus and a method for embodying the embodiment of the present invention. In the embodiment of the present invention, the arrangement of each component is described below. It is not something specific. Various modifications can be made to the embodiment of the present invention within the scope of the claims.

[First embodiment]
A schematic cross-sectional structure of the semiconductor light emitting device according to the first embodiment of the present invention is expressed as shown in FIG. The enlarged schematic cross-sectional structure of the active layer portion is expressed as shown in FIG.

  As shown in FIG. 1, the semiconductor light emitting device according to the first embodiment includes a substrate 1, a buffer layer 6 disposed on the substrate 1, a buffer layer 6, and an n-type impurity added as an impurity. N-type semiconductor layer 2, a block layer 7 disposed on n-type semiconductor layer 2 and doped with n-type impurities at a lower concentration than n-type semiconductor layer 2, and an activity disposed on block layer 7 A layer 3, a p-type semiconductor layer 4 disposed on the active layer 3, and an oxide electrode 5 disposed on the p-type semiconductor layer 4 are provided.

  As shown in FIG. 1B, the active layer 3 has a laminated structure in which barrier layers 311 to 31n and 310 and well layers 321 to 32n having a smaller band gap than the barrier layers 311 to 31n and 310 are alternately arranged. Have. Hereinafter, the first barrier layer 311 to the nth barrier layer 31n included in the active layer 3 are collectively referred to as “barrier layer 31”. Further, all well layers included in the active layer 3 are collectively referred to as “well layers 32”.

  The film thickness of the final barrier layer 310 in the uppermost layer of the stacked structure is larger than the thicknesses of the other barrier layers (the first barrier layer 311 to the nth barrier layer 31n) included in the stacked structure other than the final barrier layer 310. It may be formed.

  In the semiconductor light emitting device shown in FIG. 1, the concentration of the p-type dopant in the final barrier layer 310 extends from the first main surface of the final barrier layer 310 in contact with the p-type semiconductor layer 4 along the film thickness direction of the final barrier layer 310. There is no p-type dopant on the second main surface that gradually decreases and faces the first main surface.

  As the substrate 1, for example, a c-plane (0001), 0.25 ° off sapphire substrate can be employed. The n-type semiconductor layer 2, the active layer 3, and the p-type semiconductor layer 4 are each made of a group III nitride semiconductor, and the buffer layer 6, the n-type semiconductor layer 2, the block layer 7, the active layer 3, and the p-type are formed on the substrate 1. Semiconductor layers 4 are sequentially stacked.

(Buffer layer)
The buffer layer 6 is formed of, for example, an AlN layer having a thickness of about 10 to 50 angstroms. When the AlN buffer layer 6 is crystal-grown, for example, it is grown at a high temperature in a temperature range of about 900 ° C. to 950 ° C. By supplying trimethylaluminum (TMA) used as an Al raw material for the AlN buffer layer 6 and ammonia (NH ₃ ) used as an N raw material to the reaction chamber alternately using H ₂ gas as a carrier, an AlN buffer is obtained. Layer 6 is crystal grown. For example, the number of cycles may be about 3-5.

By supplying trimethylaluminum (TMA) and ammonia (NH ₃ ) to the reaction chamber alternately with H ₂ gas as a carrier, a thin AlN buffer layer 6 having a thickness of about 10 to 30 Å is formed. It can be grown at high speed, and can be formed while maintaining good crystallinity.

  According to the semiconductor light emitting device according to the first embodiment, the crystallinity and surface morphology of the group III nitride semiconductor formed on the high temperature AlN buffer layer can be improved.

(Block layer)
The block layer 7 disposed between the n-type semiconductor layer 2 and the active layer 3 is a group III nitride semiconductor having a thickness of about 200 nm, for example, doped with Si as an n-type impurity at less than 1 × 10 ¹⁷ cm ^−3. For example, a GaN layer can be employed.

In the semiconductor light emitting device shown in FIG. 1, for example, when Si is doped with about 3 × 10 ¹⁸ cm ^{−3 in the} n-type semiconductor layer 2, a block in which Si is doped with about 8 × 10 ¹⁶ cm ^−3. By disposing the layer 7 between the n-type semiconductor layer 2 and the active layer 3, it is possible to prevent diffusion of Si from the n-type semiconductor layer 2 to the active layer 3 in the process of forming the active layer 3 and the manufacturing process after that process. .

  That is, Si does not diffuse into the active layer 3 and a reduction in the luminance of light generated in the active layer 3 is prevented. Furthermore, when a bias is applied between the n-type semiconductor layer 2 and the p-type semiconductor layer 4 to cause the active layer 3 to emit light, electrons supplied from the n-type semiconductor layer 2 to the active layer 3 cause the active layer 3 to An overflow that passes through and reaches the p-type semiconductor layer 4 can be prevented, and a decrease in luminance of light output from the semiconductor light emitting element can be prevented.

The Si concentration of the block layer 7 is less than 1 × 10 ¹⁷ cm ⁻³ . This is because, when the Si concentration of the block layer 7 is too high, electrons supplied from the n-type semiconductor layer 2 overflow the active layer 3 to the p-type semiconductor layer 4, and the holes in the p-type semiconductor layer 4 This is because recombination occurs, the recombination rate in the active layer 3 decreases, and the luminance of light generated in the active layer 3 decreases. On the other hand, when the Si concentration of the block layer 7 is too low, the carrier density of electrons injected from the n-type semiconductor layer 2 into the active layer 3 cannot be increased. Therefore, the Si concentration of the block layer 7 is preferably about 5 × 10 ¹⁶ to less than 1 × 10 ¹⁷ cm ⁻³ .

  As described above, in the semiconductor light emitting device according to the first embodiment, the block layer 7 is disposed between the n-type semiconductor layer 2 and the active layer 3, thereby allowing the n-type semiconductor layer 2 during the manufacturing process. Diffusion of Si from the active layer 3 to the active layer 3 and overflow of electrons from the n-type semiconductor layer 2 to the p-type semiconductor layer 4 at the time of light emission can be prevented, and the luminance of light output from the semiconductor light-emitting element can be reduced. Can be prevented. As a result, deterioration of the quality of the semiconductor light emitting device shown in FIG. 1 can be prevented.

(N-type semiconductor layer)
The n-type semiconductor layer 2 supplies electrons to the active layer 3, and the p-type semiconductor layer 4 supplies holes to the active layer 3. Light is generated by the recombination of the supplied electrons and holes in the active layer 3.

  The n-type semiconductor layer 2 may be a group III nitride semiconductor having a thickness of about 1 to 6 μm doped with an n-type impurity such as silicon (Si), for example, a GaN layer.

(P-type semiconductor layer)
As the p-type semiconductor layer 4, a group III nitride semiconductor having a thickness of about 0.2 to 1 μm doped with a p-type impurity, such as a GaN layer, can be employed. As the p-type impurity, magnesium (Mg), zinc (Zn), cadmium (Cd), calcium (Ca), beryllium (Be), carbon (C), or the like can be used.

  A configuration example of the p-type semiconductor layer 4 is as follows in more detail. That is, as shown in FIG. 1A, the p-type semiconductor layer 4 is disposed on the active layer 3, and includes a first nitride-based semiconductor layer 41 containing a p-type impurity, and a first nitride-based semiconductor layer. 41, a second nitride-based semiconductor layer 42 containing a p-type impurity at a lower concentration than the p-type impurity of the first nitride-based semiconductor layer 41, and a second nitride-based semiconductor layer 42. , A third nitride-based semiconductor layer 43 containing a p-type impurity having a higher concentration than the p-type impurity of the second nitride-based semiconductor layer 42, and the third nitride-based semiconductor layer 43 disposed on the third nitride-based semiconductor layer 43. And a fourth nitride semiconductor layer 44 containing a p-type impurity having a lower concentration than the p-type impurity of the system semiconductor layer 43.

  The thickness of the second nitride-based semiconductor layer 42 is formed to be greater than the thickness of the first nitride-based semiconductor layer 41 or the third nitride-based semiconductor layer 43 to the fourth nitride-based semiconductor layer 44.

Here, the material and thickness of each layer will be specifically described. The first nitride-based semiconductor layer 41 including p-type impurities disposed on the active layer 3 is, for example, a p-type GaN layer of about 2 × 10 ²⁰ cm ⁻³ doped with Mg and having a thickness of about 50 nm. Formed with.

The second nitride semiconductor layer 42 disposed on the first nitride semiconductor layer 41 and containing a p-type impurity having a lower concentration than the p-type impurity of the first nitride semiconductor layer 41 is doped with, for example, Mg. The p-type GaN layer is about 4 × 10 ¹⁹ cm ⁻³ and about 100 nm thick.

The third nitride-based semiconductor layer 43 disposed on the second nitride-based semiconductor layer 42 and containing a p-type impurity having a higher concentration than the p-type impurity of the second nitride-based semiconductor layer 42 is doped with, for example, Mg. The p-type GaN layer is about 1 × 10 ²⁰ cm ⁻³ and about 40 nm thick.

The fourth nitride semiconductor layer 44 disposed on the third nitride semiconductor layer 43 and containing a p-type impurity having a lower concentration than the p-type impurity of the third nitride semiconductor layer 43 is doped with, for example, Mg. The p-type GaN layer is about 8 × 10 ¹⁹ cm ⁻³ and about 10 nm thick.

  In the semiconductor light emitting device according to the first embodiment, the p-type semiconductor layer 4 formed on the active layer 3 made of a multiple quantum well containing indium has a four-layer structure with different Mg concentrations as described above. It consists of a p-type GaN layer and is doped at the above concentration. The p-type GaN layer is grown at a low temperature of about 800 ° C. to 900 ° C. in order to reduce thermal damage to the active layer 3.

  The first nitride semiconductor layer 41 closest to the active layer 3 has a higher emission intensity as the Mg concentration is higher. Therefore, the higher the Mg concentration, the better.

The second nitride-based semiconductor layer 42 has a Mg concentration of about 10 ¹⁹ cm ⁻³ because the crystal defects due to Mg increase and the resistance of the film increases when Mg is excessively doped. It is desirable.

  Since the third nitride semiconductor layer 43 is a layer that determines the amount of holes injected into the active layer 3, it is desirable that the Mg concentration be slightly higher than that of the second nitride semiconductor layer 42.

The fourth nitride-based semiconductor layer 44 is a p-type GaN layer for making ohmic contact with the oxide electrode 5 and is substantially depleted. For example, when a ZnO electrode doped with about 1 × 10 ^{19 to} 5 × 10 ²¹ cm ^{−3 of} Ga or Al is used as the oxide electrode 5, the Mg when the forward voltage Vf of the semiconductor light emitting element is lowered most Mg is added to the fourth nitride-based semiconductor layer 44 so as to have a concentration.

When four p-type GaN layers are grown, the third nitride semiconductor layer 43 and the fourth nitride semiconductor layer 44 close to the p-side electrode 100 need to increase the hole concentration in the film. Increase the amount of H ₂ gas in the carrier gas. Further, the first nitride semiconductor layer 41 and the second nitride semiconductor layer 42 close to the active layer 3 do not need to increase the amount of H2 gas in the carrier gas, and the active layer 3 is grown with the N2 carrier gas. The crystal grows with its extension. When these p-type GaN layers are grown, a film having a lower resistance can be grown by increasing the V / III ratio as much as possible, and the forward voltage (Vf) of the light emitting element can be lowered.

  According to the semiconductor light emitting device according to the first embodiment, the p-type semiconductor layer is formed at a low temperature to reduce the thermal damage to the active layer, and the forward voltage (Vf) is reduced to improve the light emission efficiency. Can be made.

(Active layer)
As shown in FIG. 1B, the active layer 3 includes a first well layer 321 to an nth well layer 32n sandwiched between a first barrier layer 311 to an nth barrier layer 31n and a final barrier layer 310, respectively. It is a quantum well (MQW) structure (n: natural number). That is, the active layer 3 has a quantum well structure in which the well layer 32 is sandwiched between the barrier layers 31 having a larger band gap than the well layer 32 in a unit pair structure, and this unit pair structure is stacked n times. Have

  Specifically, the first well layer 321 is disposed between the first barrier layer 311 and the second barrier layer 312, and the second well layer 322 is disposed between the second barrier layer 312 and the third barrier layer 313. The The nth well layer 32n is disposed between the nth barrier layer 31n and the final barrier layer 310. The first barrier layer 311 of the active layer 3 is disposed on the n-type semiconductor layer 2 via the buffer layer 6, and the p-type semiconductor layer 4 (41 to 44) is disposed on the final barrier layer 310 of the active layer 3. Is done.

The well layers 321 to 32n are formed by, for example, In _x Ga _1-x N (0 <x <1) layers, and the barrier layers 311 to 31n and 310 are formed by, for example, GaN layers. Moreover, the number of pairs of multiple quantum well layers is, for example, 6 to 11. The ratio of indium (In) to gallium (Ga) in the well layers 321 to 32n {x / (1-x)} is appropriately set according to the wavelength of light to be generated.

  Further, the thickness of the well layers 321 to 32n is, for example, about 2 to 3 nm, preferably about 2.8 nm, and the thickness of the barrier layers 311 to 31n is about 7 to 18 nm, preferably about It is about 16.5 nm.

  FIG. 4 shows the relationship between the light emission output and the number of quantum well pairs in the semiconductor light emitting device according to the first embodiment.

  FIG. 5 is a schematic diagram of a band structure for explaining the light emission phenomenon in the active layer 3 in the semiconductor light emitting device according to the first embodiment.

  FIG. 6 shows a band structure for explaining the light emission phenomenon in the active layer 3 in the semiconductor light emitting device according to the first embodiment. FIG. 6A shows the band structure when MQW is 5 pairs. FIG. 6B is a schematic diagram, and FIG. 6B is a schematic diagram of a band structure when MQW is 8 pairs. FIG. 6C is a schematic diagram of a band structure when MQW is 12 pairs.

  In the conventional structure, since 4 to 5 MQW pairs are used, as shown in FIG. 6A, electrons supplied from the n-type semiconductor layer 2 jump over the active layer 3 and become p-type. It flows to the semiconductor layer 4. At this time, holes supplied from the p-type semiconductor layer 4 are recombined with electrons before reaching the active layer 3, and the hole concentration reaching the active layer 3 decreases. Thereby, the brightness | luminance of LED will reduce. This is because the effective mass of holes is higher than that of electrons, so the mobility of injected holes from the p-type semiconductor layer 4 is low, and electrons reach the p-type semiconductor layer 4 before the holes reach the active layer 3. This is because they recombine with holes.

  On the other hand, when the number of MQW pairs is larger than 12 pairs, as shown in FIG. 6C, the active layer 3 is thick, so that the electrons supplied from the n-type semiconductor layer 2 are within the active layer 3. Can not drive enough. At this time, the holes supplied from the p-type semiconductor layer 4 cannot sufficiently travel in the active layer 3. For this reason, electrons and holes are not sufficiently recombined in the active layer 3, thereby reducing the luminance of the LED.

  On the other hand, when the number of MQW pairs is about 8 pairs, the thickness of the active layer 3 is optimized and supplied from the n-type semiconductor layer 2 as shown in FIGS. The electrons that are generated travel sufficiently in the active layer 3, and at the same time, the holes supplied from the p-type semiconductor layer 4 can also travel sufficiently in the active layer 3. And hole recombination occur sufficiently, thereby increasing the brightness of the LED.

  In a case where a sufficient injection amount of holes from the p-type semiconductor layer 4 to the active layer 3 is secured and a sufficient injection amount of electrons from the n-type semiconductor layer 2 to the active layer 3 is secured. The MQW in the active layer 3 contributing to the light emission phenomenon may be 2 to 3 pairs counted from the p-type semiconductor layer 4. Since the electron mobility is higher than the hole mobility, the MQW in the active layer 3 contributing to the light emission phenomenon is several pairs close to the p-type semiconductor layer 4 side.

Further, as shown in FIG. 4, when the number of MQW pairs is 8, the light emission output P exhibits the maximum value P2, while when the number of MQW pairs is 5 or 12, the light emission output P is P ₁ (P ₁ <P ₂ When the number of MQW pairs is smaller than 5 or larger than 12, it is difficult to secure a sufficient light output P.

  In the semiconductor light emitting device according to the first embodiment, the active layer for efficiently recombining the electrons supplied from the n-type semiconductor layer 2 and the holes supplied from the p-type semiconductor layer 4 in the active layer 3. The number of MQW pairs in 3 can be optimized.

(Final barrier layer)
The final barrier layer 310 is formed thicker than the Mg diffusion distance from the p-type semiconductor layer 4 to the active layer 3.

  In the semiconductor light emitting device shown in FIG. 1, the concentration of the p-type impurity in the final barrier layer 310 is from the first main surface of the final barrier layer 310 in contact with the p-type semiconductor layer 4 along the film thickness direction of the final barrier layer 310. There is no p-type impurity in the second main surface that gradually decreases and faces the first main surface.

  The film thickness d0 of the final barrier layer 310 of the semiconductor light emitting device shown in FIG. 1 is such that the p-type impurities diffused from the p-type semiconductor layer 4 to the active layer 3 in the process of forming the p-type semiconductor layer 4 and thereafter It is set so as not to reach the well layer 32 of the layer 3. That is, the p-type impurity diffused from the p-type semiconductor layer 4 to the final barrier layer 310 is a second main surface (the final barrier layer 310 is a well) facing the first main surface of the final barrier layer 310 in contact with the p-type semiconductor layer 4. The film thickness d0 is set to a thickness that does not reach the surface (the surface in contact with the layer 32n).

The Mg concentration on the first main surface of the final barrier layer 310 in contact with the p-type semiconductor layer 4 is, for example, about 2 × 10 ²⁰ cm ⁻³ , and the second concentration of the final barrier layer 310 facing the first main surface is about 2 × 10 ²⁰ cm ⁻³ . The Mg concentration gradually decreases toward the main surface, and the Mg concentration falls below the lower detection limit of about 10 ¹⁶ cm ⁻³ or less at a position of about 7 to 8 nm from the first main surface. That is, by setting the film thickness d0 of the final barrier layer 310 to about 10 nm, Mg does not diffuse to the second main surface of the final barrier layer 310, and therefore, the second barrier layer 310 in contact with the active layer 3 has a second thickness. There is no Mg on the main surface. That is, Mg does not diffuse into the n-th well layer 32n, and a reduction in the luminance of light generated in the active layer 3 is prevented.

  The film thicknesses d1 to dn of the first barrier layer 311 to the nth barrier layer 31n may be the same. However, the thicknesses d1 to dn are such that holes injected from the n-type semiconductor layer 2 into the active layer 3 reach the nth well layer 32n, and light emission due to recombination of electrons and holes occurs in the nth well layer 32n. It is necessary to set a thickness that can be generated. This is because if the film thicknesses d1 to dn of the first barrier layer 311 to the nth barrier layer 31n are too thick, the movement of holes in the active layer 3 is hindered and the light emission efficiency is lowered.

  For example, the film thickness d0 of the final barrier layer 310 is about 10 nm, the film thicknesses d1 to dn of the first barrier layer 311 to the nth barrier layer 31n are about 7 to 18 nm, and the first well layer 321 to the first well layer 321 to the first barrier layer 31n. The thickness of the n well layer 32n is about 2 to 3 nm.

  As described above, in the semiconductor light emitting device according to the first embodiment, the thickness d0 of the final barrier layer 310 in contact with the p-type semiconductor layer 4 is diffused from the p-type semiconductor layer 4 to the active layer 3. The thickness is set such that the type dopant does not reach the well layer 32 of the active layer 3. That is, according to the semiconductor light emitting device shown in FIG. 1, by setting the film thickness d0 of the final barrier layer 310 to be larger than the Mg diffusion distance, the p-type is suppressed while suppressing the increase in the film thickness of the active layer 3 as a whole. The diffusion of p-type impurities from the semiconductor layer 4 to the well layer 32 of the active layer 3 can be prevented. As a result, it is possible to manufacture a semiconductor light emitting device in which the light luminance is not lowered due to the diffusion of the p-type impurity into the well layer 32 and the deterioration of the quality of the semiconductor light emitting device is suppressed.

(Electrode structure)
As shown in FIG. 3, the semiconductor light emitting device according to the first embodiment includes an n-side electrode 200 that applies a voltage to the n-type semiconductor layer 2 and a p-side electrode 100 that applies a voltage to the p-type semiconductor layer 4. Is further provided. As shown in FIG. 3, the p-type semiconductor layer 4, the active layer 3, the block layer 7, and a partial region of the n-type semiconductor layer 2 are exposed on the n-type semiconductor layer 2 by mesa etching. An electrode 200 is disposed.

  The p-side electrode 100 is disposed on the p-type semiconductor layer 4 via the oxide electrode 5. Alternatively, the p-side electrode 100 may be disposed directly on the p-type semiconductor layer 4. The transparent electrode made of the oxide electrode 5 disposed on the fourth nitride semiconductor layer 44 includes, for example, any of ZnO, ITO, or ZnO containing indium.

  The n-side electrode 200 is, for example, an aluminum (Al) film, a multilayer film of Ti / Ni / Au or Al / Ti / Au, Al / Ni / Au, Al / Ti / Ni / Au, or Au—Sn / Ti from the upper layer. The p-side electrode 100 is made of, for example, an Al film, a palladium (Pd) -gold (Au) alloy film, a Ni / Ti / Au multilayer film, or an Au—Sn / It consists of a multilayer film of Ti / Au. The n-side electrode 200 is ohmically connected to the n-type semiconductor layer 2, and the p-side electrode 100 is ohmically connected to the p-type semiconductor layer 4 via the oxide electrode 5.

  In order to mount the semiconductor light emitting device according to the first embodiment of the present invention in a flip-chip structure, the surface of the p-side electrode 100 and the surface of the n-side electrode 200 measured from the substrate 1 have the same height. You may form so that it may become.

A transparent conductive film ZnO may be formed as the oxide electrode 5 and the ZnO may be covered with a reflective laminated film that reflects the wavelength λ of the emitted light. The reflective laminated film has a laminated structure of λ / 4n ₁ and λ / 4n ₂ (n ₁ and n ₂ are refractive indexes of the laminated layers). As a material used for the laminated structure, for example, λ = 450 nm for blue light On the other hand, a laminated structure composed of ZrO ₂ (n = 2.12) and SiO ₂ (n = 1.46) can be used. In this case, the thickness of each layer is, for example, about 53 nm for ZrO ₂ and about 77 nm for SiO ₂ . As another material for forming the laminated structure, TiO ₂ , Al ₂ O ₃ or the like can be used.

  According to the semiconductor light emitting device according to the first embodiment, the light emitted in the active layer 3 by the reflective laminated film 8 can be extracted outside without being absorbed by the n-side electrode 100, and thus the external light emission. Efficiency can be improved.

(Production method)
Hereinafter, an example of a method for manufacturing the semiconductor light emitting device according to the first embodiment shown in FIG. 1 will be described. In addition, the manufacturing method of the semiconductor light emitting element described below is an example, and it is needless to say that it can be realized by various other manufacturing methods including this modification. Here, an example in which a sapphire substrate is applied to the substrate 1 will be described.

(A) First, an AlN buffer layer 6 is grown on the sapphire substrate 1 by a well-known metal organic chemical vapor deposition (MOCVD) method or the like. For example, at a high temperature of about 900 ° C. to 950 ° C., trimethylaluminum (TMA) and ammonia (NH ₃ ) are supplied to the reaction chamber alternately and pulsed by using H ₂ gas as a carrier. A thin AlN buffer layer 6 of about 10 to 50 angstroms is grown in a short time.

(B) Next, a GaN layer to be the n-type semiconductor layer 2 is grown on the AlN buffer layer 6 by MOCVD or the like. For example, after the substrate 1 on which the AlN buffer layer 6 is formed is thermally cleaned, the substrate temperature is set to about 1000 ° C., and the n-type semiconductor layer 2 doped with n-type impurities on the AlN buffer layer 6 is set to 1 Grow about ~ 5 μm. For the n-type semiconductor layer 2, for example, a GaN film doped with Si as an n-type impurity at a concentration of about 3 × 10 ¹⁸ cm ⁻³ can be employed. When Si is added as an impurity, trimethylgallium (TMG), ammonia (NH ₃ ), and silane (SiH ₄ ) are supplied as source gases to form the n-type semiconductor layer 2.

(C) Next, as the block layer 7 on the n-type semiconductor layer 2, for example, a GaN film doped with Si at a concentration of less than 1 × 10 ¹⁷ cm ⁻³ , for example, about 8 × 10 ¹⁶ cm ⁻³ , Grow about 200 nm. At this time, the same source gas as in the case where the n-type semiconductor layer 2 is formed can be applied.

(D) Next, the active layer 3 is formed on the n-type semiconductor layer 2. For example, the active layer 3 is formed by alternately laminating barrier layers 31 made of GaN films and well layers 32 made of InGaN films. Specifically, while adjusting the substrate temperature and the flow rate of the source gas when forming the active layer 3, the barrier layers 31 and the well layers 32 are grown alternately and continuously, and the barrier layers 31 and the well layers 32 are stacked. Thus formed active layer 3 is formed. That is, the step of laminating the well layer 32 and the barrier layer 31 having a larger band gap than the well layer 32 by adjusting the substrate temperature and the flow rate of the source gas is defined as a unit step, and this unit step is repeated n times, for example, about 8 times. Thus, a stacked structure in which the barrier layers 31 and the well layers 32 are alternately stacked is obtained.

  For example, the barrier layer 31 is formed at the substrate temperature Ta, and the well layer 32 is formed at the substrate temperature Tb (Ta> Tb). That is, the first barrier layer 311 is formed at times t10 to t11 when the substrate temperature is set to Ta. Next, the substrate temperature is set to Tb at time t11, and the first well layer 321 is formed at time t11 to time t20. Similarly, the second barrier layer 312 is formed at the substrate temperature Ta from time t20 to t21, and the second well layer 322 is formed at the substrate temperature Tb from time t21 to time t30. Then, the nth barrier layer 31n is formed at the substrate temperature Ta at the time tn0 to tn1, the nth well layer 32n is formed at the substrate temperature Tb at the time tn1 to the time te, and the barrier layers 31 and the well layers 32 are alternately stacked. The laminated structure completed is completed.

In the case of forming the barrier layer 31, as source gases, for example, TMG gas is supplied to a film forming processing apparatus at a flow rate of 300 sccm (standard cc / min) and NH ₃ gas at a flow rate of 20 slm (standard L / min). On the other hand, when forming the well layer 32, as source gases, for example, TMG gas is supplied to the processing apparatus at a flow rate of 300 sccm, trimethylindium (TMI) gas is 280 sccm, and NH ₃ gas is supplied at a flow rate of 20 slm. TMG gas is supplied as Ga atom source gas, TMI gas is supplied as In atom source gas, and NH ₃ gas is supplied as nitrogen atom source gas.

  An active layer 3 shown in FIG. 1 is formed by forming a non-doped GaN film of about 10 nm as the final barrier layer 310 on the formed laminated structure. As already described, the film thickness d0 of the final barrier layer 310 is set to a thickness at which the p-type dopant diffused from the p-type semiconductor layer 4 to the active layer 3 does not reach the well layer 32 of the active layer 3.

(E) Next, the substrate temperature is set to about 800 ° C. to 900 ° C., and the p-type semiconductor layer 4 doped with p-type impurities is formed on the final barrier layer 310 to about 0.05 to 1 μm.

The p-type semiconductor layer 4 is formed, for example, in a four-layer structure in which Mg is added as a p-type impurity. The first nitride-based semiconductor layer 41 disposed on the active layer 3 is formed of a p-type GaN layer having a thickness of approximately 2 × 10 ²⁰ cm ⁻³ and a thickness of approximately 50 nm, and the second nitride-based semiconductor layer 42 is formed. Is formed of a p-type GaN layer having a thickness of about 4 × 10 ¹⁹ cm ⁻³ and a thickness of about 100 nm. The third nitride semiconductor layer 43 has a thickness of about 1 × 10 ²⁰ cm ⁻³ and a thickness of about 40 nm, for example. The fourth nitride semiconductor layer 44 is formed of a p-type GaN layer having a thickness of about 8 × 10 ¹⁹ cm ⁻³ and a thickness of about 10 nm.

When adding Mg as impurities, TMG gas, NH ₃ gas and biscyclopentadienyl magnesium (Cp ₂ Mg) gas are supplied as source gases to form the p-type semiconductor layers 4 (41 to 44). Mg is diffused from the p-type semiconductor layer 4 (41 to 44) to the active layer 3 during the formation of the p-type semiconductor layer 4 (41 to 44), but the Mg is diffused into the well layer 32 of the active layer 3 by the final barrier layer 310. It is prevented from spreading.

  Here, the process of forming the p-type semiconductor layer 4 will be described in more detail.

  In the semiconductor light emitting device according to the first embodiment, the temperature distribution when forming the p-type semiconductor layers (41 to 44) having the four-layer structure is as shown in FIGS. 7 (a) and 8 (a). expressed. Further, the drawings for explaining the conditions of the hydrogen gas flow when forming the p-type semiconductor layers (41 to 44) having the four-layer structure are expressed as shown in FIGS. 7 (b) to 7 (d). Further, a diagram for explaining the conditions of the nitrogen gas flow when forming the p-type semiconductor layers (41 to 44) having the four-layer structure is expressed as shown in FIG. Moreover, the figure explaining the conditions of ammonia gas flow is represented as shown in FIG.8 (c).

  In the temperature distribution shown in FIGS. 7A and 8A, a period T1 from time t1 to t2 is a period in which the first nitride-based semiconductor layer 41 is formed, and a period T2 from time t2 to t3 is This is a period for forming the second nitride semiconductor layer 42, a period T3 from time t3 to t4 is a period for forming the third nitride semiconductor layer 43, and a period T4 from time t4 to t5 is the fourth period. This is a period in which the nitride-based semiconductor layer 44 is formed. A period T5 between times t5 and t6 is a period during which the substrate temperature is cooled from 850 ° C. to 350 ° C.

  In the method of manufacturing the semiconductor light emitting device according to the first embodiment, the step of forming the n-type semiconductor layer 2, the step of forming the active layer 3 on the n-type semiconductor layer 2, forming a nitride semiconductor layer (41-44) at a low temperature of about 800-900 ° C. by laminating a plurality of p-type GaN layers each containing a p-type impurity, and using a carrier gas not containing hydrogen A source gas is supplied to form at least a part of the plurality of p-type GaN layers.

  When the p-type semiconductor layer 4 is formed with a carrier gas containing hydrogen, the Mg atoms are hardly activated by the hydrogen atoms taken together with the Mg, and the p-type semiconductor layer 4 is prevented from being made p-type. Therefore, after forming the p-type semiconductor layer 4, it is necessary to perform annealing (hereinafter referred to as “p-type annealing”) for removing the hydrogen atoms and making the p-type semiconductor layer 4 p-type.

  However, according to the method for manufacturing the semiconductor light emitting device according to the first embodiment, at least one of the first nitride semiconductor layer 41 to the fourth nitride semiconductor layer 44 is formed by a carrier gas not containing hydrogen. By supplying the source gas of Mg and forming it, the step of p-type annealing can be omitted. Which part of the p-type semiconductor layer 4 is formed by a carrier gas not containing hydrogen can be arbitrarily set. For example, the first nitride semiconductor layer 41 to the third nitride semiconductor layer 43 do not contain hydrogen. It may be formed by a carrier gas, and only the fourth nitride semiconductor layer 44 may be formed by a carrier gas containing hydrogen.

  For example, as shown in FIG. 7B, among the first nitride semiconductor layer 41 to the fourth nitride semiconductor layer 44, the second nitride semiconductor layer 42 having a large film thickness or a high Mg concentration. Forming the first nitride-based semiconductor layer 41 with a carrier gas not containing hydrogen is preferable in that the step of p-type annealing is omitted. For example, FIG. 7C shows that the first nitride-based semiconductor layer 41 to the third nitride-based semiconductor layer 43 among the first nitride-based semiconductor layer 41 to the fourth nitride-based semiconductor layer 44 are replaced with hydrogen. It is an example formed by a carrier gas not included. FIG. 7D shows an example in which the first nitride-based semiconductor layer 41 and the third nitride-based semiconductor layer 43 are formed using a carrier gas that does not contain hydrogen. FIG. 7E shows an example in which the second nitride-based semiconductor layer 42 and the third nitride-based semiconductor layer 43 are formed using a carrier gas that does not contain hydrogen.

  On the other hand, as shown in FIGS. 7B to 7E, the fourth nitride semiconductor layer 44 in contact with the p-side electrode 100 is formed of Mg by a carrier gas containing hydrogen in order to improve the crystal state as much as possible. It is preferable to form by supplying the raw material gas. In general, when the source gas of Mg is supplied by a carrier gas containing hydrogen, the crystal state of the p-type semiconductor layer doped with Mg is higher than when the source gas of Mg is formed by a carrier gas not containing hydrogen. Because it is good.

  The p-type film forming method in the method for manufacturing the semiconductor light emitting device according to the first embodiment will be described below. Note that the p-type film forming method described below is an example, and it is needless to say that it can be realized by various other methods including this modification. Here, Mg is employed as the p-type impurity, and as shown in FIG. 7B, the first nitride-based semiconductor layer 41 and the second nitride-based semiconductor layer 42 are formed by a carrier gas not containing hydrogen, A case where the third nitride semiconductor layer 43 and the fourth nitride semiconductor layer 44 are formed using a carrier gas containing hydrogen will be described as an example.

  As shown in FIGS. 7 to 8, the substrate temperature Tp for forming the p-type semiconductor layer 4 is set to 850 ° C. and the pressure is set to 200 Torr.

In (step 1) Time t1~ time t2 supply, by supplying N ₂ gas as a carrier gas, NH ₃ gas as a raw material gas, TMG gas, each processor biscyclopentadienyl magnesium (Cp ₂ Mg) gas Thus, the first nitride semiconductor layer 41 is formed. The first nitride-based semiconductor layer 41 having a film thickness = 50 nm and an Mg concentration = 2 × 10 ²⁰ cm ⁻³ is formed with a time interval between time t1 and time t2.

(Step 2) From time t2 to time t3, N ₂ gas is supplied as a carrier gas, and NH ₃ gas, TMG gas, and Cp ₂ Mg gas are supplied as source gases to the processing apparatus, respectively, and the second nitride semiconductor Layer 42 is formed. The second nitride-based semiconductor layer 42 having a film thickness = 100 nm and an Mg concentration = 4 × 10 ¹⁹ cm ⁻³ is formed with a time interval between time t2 and time t3 being 21 minutes.

(Step 3) From time t3 to time t4, H ₂ gas and N ₂ gas are supplied as carrier gases, and NH 3 gas, TMG gas, and Cp ₂ Mg gas are supplied as source gases to the processing apparatus, respectively, and third nitriding is performed. A physical semiconductor layer 43 is formed. The third nitride-based semiconductor layer 43 having a film thickness = 40 nm and an Mg concentration = 1 × 10 ²⁰ cm ⁻³ is formed with a time period from time t3 to time t4 being 1 minute.

(Step 4) From time t4 to time t5, H ₂ gas and N ₂ gas are supplied as carrier gases, and NH ₃ gas, TMG gas, and Cp ₂ Mg gas are supplied as source gases to the processing apparatus, respectively. A nitride-based semiconductor layer 44 is formed. The fourth nitride semiconductor layer 44 having a film thickness = 10 nm and an Mg concentration = 8 × 10 ¹⁹ cm ⁻³ is formed with a time interval between time t4 and time t5 being 3 minutes.

(Step 5) At time t5 to time t6, the substrate temperature is lowered from the temperature Tp (850 ° C.) to the temperature Td (350 ° C.) or lower while supplying N ₂ gas as the carrier gas. That is, p-type annealing performed at 400 ° C. or higher is not performed.

The p-type semiconductor layer 4 including the first nitride-based semiconductor layer 41 to the fourth nitride-based semiconductor layer 44 is formed by the steps 1 to 5 described above. Since the first nitride-based semiconductor layer 41 with a high Mg concentration and the second nitride-based semiconductor layer 42 with a large film thickness are formed by a carrier gas not containing H ₂ gas, p-type annealing is not performed. A p-type semiconductor layer 4 is obtained as a p-type semiconductor. In addition, the fourth nitride semiconductor layer 44 is improved in crystal state by being formed by supplying a carrier gas containing H ₂ gas. That is, the crystal state of the surface in contact with the p-side electrode 100 of the p-type semiconductor layer 4 is good, and the contact with the p-side electrode 100 of the p-type semiconductor layer 4 is good.

According to the formation process of the p-type semiconductor layer 4 as described above, the carrier gas containing no H ₂ gas is supplied to form the p-type semiconductor layer 4, thereby bringing the p-type semiconductor layer 4 together with the p-type impurities. H ₂ is not taken into Therefore, p-type annealing for removing H ₂ from the p-type semiconductor layer 4 becomes unnecessary, and the manufacturing process of the semiconductor light emitting device can be shortened.

(F) Next, the oxide electrode 5 is formed on the p-type semiconductor layer 4 by vapor deposition, sputtering technique or the like. As the oxide electrode 5, for example, any one of ZnO, ITO, or ZnO containing indium can be used. Further, an n-type impurity such as Ga or Al may be added at a high concentration up to about 1 × 10 ^{19 to} 5 × 10 ²¹ cm ⁻³ .

(G) Next, after patterning the oxide electrode 5, a reflective laminated film 8 that reflects the wavelength λ of the emitted light is formed so as to cover the oxide electrode 5 by vapor deposition, sputtering technique, or the like. As the material used for the reflective laminated film 8, for example, a laminated structure made of ZrO ₂ (n = 2.12) and SiO ₂ (n = 1.46) is used for blue light with λ = 450 nm. The thickness of each layer is, for example, about 53 nm for ZrO ₂ and about 77 nm for SiO ₂ .

(H) Next, the reflective laminated film 8 and the middle of the p-type semiconductor layer 4 to the n-type semiconductor layer 2 are removed by mesa etching using an etching technique such as reactive ion etching (RIE). Then, the surface of the n-type semiconductor layer 2 is exposed.

(I) Next, n-side electrodes 200 and 300 are formed on the exposed surface of the n-type semiconductor layer 2 by vapor deposition, sputtering technique, or the like. Also on the oxide electrode 5 on the p-type semiconductor layer 4, the p-side electrode 100 is formed by vapor deposition, sputtering technique, etc. after pattern formation, and the semiconductor light emitting device shown in FIG. 3 is completed.

(Modification)
A schematic cross-sectional structure of the semiconductor light emitting device according to the modification of the first embodiment is expressed as shown in FIG. 2A, and an enlarged schematic cross-sectional structure of the active layer portion is shown in FIG. ).

  As shown in FIG. 2, the semiconductor light emitting device according to the modification of the first embodiment includes a substrate 1, a buffer layer 6 disposed on the substrate 1, a buffer layer 6 and an n-type impurity. Is disposed on the n-type semiconductor layer 2 doped with n-type impurities, the block layer 7 doped with n-type impurities at a lower concentration than the n-type semiconductor layer 2, and disposed on the block layer 7 Active layer 3, p-type semiconductor layer 4 disposed on active layer 3, and oxide electrode 5 disposed on p-type semiconductor layer 4.

  The semiconductor light emitting device according to the modification of the first embodiment is disposed on the third nitride semiconductor layer 43 including the p-type impurity disposed on the active layer 3 and on the third nitride semiconductor layer. And a fourth nitride-based semiconductor layer containing a p-type impurity at a concentration lower than that of the p-type impurity of the third nitride-based semiconductor layer, and an oxide electrode 5 disposed on the fourth nitride-based semiconductor layer. And a transparent electrode.

In addition, the transparent electrode includes any one of ZnO doped with impurities up to about 1 × 10 ^{19 to} 5 × 10 ²¹ cm ^{−3 of} Ga or Al, ITO, or ZnO containing indium.

  The semiconductor light emitting device according to the modification of the first embodiment has a third structure in which the p-type semiconductor layer 4 is directly disposed on the active layer 3 because of the structure of the semiconductor light emitting device according to the first embodiment. 2 comprising a nitride-based semiconductor layer and a fourth nitride-based semiconductor layer disposed on the third nitride-based semiconductor layer and including a p-type impurity at a concentration lower than that of the p-type impurity of the third nitride-based semiconductor layer. It is formed in a layer structure.

The third nitride-based semiconductor layer 43 disposed directly on the active layer 3 is formed of, for example, a p-type GaN layer of about 1 × 10 ²⁰ cm ⁻³ and about 40 nm thick doped with Mg. .

The fourth nitride semiconductor layer 44 disposed on the third nitride semiconductor layer 43 and containing a p-type impurity having a lower concentration than the p-type impurity of the third nitride semiconductor layer 43 is doped with, for example, Mg. The p-type GaN layer is about 8 × 10 ¹⁹ cm ⁻³ and about 10 nm thick.

  In the semiconductor light emitting device according to the second embodiment, the p-type semiconductor layer 4 formed on the active layer 3 made of a multiple quantum well containing indium has a two-layer structure with different Mg concentrations as described above. It consists of a p-type GaN layer and is doped at the above concentration. The p-type GaN layer is grown at a low temperature of about 800 ° C. to 900 ° C. in order to reduce thermal damage to the active layer 3.

  Since the third nitride semiconductor layer 43 closest to the active layer 3 is a layer that determines the amount of holes injected into the active layer 3, the higher the Mg concentration, the higher the emission intensity. For this reason, the higher the Mg concentration, the better.

The fourth nitride-based semiconductor layer 44 is a p-type GaN layer for making ohmic contact with the oxide electrode 5 and is substantially depleted. For example, when a ZnO electrode doped with about 1 × 10 ^{19 to} 5 × 10 ²¹ cm ^{−3 of} Ga or Al is used as the oxide electrode 5, the Mg when the forward voltage Vf of the semiconductor light emitting element is lowered most Mg is added to the fourth nitride-based semiconductor layer 44 so as to have a concentration.

When four p-type GaN layers are grown, the third nitride semiconductor layer 43 and the fourth nitride semiconductor layer 44 close to the p-side electrode 100 need to increase the hole concentration in the film. Increase the amount of H ₂ gas in the carrier gas. Alternatively, the third nitride-based semiconductor layer 43 close to the active layer 3 does not need to increase the amount of H ₂ gas in the carrier gas, and is crystallized as an extension of the active layer 3 grown with N ₂ carrier gas. It may be grown.

  Also in the semiconductor light emitting device according to the modification of the first embodiment, the AlN buffer layer 6, the n-type semiconductor layer 2, the block layer 7, the active layer 3, the p-type semiconductor layer 4, the final barrier layer 310, and the reflective laminated film 8 are used. Since the electrode structure is the same as that of the semiconductor light emitting device according to the first embodiment of the present invention, the description thereof is omitted.

  According to the semiconductor light emitting device according to the first embodiment and the modification thereof, the electrons supplied from the n-type semiconductor layer and the holes supplied from the p-type semiconductor layer are efficiently recombined in the active layer. The number of MQW pairs in the active layer can be optimized and the light emission efficiency can be improved.

[Second Embodiment]
As shown in FIG. 9, the semiconductor light emitting device according to the second embodiment of the present invention is disposed on the substrate 1, the n-type semiconductor layer 2 disposed on the substrate 1, and the n-type semiconductor layer 2. And an active layer 3 having a stacked structure in which barrier layers and well layers having a smaller band gap than the barrier layer are alternately arranged, and a p-type semiconductor layer 4 disposed on the active layer 3 and including a p-type dopant. . In the semiconductor light emitting device shown in FIG. 9, the film thickness d0 of the final barrier layer 310 in the uppermost layer of the stacked structure of the active layer 3 is larger than the distance for diffusing the final barrier layer 310 of the p-type dopant, The concentration of the type dopant gradually decreases from the first main surface of the final barrier layer 310 in contact with the p-type semiconductor layer 4 along the film thickness direction of the final barrier layer 310, and the p-type in the second main surface facing the first main surface. The concentration of dopand is less than 1 × 10 ¹⁶ cm ⁻³ .

  As the substrate 1, for example, a sapphire substrate or the like can be employed. The n-type semiconductor layer 2, the active layer 3, and the p-type semiconductor layer 4 are each made of a group III nitride semiconductor, and the n-type semiconductor layer 2, the active layer 3, and the p-type semiconductor layer 4 are sequentially stacked on the substrate 1.

  The n-type semiconductor layer 2 supplies electrons to the active layer 3, and the p-type semiconductor layer 4 supplies holes to the active layer 3. Light is generated by the recombination of the supplied electrons and holes in the active layer 3.

  As the n-type semiconductor layer 2, a group III nitride semiconductor having a film thickness of about 0.2 to 5 μm doped with an n-type dopant such as silicon (Si), for example, a GaN layer can be employed. As the p-type semiconductor layer 4, a group III nitride semiconductor doped with a p-type dopant and having a thickness of about 0.05 to 1 μm, for example, a GaN layer can be employed. As the p-type dopant, magnesium (Mg), zinc (Zn), cadmium (Cd), calcium (Ca), beryllium (Be), carbon (C), or the like can be used.

  As shown in FIG. 9, the active layer 3 includes a first quantum well layer 321 to a nth well layer 32 n sandwiched between a first barrier layer 311 to an nth barrier layer 31 n and a final barrier layer 310, respectively. MQW) structure (n: natural number). That is, the active layer 3 has a quantum well structure in which a well layer is sandwiched between barrier layers having a larger band gap than the well layer as a unit structure, and this unit structure is stacked n times. Specifically, the first well layer 321 is disposed between the first barrier layer 311 and the second barrier layer 312, and the second well layer 322 is disposed between the second barrier layer 312 and the third barrier layer 313. The The nth well layer 32n is disposed between the nth barrier layer 31n and the final barrier layer 310. The first barrier layer 311 of the active layer 3 is disposed on the n-type semiconductor layer 2, and the p-type semiconductor layer 4 is disposed on the final barrier layer 310 of the active layer 3.

  The semiconductor light emitting device shown in FIG. 9 further includes an n-side electrode 200 that applies a voltage to the n-type semiconductor layer 2 and a p-side electrode 100 that applies a voltage to the p-type semiconductor layer 4. As shown in FIG. 9, the n-side electrode 200 is disposed on the surface of the n-type semiconductor layer 2 exposed by mesa etching of the p-type semiconductor layer 4, the active layer 3, and a partial region of the n-type semiconductor layer 2. Is done. The p-side electrode 100 is disposed on the p-type semiconductor layer 4. The n-side electrode 200 is made of, for example, an aluminum (Al) film, and the p-side electrode 100 is made of, for example, a titanium (Ti) film, a nickel (Ni) film, an indium tin oxide (ITO) film, or a zinc oxide (ZnO) film. Or the like, or a palladium (Pd) -gold (Au) alloy film. The n-side electrode 200 is ohmically connected to the n-type semiconductor layer 2, and the p-side electrode 100 is ohmically connected to the p-type semiconductor layer 4.

  The barrier layer 31 and the final barrier layer 310 are made of, for example, a GaN film, and the well layer 32 is made of, for example, an indium gallium nitride (InGaN) film. Note that the composition ratio of indium (In) in the well layer 32 is appropriately set according to the wavelength of light to be generated. As the barrier layer 31, an InGaN film having a smaller In composition than the well layer 32 may be employed.

  The film thickness d0 of the final barrier layer 310 of the semiconductor light emitting device shown in FIG. 9 is such that the p-type dopant diffused from the p-type semiconductor layer 4 to the active layer 3 in the process of forming the p-type semiconductor layer 4 and thereafter is active. It is set so as not to reach the well layer 32 of the layer 3. That is, the p-type dopant diffused from the p-type semiconductor layer 4 to the final barrier layer 310 is a second main surface (the final barrier layer 310 is a well) facing the first main surface of the final barrier layer 310 in contact with the p-type semiconductor layer 4. The film thickness d0 is set to a thickness that does not reach the layer 32n).

FIG. 10 shows an example of the concentration distribution of the p-type dopant diffused from the p-type semiconductor layer 4 in the final barrier layer 310. FIG. 10 shows a p-type semiconductor layer 4 made of a GaN layer doped with magnesium (Mg) as a p-type dopant at a concentration of 3 × 10 ¹⁹ cm ⁻³ on the final barrier layer 310 formed as a non-doped GaN film. The Mg density | concentration distribution in the last barrier layer 310 in the case of forming is shown exemplarily. The vertical axis in FIG. 10 is the Mg concentration in the final barrier layer 310, and the horizontal axis is the distance in the film thickness direction of the final barrier layer 310 starting from the first main surface of the final barrier layer 310 in contact with the p-type semiconductor layer 4. It is.

In the example shown in FIG. 10, the Mg concentration in the first main surface of the final barrier layer 310 in contact with the p-type semiconductor layer 4 is approximately the same as the Mg concentration in the p-type semiconductor layer 4 in contact with the first main surface. It is 2 × 10 ²⁰ cm ⁻³ , and the Mg concentration gradually decreases toward the second main surface of the final barrier layer 310 facing the first main surface, and the Mg concentration is 1 at a position 8 nm from the first main surface. × Below the lower limit of measurement less than 10 ¹⁶ cm ⁻³ . That is, by setting the film thickness d0 of the final barrier layer 310 to 8 nm or more, Mg that reaches the well layer 32 and adversely affects light emission does not diffuse to the second main surface of the final barrier layer 310. Therefore, there is no Mg on the second main surface of the final barrier layer 310 that is in contact with the active layer 3 to the extent that the light emission is adversely affected. That is, Mg does not diffuse into the n-th well layer 32n, and a reduction in the luminance of light generated in the active layer 3 is prevented.

FIG. 11 shows an example of the Mg concentration of the final barrier layer 310 and the p-type semiconductor layer 4. As shown in FIG. 11A, a final barrier layer 310 having a thickness of 10 nm is disposed in contact with the second main surface of the n-th well layer 32n having a thickness of 2.8 nm, and the first main surface of the final barrier layer 310 is disposed. A p-type semiconductor layer 4 is disposed in contact with the substrate. The p-type semiconductor layer 4 shown in FIG. 11 has a structure in which a first nitride semiconductor layer 41 to a fourth nitride semiconductor layer 44 are stacked in this order. Examples of the film thickness and Mg concentration of the first nitride semiconductor layer 41 to the fourth nitride semiconductor layer 44 are shown below:
(1) First nitride semiconductor layer 41: film thickness = 50 nm, Mg concentration = 2 × 10 ²⁰ cm ⁻³
(2) Second nitride semiconductor layer 42: film thickness = 100 nm, Mg concentration = 4 × 10 ¹⁹ cm ⁻³
(3) Third nitride semiconductor layer 43: film thickness = 40 nm, Mg concentration = 1 × 10 ²⁰ cm ⁻³
(4) Fourth nitride semiconductor layer 44: film thickness = 10 nm, Mg concentration = 8 × 10 ¹⁹ cm ⁻³
The Mg concentration of the n-th well layer 32n, the final barrier layer 310, and the p-type semiconductor layer 4 is as shown in FIG. As shown in FIG. 11B, since the film thickness d0 of the final barrier layer 310 is thicker than the diffusion distance of Mg in the final barrier layer 310, Mg reaching the n-th well layer 32n has an adverse effect on light emission. Absent.

  FIG. 12 shows an example of the relationship between the film thickness d0 of the final barrier layer 310 and the output PO of light emission from the active layer 3. As shown in FIG. 12, the output PO is maximized when the film thickness is d0 = 10 nm, and in order to make the output PO 90% or more of the maximum output, the film thickness d0 = 10 nm ± 2 nm is preferable.

  The film thicknesses d1 to dn of the first barrier layer 311 to the nth barrier layer 31n may be the same. However, the film thicknesses d1 to dn are such thicknesses that holes injected from the p-type semiconductor layer 4 to the active layer 3 reach the well layer 32 and light emission due to recombination of electrons and holes may occur in the well layer 32. Must be set to This is because if the film thicknesses d1 to dn of the first barrier layer 311 to the nth barrier layer 31n are too thick, the movement of holes in the active layer 3 is hindered and the light emission efficiency is lowered. For example, the film thickness d0 of the final barrier layer 310 is about 10 nm, the film thicknesses d1 to dn of the first barrier layer 311 to the nth barrier layer 31n are about 7 to 16 nm, and the first well layer 321 to the nth well. The thickness of the layer 32n is about 3 nm. Therefore, when the film thicknesses d1 to dn of the first barrier layer 311 to the nth barrier layer 31n are, for example, about 16.5 nm, the film thickness d0 of the final barrier layer 310 is smaller than the film thicknesses d1 to dn.

  As described above, in the semiconductor light emitting device according to the second embodiment, the thickness d0 of the final barrier layer 310 in contact with the p-type semiconductor layer 4 is diffused from the p-type semiconductor layer 4 to the active layer 3. The thickness is set such that the type dopant does not reach the well layer 32 of the active layer 3. That is, according to the semiconductor light emitting device shown in FIG. 9, by setting the film thickness d0 of the final barrier layer 310 to be thicker than the distance for diffusing the final barrier layer 310 of the p-type dopant, The diffusion of the p-type dopant from the p-type semiconductor layer 4 to the well layer 32 of the active layer 3 can be prevented while suppressing the increase. As a result, the light luminance is not lowered due to the diffusion of the p-type dopant into the well layer 32, and the deterioration of the quality of the semiconductor light emitting element is suppressed.

  Hereinafter, an example of a method for manufacturing the semiconductor light emitting element shown in FIG. 9 will be described. In addition, the manufacturing method of the semiconductor light emitting element described below is an example, and it is needless to say that it can be realized by various other manufacturing methods including this modification. Here, an example in which a sapphire substrate is applied to the substrate 1 will be described.

As a manufacturing method, GaN is grown on a sapphire substrate by a well-known metal organic chemical vapor deposition (MOCVD) method or the like. For example, after the substrate 1 is thermally cleaned, the substrate temperature is set to about 1000 ° C., and the n-type semiconductor layer 2 doped with the n-type dopant is grown on the substrate 1 by about 1 to 5 μm. For the n-type semiconductor layer 2, for example, a GaN film doped with Si as an n-type dopant at a concentration of about 3 × 10 ¹⁸ cm ⁻³ can be employed. When doping Si, trimethylgallium (TMG), ammonia (NH ₃ ), and silane (SiH ₄ ) are supplied as source gases to form the n-type semiconductor layer 2.

  Next, the active layer 3 is formed on the n-type semiconductor layer 2. For example, the active layer 3 is formed by alternately laminating barrier layers 31 made of GaN films and well layers 32 made of InGaN films. Specifically, while adjusting the substrate temperature and the flow rate of the source gas when forming the active layer 3, the barrier layers 31 and the well layers 32 are grown alternately and continuously, and the barrier layers 31 and the well layers 32 are stacked. Thus formed active layer 3 is formed. That is, the step of laminating the well layer 32 and the barrier layer 31 having a larger band gap than the well layer 32 by adjusting the substrate temperature and the flow rate of the source gas is defined as a unit step, and this unit step is repeated n times, for example, about 8 times. Thus, a stacked structure in which the barrier layers 31 and the well layers 32 are alternately stacked is obtained.

  FIG. 13 shows an example in which the barrier layer 31 and the well layer 32 are stacked. The barrier layer 31 is formed at the substrate temperature Ta shown in FIG. 13, and the well layer 32 is formed at the substrate temperature Tb.

  That is, the first barrier layer 311 is formed at times t10 to t11 when the substrate temperature is set to Ta. Next, the substrate temperature is lowered until the substrate temperature Tb is reached at times t11 to t12. From time t12 to time t13, the first well layer 321 is formed at the substrate temperature Tb. Thereafter, the substrate temperature is increased until the substrate temperature Ta is reached at times t13 to t20, and the second barrier layer 312 is formed at times t20 to t21. The substrate temperature is lowered until the substrate temperature Tb is reached from time t21 to t22, and the second well layer 322 is formed at the substrate temperature Tb from time t22 to time t30. Similarly, the barrier layers 31 and the well layers 32 are alternately formed at the substrate temperature Ta and the substrate temperature Tb, respectively. Then, the nth barrier layer 31n is formed at the substrate temperature Ta at time tn0 to tn1, the substrate temperature is lowered until the substrate temperature Tb is reached at time tn1 to tn2, and the nth well layer 32n is formed at time tn2 to time tn3. Thus, a laminated structure in which the barrier layers 31 and the well layers 32 are alternately laminated is completed. When the substrate temperature is raised or lowered, the barrier layer 31 or the well layer 32 can be grown or the growth can be interrupted.

When forming the barrier layer 31, for example, TMG gas and NH ₃ gas are supplied to the processing apparatus for film formation as source gases. On the other hand, when forming the well layer 32, for example, TMG gas, trimethylindium (TMI) gas, and NH ₃ gas are supplied to the processing apparatus as source gases. TMG gas is supplied as Ga atom source gas, TMI gas is supplied as In atom source gas, and NH ₃ gas is supplied as nitrogen atom source gas.

  An active layer 3 shown in FIG. 9 is formed by forming a non-doped GaN film of about 10 nm as the final barrier layer 310 on the formed laminated structure. As already described, the film thickness d0 of the final barrier layer 310 is set to a thickness at which the p-type dopant diffused from the p-type semiconductor layer 4 to the active layer 3 does not reach the well layer 32 of the active layer 3.

Next, the substrate temperature is set to about 800 ° C. to 1000 ° C., and the p-type semiconductor layer 4 doped with the p-type dopant is formed on the final barrier layer 310 to about 0.05 to 1 μm. As the p-type semiconductor layer 4, for example, a GaN layer doped with Mg as a p-type dopant at a concentration of about 3 × 10 ¹⁹ cm ⁻³ can be employed. In the case of doping Mg, TMG gas, NH ₃ gas and biscyclopentadienyl magnesium (Cp ₂ Mg) gas are supplied as source gases to form the p-type semiconductor layer 4. Mg diffuses from the p-type semiconductor layer 4 to the active layer 3 when the p-type semiconductor layer 4 is formed, but the final barrier layer 310 prevents Mg from diffusing into the well layer 32 of the active layer 3.

  Next, part of the p-type semiconductor layer 4 to the n-type semiconductor layer 2 is removed by mesa etching by reactive ion etching or the like to expose the surface of the n-type semiconductor layer 2. Thereafter, an n-side electrode 200 is formed on the exposed surface of the n-type semiconductor layer 2 by vapor deposition, and a p-side electrode 100 is formed on the p-type semiconductor layer 4 by vapor deposition, thereby completing the semiconductor light emitting device shown in FIG. To do.

  According to the semiconductor light emitting device and the method for manufacturing the same according to the second embodiment, the p type diffuses the thickness d0 of the final barrier layer 310 in contact with the p type semiconductor layer 4 from the p type semiconductor layer 4 to the active layer 3. By setting the thickness so that the dopant does not reach the well layer 32 of the active layer 3, the p-type dopant is prevented from diffusing into the well layer 32 of the active layer 3. As a result, it is possible to manufacture a semiconductor light emitting device in which deterioration of quality is suppressed without causing a decrease in light luminance due to diffusion of the p-type dopant into the well layer 32.

[Third embodiment]
As shown in FIG. 14, the semiconductor light emitting device according to the third embodiment of the present invention includes an n-type semiconductor layer 2 doped with an n-type dopant, and an n-type semiconductor layer disposed on the n-type semiconductor layer. A block layer 7 doped with an n-type dopant at a lower concentration, an active layer 3 disposed on the block layer 7, and a p-type semiconductor layer 4 disposed on the active layer 3 are provided.

  As the substrate 1 shown in FIG. 14, for example, a sapphire substrate can be employed. A group III nitride semiconductor can be employed for each of the n-type semiconductor layer 2, the block layer 7, the active layer 3, and the p-type semiconductor layer 4, and the n-type semiconductor layer 2, the block layer 7, and the active layer 3 are formed on the substrate 1. And the p-type semiconductor layer 4 are sequentially stacked.

  The n-type semiconductor layer 2 supplies electrons to the active layer 3, and the p-type semiconductor layer 4 supplies holes to the active layer 3. Light is generated by the recombination of the supplied electrons and holes in the active layer 3.

  As the n-type semiconductor layer 2, a group III nitride semiconductor having a thickness of about 0.2 to 5 μm doped with silicon (Si) as an n-type dopant, for example, a GaN layer or the like can be used. As the p-type semiconductor layer 4, a group III nitride semiconductor doped with a p-type dopant and having a thickness of about 0.05 to 1 μm, for example, a GaN layer can be employed. As the p-type dopant, magnesium (Mg), zinc (Zn), cadmium (Cd), calcium (Ca), beryllium (Be), carbon (C), or the like can be used.

The block layer 7 disposed between the n-type semiconductor layer 2 and the active layer 3 is a group III nitride having a film thickness of about 50 to 500 nm, for example, 200 nm, doped with Si as an n-type dopant to less than 1 × 10 ¹⁷ cm ^−3. A physical semiconductor such as a GaN layer can be employed.

  The active layer 3 has a quantum well structure in which the well layer 32 is sandwiched between barrier layers 31 having a larger band gap than the well layer 32. The active layer 3 may have a quantum well structure in which a well layer is sandwiched between barrier layers as a unit structure, and may have a multiple quantum well (MQW) structure in which this unit structure is stacked n times (n: natural number). In the case of the MQW structure, the active layer 3 includes, for example, a first well layer 321 to an nth well layer sandwiched between a first barrier layer 311 to an nth barrier layer 31n and a final barrier layer 310, as shown in FIG. 32n. Specifically, the first well layer 321 is disposed between the first barrier layer 311 and the second barrier layer 312, and the second well layer (not shown) is the second barrier layer 312 and the third barrier layer (not shown). ). The nth well layer 32n is disposed between the nth barrier layer 31n and the final barrier layer 310. The first barrier layer 311 of the active layer 3 is disposed on the block layer 7, and the p-type semiconductor layer 4 is disposed on the final barrier layer 310 of the active layer 3.

  The barrier layer 31 is made of, for example, a GaN film, and the well layer 32 is made of, for example, an indium gallium nitride (InGaN) film. Note that the composition ratio of indium (In) in the well layer 32 is appropriately set according to the wavelength of light to be generated. As the barrier layer 31, an InGaN film having a smaller In composition than the well layer 32 may be employed.

  The semiconductor light emitting device shown in FIG. 14 further includes an n-side electrode 200 that applies a voltage to the n-type semiconductor layer 2 and a p-side electrode 100 that applies a voltage to the p-type semiconductor layer 4. As shown in FIG. 14, an n-side electrode is formed on the surface of the n-type semiconductor layer 2 exposed by mesa etching in a partial region of the p-type semiconductor layer 4, the active layer 3, the block layer 7, and the n-type semiconductor layer 2. 200 is arranged. The p-side electrode 100 is disposed on the p-type semiconductor layer 4. The n-side electrode 200 is made of, for example, an aluminum (Al) film, and the p-side electrode 100 is made of, for example, a titanium (Ti) film, a nickel (Ni) film, an indium tin oxide (ITO) film, or a zinc oxide (ZnO) film. Or the like, or a palladium (Pd) -gold (Au) alloy film. The n-side electrode 200 is ohmically connected to the n-type semiconductor layer 2, and the p-side electrode 100 is ohmically connected to the p-type semiconductor layer 4.

In the semiconductor light emitting device shown in FIG. 14, for example, when the n-type semiconductor layer 2 is doped with Si by about 3 × 10 ¹⁸ cm ^−3, the block layer 7 doped with Si by about 8 × 10 ¹⁶ cm ⁻³ is used. By disposing between the n-type semiconductor layer 2 and the active layer 3, it is possible to prevent diffusion of Si from the n-type semiconductor layer 2 to the active layer 3 in the process of forming the active layer 3 and the manufacturing process after that process. Furthermore, when a bias is applied between the n-type semiconductor layer 2 and the p-type semiconductor layer 4 to cause the active layer 3 to emit light, electrons supplied from the n-type semiconductor layer 2 to the active layer 3 cause the active layer 3 to An overflow that passes through and reaches the p-type semiconductor layer 4 can be prevented, and a decrease in luminance of light output from the semiconductor light emitting element can be prevented.

The Si concentration of the block layer 7 is less than 1 × 10 ¹⁷ cm ⁻³ . This is because when the Si concentration of the block layer 7 is too high, excess electrons are supplied from the n-type semiconductor layer 2 to the active layer 3, and the electrons overflow into the p-type semiconductor layer 4. This is because the brightness of the light to be reduced decreases. On the other hand, when the Si concentration of the block layer 7 is too low, electrons cannot be supplied into the active layer 3. Therefore, the Si concentration of the block layer 7 is preferably 1 × 10 ¹⁶ to 1 × 10 ¹⁷ cm ⁻³ .

FIG. 16 shows an example of the relationship between the Si concentration of the block layer 7 when the film thickness is 200 nm and the output PO of light output from the semiconductor light emitting element. As shown in FIG. 17, the output PO is maximized when the Si concentration is about 5 × 10 ¹⁶ cm ⁻³ , and the output PO is reduced by setting the Si concentration to about 1 × 10 ¹⁶ to 1 × 10 ¹⁷ cm ^−3. It can be 97% or more of the maximum output.

  As described above, in the semiconductor light emitting device according to the third embodiment, the block layer 7 is disposed between the n-type semiconductor layer 2 and the active layer 3, thereby allowing the n-type semiconductor layer 2 during the manufacturing process. Diffusion of Si from the active layer 3 to the active layer 3 and overflow of electrons from the n-type semiconductor layer 2 to the p-type semiconductor layer 4 can be prevented, and a decrease in luminance of light output from the semiconductor light emitting element can be prevented. As a result, deterioration of the quality of the semiconductor light emitting device shown in FIG. 14 can be prevented.

  Hereinafter, an example of a method for manufacturing the semiconductor light emitting element shown in FIG. 14 will be described. In addition, the manufacturing method of the semiconductor light emitting element described below is an example, and it is needless to say that it can be realized by various other manufacturing methods including this modification. Here, Si is adopted as the n-type dopant.

As a manufacturing method, GaN is grown on a substrate 1 such as a sapphire substrate by a well-known metal organic chemical vapor deposition (MOCVD) method or the like. For example, after the substrate 1 is thermally cleaned, the substrate temperature is set to about 1000 ° C., and an n-type semiconductor layer 2 is formed on the substrate 1 as a GaN film doped with Si at a concentration of about 3 × 10 ¹⁸ cm ^−3. Is grown about 0.2 to 5 μm. At this time, trimethylgallium (TMG), ammonia (NH ₃ ) and silane (SH ₄ ) are supplied as source gases to form the n-type semiconductor layer 2.

Next, a GaN film doped with Si at a concentration of less than 1 × 10 ¹⁷ cm ⁻³ , for example, about 8 × 10 ¹⁶ cm ^{−3 is} grown as a block layer 7 on the n-type semiconductor layer 2 by about 200 nm. At this time, the same source gas as in the case where the n-type semiconductor layer 2 is formed can be applied.

  Next, for example, barrier layers 31 made of a GaN film and well layers 32 made of an InGaN film are alternately laminated to form the active layer 3 on the block layer 7. Specifically, while adjusting the substrate temperature and the flow rate of the source gas when forming the active layer 3, the barrier layers 31 and the well layers 32 are grown alternately and continuously, and the barrier layers 31 and the well layers 32 are stacked. Thus formed active layer 3 is formed. In the case where the active layer 3 has an MQW structure, the step of laminating the well layer 32 and the barrier layer 31 having a larger band gap than the well layer 32 by adjusting the substrate temperature and the flow rate of the source gas is defined as a unit step. Repeated n times, for example, about 8 times, to obtain a laminated structure in which the barrier layers 31 and the well layers 32 are alternately laminated.

  FIG. 17 shows an example in which the barrier layer 31 and the well layer 32 are stacked. The barrier layer 31 is formed at the substrate temperature Ta shown in FIG. 17, and the well layer 32 is formed at the substrate temperature Tb.

  That is, the first barrier layer 311 is formed at times t10 to t11 when the substrate temperature is set to Ta. Next, the substrate temperature is lowered until the substrate temperature Tb is reached from time t11 to t12, and the first well layer 321 is formed at the substrate temperature Tb from time t12 to time t13. Thereafter, the substrate temperature is increased until the substrate temperature Ta is reached at times t13 to t20, and the second barrier layer 312 is formed at times t20 to t21. Similarly, the barrier layers 31 and the well layers 32 are alternately formed at the substrate temperature Ta and the substrate temperature Tb, respectively. Then, the nth barrier layer 31n is formed at time tn0 to tn1, the substrate temperature is lowered until the substrate temperature Tb is reached at time tn1 to tn2, and the nth well layer 32n is formed at time tn2 to time tn3. Then, the substrate temperature is raised until the substrate temperature Ta is reached at times tn3 to te0, and the final barrier layer 310 is formed at times te0 to te1 to complete the active layer 3. When the substrate temperature is raised or lowered, the barrier layer 31 or the well layer 32 can be grown or the growth can be interrupted.

When forming the barrier layer 31, for example, TMG gas and NH ₃ gas are supplied to the processing apparatus for film formation as source gases. On the other hand, when forming the well layer 32, for example, TMG gas, trimethylindium (TMI) gas, and NH ₃ gas are supplied to the processing apparatus as source gases. TMG gas is supplied as Ga atom source gas, TMI gas is supplied as In atom source gas, and NH ₃ gas is supplied as nitrogen atom source gas.

Next, the substrate temperature is set to about 800 ° C. to 1000 ° C., and the p-type semiconductor layer 4 doped with the p-type dopant is formed on the active layer 3 to about 0.05 to 1 μm. As the p-type semiconductor layer 4, for example, a GaN layer doped with Mg as a p-type dopant at a concentration of about 3 × 10 ¹⁹ cm ⁻³ can be employed. In the case of doping Mg, TMG gas, NH ₃ gas and biscyclopentadienyl magnesium (Cp ₂ Mg) gas are supplied as source gases to form the p-type semiconductor layer 4.

  Next, part of the p-type semiconductor layer 4 to the n-type semiconductor layer 2 is removed by mesa etching by reactive ion etching or the like to expose the surface of the n-type semiconductor layer 2. Thereafter, an n-side electrode 200 is formed on the exposed surface of the n-type semiconductor layer 2 by vapor deposition, and a p-side electrode 100 is formed on the p-type semiconductor layer 4 by vapor deposition, thereby completing the semiconductor light emitting device shown in FIG. To do. Note that after the p-side electrode 100 is formed, mesa etching for disposing the n-side electrode 200 may be performed.

According to the method for manufacturing a semiconductor light emitting element according to the embodiment of the present invention as described above, the block layer 7 having an Si concentration of less than 1 × 10 ¹⁷ cm ⁻³ is formed between the n-type semiconductor layer 2 and the active layer 3. Thus formed, the diffusion of Si from the n-type semiconductor layer 2 to the active layer 3 in the manufacturing process and the overflow of electrons from the n-type semiconductor layer 2 to the p-type semiconductor layer 4 during light emission are prevented. For this reason, it is possible to manufacture a semiconductor light-emitting element in which deterioration of quality is suppressed without a decrease in light luminance.

[Other embodiments]
As described above, the present invention has been described with reference to the first to third embodiments. However, the description and the drawings that form a part of this disclosure are exemplary and limit the present invention. Should not be understood. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  In the description of the embodiment already described, the active layer 3 has a MQW structure having a plurality of well layers 32 sandwiched between the barrier layers 31. However, the active layer 3 has one well layer 32. The film thickness d0 of the final barrier layer 310 disposed between the well layer 32 and the p-type semiconductor layer 4 may be larger than the Mg diffusion distance.

  Alternatively, the final barrier layer 310 may have a structure in which the film thickness d0 is thicker than the barrier layer 31 disposed between the well layer 32 and the n-type semiconductor layer 2.

  As described above, the present invention includes various embodiments that are not described herein.

  The semiconductor light emitting device and the manufacturing method thereof of the present invention can be used for all semiconductor light emitting devices such as LED devices and LD devices having a quantum well structure.

Claims (16)

an n-type nitride semiconductor layer;
a p-type nitride semiconductor layer;
Between the n-type nitride semiconductor layer and the p-type nitride semiconductor layer, a barrier layer made of GaN and a well layer made of In _x Ga _1-x N (0 <x <1) An active layer containing In having a multiple quantum well structure, wherein the number of pairs of the multiple quantum well layers is 6 to 11. 2. The semiconductor light emitting device according to claim 1, wherein the well layer has a thickness of 2 to 3 nm, and the barrier layer has a thickness of 7 to 18 nm. an n-type semiconductor layer;
An active layer disposed on the n-type semiconductor layer and having a stacked structure in which barrier layers and well layers having a smaller band gap than the barrier layers are alternately disposed;
A p-type semiconductor layer including a p-type dopant disposed on the active layer, and a film thickness of a final barrier layer of an uppermost layer of the stacked structure of the active layers diffuses the final barrier layer of the p-type dopant The concentration of the p-type dopant in the final barrier layer gradually decreases from the first main surface of the final barrier layer in contact with the p-type semiconductor layer along the film thickness direction of the final barrier layer. A semiconductor light-emitting element, wherein a concentration of the p-type dopant is less than 1 × 10 ¹⁶ cm ^{−3 on a} second main surface facing the surface.   4. The semiconductor light emitting device according to claim 3, wherein the n-type semiconductor layer, the active layer, and the p-type semiconductor layer are made of a group III nitride semiconductor.   The semiconductor light emitting device according to claim 4, wherein the final barrier layer is a gallium nitride film.   The semiconductor light-emitting device according to claim 3, wherein the p-type dopant is magnesium. an n-type semiconductor layer doped with an n-type dopant;
A block layer disposed on the n-type semiconductor layer and doped with the n-type dopant at a lower concentration than the n-type semiconductor layer;
An active layer disposed on the block layer;
And a p-type semiconductor layer disposed on the active layer.   8. The semiconductor light emitting device according to claim 7, wherein the n-type semiconductor layer, the block layer, the active layer, and the p-type semiconductor layer are made of a group III nitride semiconductor.   9. The semiconductor light emitting device according to claim 7, wherein the n-type dopant is silicon. The semiconductor light emitting device according to claim 9, wherein the silicon concentration of the block layer is less than 1 × 10 ¹⁷ cm ⁻³ .   11. The active layer according to claim 7, wherein the active layer has a stacked structure in which a plurality of barrier layers and a plurality of well layers having a band gap smaller than the barrier layers are alternately arranged. Semiconductor light emitting device. forming an n-type semiconductor layer;
Forming an active layer by alternately laminating a barrier layer and a well layer having a smaller band gap than the barrier layer on the n-type semiconductor layer;
Forming a p-type semiconductor layer containing a p-type dopant on the active layer, and diffusing the final barrier layer of the p-type dopant in the final barrier layer of the active layer in contact with the p-type semiconductor layer A method of manufacturing a semiconductor light emitting element, wherein the semiconductor light emitting element is formed thicker than a distance.   Forming the final barrier layer with such a thickness that the p-type dopant contained in the p-type semiconductor layer does not diffuse to the second main surface facing the first main surface of the final barrier layer in contact with the p-type semiconductor layer. The method of manufacturing a semiconductor light emitting element according to claim 12.   14. The method for manufacturing a semiconductor light emitting device according to claim 12, wherein the n-type semiconductor layer, the active layer, and the p-type semiconductor layer are formed of a group III nitride semiconductor.   The method of manufacturing a semiconductor light emitting element according to claim 14, wherein the final barrier layer is a non-doped gallium nitride film.   The method for manufacturing a semiconductor light emitting element according to claim 12, wherein the p-type dopant is magnesium.

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