JPWO2007034822A1 - Image generation device - Google Patents

Abstract

An object of the present invention is to provide an image generation apparatus capable of performing image generation processing in a unified manner when generating a final image including a vector image and a plurality of image layers. The image generation apparatus (1) of the present invention includes an edge information storage memory (2), a vector data storage memory (3), an edge information generation unit (4), a layer image storage memory (5), and the edge information. When painting the inside of the image defined in the vector format using the edge information stored in the storage memory, the image information on the background and the image information for each layer stored in the layer image storage memory are read out, An image composition unit (6) that performs image composition in units of pixels by superimposing the format image and image information for each layer and performing image processing operations in units of pixels, and a result image storage memory (7) are provided.

Description

  The present invention relates to an image generation apparatus that generates computer graphics. More specifically, the present invention relates to an image generation apparatus that can simultaneously perform image composition at the time of painting after rendering, a computer using such an image generation apparatus, and the like.

  In recent years, computer graphics systems (image generation devices) have been installed and used not only in stationary devices such as arcade game machines and desktop computers, but also in mobile phones and portable game machines. .

  In particular, an image generation apparatus mounted on a portable device is required to have a smaller physical size and lower power consumption than those used in a conventional stationary apparatus. Furthermore, it is expected to generate an effective image under such restrictions.

  In a conventional image generation method in computer graphics, an edge portion is first rendered by a renderer. FIG. 19A shows an example of an image after rendering. That is, after the renderer obtains a rendering image as shown in FIG. 19 (a), the renderer scans line by line from the upper part of the screen, for example, and fills a predetermined area inside the image. FIG. 19 (b) is a diagram showing an example of an image after painting. As shown in FIG. 19 (b), a predetermined area of the rendered image shown in FIG. 19 (a) is filled. After that, the images displayed on the screen include images of various layers such as background images and images that come before the background. Therefore, processing such as geometric calculation and color correction is performed on each layer image. After that, processing such as hidden surface removal processing is performed to synthesize the display image.

  FIG. 20 is a diagram illustrating an example of each layer image of an image displayed on a certain mobile phone. As shown in FIG. 20, images displayed on a mobile phone or the like include a background image (layer 0), a header image (layer 1), a footer image (layer 2), a video image (layers 3 and 4), and a game. Are formed by combining computer graphics images (layer 5). Conventionally, after rendering, painting is performed, and then image composition is performed.

  In recent years, image generation apparatuses have also been used for user interface display in computers, and it is required to generate images quickly and highly under the demand for reducing power consumption.

  Under such a requirement, Japanese Patent Laid-Open No. 2003-143419 (Patent Document 1) discloses drawing data to be drawn in accordance with a plurality of graphic data in order to perform high-speed and accurate color correction / color conversion. A data storage unit that stores intermediate data, an edge generation unit that extracts each graphic data from the stored intermediate data, and obtains an edge with a predetermined scan line width for each graphic data, and between each generated graphic data For the drawing color at each edge of the sorted edge sequence and the rendering unit having the graphic overlap elimination processing means for eliminating the overlap of edges, the edge sort processing means for performing the sort processing on the edge sequence from which the overlap has been eliminated, An image processing apparatus including a color correction / color conversion unit that performs color correction / color conversion is disclosed.

  The invention described in Japanese Patent Application Laid-Open No. 2003-143419 is adapted to perform color correction / color conversion on rasterized data with respect to a minimum portion using vector information. Although color correction / color conversion processing is performed simultaneously with vector image generation processing, vector image generation and image synthesis processing are not performed in a centralized manner.

  Further, Japanese Patent Laid-Open No. 2000-172870 discloses that an image processing apparatus that draws a three-dimensional object according to a polygon model in order to draw a polygon edge with a specified width without using line drawing but only with a triangle drawing algorithm. The edge width and edge mode are stored in the register of the drawing controller along with the vertex coordinate value and color value of the triangle unit geometrically processed from the host PC.The processor starts when the triangle drawing start flag is written from the PC, and draw command Is read via the bus controller, the data in the register is read, the triangle drawing operation (pixel expansion) is performed, and the result is written to the frame buffer and Z buffer. Normal triangle for each horizontal span of the triangle It performs overall fill. Meanwhile, if the mode is 1, seeking the end of the edge width of, performs filling from the start point to the edge width end point. "Such techniques have been disclosed.

  The invention disclosed in Japanese Patent Laid-Open No. 2000-172870 implements drawing a line using vector information by a triangle algorithm, and does not perform image composition during vector image generation processing.

  Japanese Patent Laid-Open No. 2000-69275 discloses edge enhancement for a black line image that predetermines a boundary when specifying an editing area by marker processing or the like and performing a process of filling the area surrounded by the boundary line. A technique is disclosed in which the black image density near the boundary is increased to narrow the gap between the black line image and the filled image at the boundary and make it difficult to recognize the white spots near the boundary. However, this technique relates to an anti-aliasing technique for generating a vector format image, and does not perform image composition during vector image generation processing.

  Japanese Patent Application Laid-Open No. 6-68271 discloses a technique for shortening the processing time without reducing the effect of the anti-aliasing processing when the region surrounded by the edge of the vector image is filled. However, image synthesis is not performed during vector image generation processing.

  In addition, Japanese Patent Laid-Open No. 2000-172858 discloses a contour of a graphic to be drawn in order to be able to deal with complex graphics without imposing a load on the system when converting vector data into edge data. A drawing unit 2 for recognizing coordinates that are intersections of vector data to be represented and a scan line, a drawing coordinate storage unit L1 for storing coordinate data indicating coordinates recognized by the drawing unit 2, and coordinates recognized by the drawing unit 2 A vector number determining means 3 for calculating the number for each scan line, and determining whether or not the calculated coordinate number exceeds the number of coordinate data of one scan line previously assigned to the drawing coordinate storage unit L1, A control unit 5 that secures a drawing coordinate storage unit L2 capable of storing the number of coordinate data determined to exceed, and an edge list region switching unit that stores coordinate data in the secured storage region An image generation device comprising stage 6 is disclosed.

  This technique relates to a technique for generating an edge portion when generating a vector graphics image, and does not perform image composition when forming a vector format image.

  In the conventional image generation apparatus described so far, the vector image generation unit and the image synthesis unit are separated, and these processes are realized by hardware or a combination of hardware and software. However, in the image generation apparatus in which the vector image generation unit and the image composition unit are divided in this way, when generating the final image, after generating the vector image, the image just generated and the background and other images Combining is required, and unnecessary memory access occurs, resulting in waste in terms of performance and power consumption. In addition, these synchronous controls are required, which complicates the system.

Japanese Patent Laid-Open No. 2003-143419

  The present invention has been made in view of the above-described problems, and provides an image generation apparatus capable of performing image generation processing in an integrated manner when generating a final image including a vector image and a plurality of image layers. Objective.

  The present invention provides an image generation apparatus that can perform a single image generation process when generating a final image including a vector image and a plurality of image layers, so that performance is high, power consumption is low, and system complexity is reduced. This is a different purpose from the above.

  The present invention basically reads out image information for each layer stored in the layer image storage memory when the inside of the image is painted using edge information, and obtains a vector format image and image information for each layer. The knowledge that it is possible to provide an image generation system with high performance, low power consumption, and minimal system complexity by performing image processing operations in units of pixels simultaneously instead of separately. It is based on.

  That is, the image generation device (1) according to the first aspect of the present invention includes an edge information storage memory (2) for storing polygon edge information in a certain pixel, and a vector format rasterization result. Based on the vector data storage memory (3) and the rasterization result in the vector format stored in the vector data storage memory, an edge for performing processing for writing the edge information of the image as the rasterization result to the edge information storage memory An information generation unit (4), a layer image storage memory (5) for storing at least background-related image information and image information for each of a plurality of layers, and edge information stored in the edge information storage memory, When painting the inside of the image defined in (3), the image information and record related to the background stored in the layer image storage memory. An image composition unit (6) that reads out image information for each ear, superimposes image information in a vector format and image information for each layer, and performs image processing operation in units of pixels to perform image synthesis in units of pixels; and The present invention relates to an image generation apparatus including a result image storage memory (7) for storing an image synthesized by a synthesis unit.

  The image generation apparatus according to the first aspect of the present invention includes an image composition unit (6) that simultaneously performs image processing in vector format and processing for superimposing image information for each layer. For example, when a vector image is formed, image composition can be performed.

  As described above, vector-format image processing and layer-by-layer image information overlap are basically different processes, and it is common knowledge to perform separate processing as in the prior art. Like the image generation apparatus of the present invention, the processing is simultaneously performed by the image composition unit (6), so that the memory access amount is reduced, and as a result, the power consumption can be reduced.

  In addition, by performing these processes with a single image composition unit (6), it is possible to prevent the system from becoming complicated. In particular, when the image composition unit (6) is implemented by hardware, sharing the circuit elements can effectively prevent a situation where the hardware scale increases. In addition, if software control is complicated, it is possible to effectively prevent a situation where the system is complicated and to achieve quick processing.

  According to the present invention, it is possible to provide an image generation apparatus capable of performing image generation processing in a unified manner when generating a final image including a vector image and a plurality of image layers.

  According to the present invention, when generating a final image including a vector image and a plurality of image layers, it is possible to perform image generation processing in a unified manner, so that an image generating apparatus that has high performance, low power consumption, and reduced system complexity. Can be provided.

  In a preferred embodiment of the present invention, a blending factor for synthesizing the surface color is combined with the shading result of a single light source or a plurality of light sources for a specific pixel to generate a surface color after blending for at least two layers, Synthesize. As a result, according to the present invention, luminance calculation can be performed without considering incident light to pixels other than a specific pixel, and therefore, for computer graphics that can calculate shadows and the like at high speed. A multilayer reflection shading image generation method and a computer can be provided.

FIG. 1 is a schematic diagram showing a basic configuration of an image generation apparatus according to the first aspect of the present invention. FIG. 2 is a diagram for explaining the flow of an image obtained by the image generation apparatus according to the first aspect of the present invention. FIG. 2 (a) is a diagram showing an example of polygon shape data defined in the vector format stored in the vector data storage memory. FIG. 2B is a diagram showing an example of data including edge information of an image as a rasterization result written in the edge information storage memory. FIG. 2 (c) is a diagram showing an example of a synthesized image synthesized by the image synthesis unit and stored in the result image storage memory (7). FIG. 3 is a block diagram illustrating a configuration example of the edge information generation unit. FIG. 4 is a block diagram illustrating a configuration example of the image composition unit. FIG. 5 is a diagram for explaining the process of image composition performed in the image composition unit. FIG. 6 is a block diagram of the anti-aliasing circuit according to the first embodiment of the present invention. FIG. 7 is a diagram illustrating an example of polygon edges and sampling points in a certain pixel. FIG. 8 is a diagram showing another example of polygon edges and sampling points in a certain pixel. FIG. 9 is a diagram showing another example of polygon edges and sampling points in a certain pixel. FIG. 10 is a diagram showing another example of polygon edges and sampling points in a certain pixel. FIG. 11 is a block diagram of an anti-aliasing circuit according to the second embodiment of the present invention. FIG. 12 is a flowchart for explaining an example of the painting process in the present invention. FIG. 13 is a block diagram showing an embodiment (computer) of the present invention. FIG. 14 is a block diagram of an embodiment (game machine) according to the present invention. FIG. 15 is a block diagram of an embodiment of the present invention (a mobile phone with a computer graphic function). FIG. 16 is a block diagram of an embodiment (navigation system) of the present invention. FIG. 17 is a block diagram showing the main control circuit 361 of the pachislot machine. FIG. 18 is a block diagram showing a sub control circuit of the pachislot machine. FIG. 19 is a diagram for explaining rendering and filling. FIG. 19A shows an example of an image after rendering. FIG. 19 (b) is a diagram showing an example of an image after painting. FIG. 20 is a diagram illustrating an example of each layer image of an image displayed on a certain mobile phone.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Image generation apparatus 2 Edge information storage memory 3 Vector data storage memory 4 Edge information generation part 5 Layer image storage memory 6 Image composition part 7 Result image storage memory

[Basic configuration and basic operation of image generator]
FIG. 1 is a schematic diagram showing a basic configuration of an image generation apparatus according to the first aspect of the present invention. As shown in FIG. 1, an image generation apparatus (1) according to a first aspect of the present invention includes an edge information storage memory (2) for storing polygon edge information in a certain pixel, and vector format rasterization. Based on the vector data storage memory (3) for storing the result and the rasterization result in the vector format stored in the vector data storage memory, the edge information of the image as the rasterization result is written to the edge information storage memory An edge information generator (4) for performing processing, a layer image storage memory (5) for storing at least image information relating to the background and image information for each of a plurality of layers, and edge information stored in the edge information storage memory When painting the inside of an image defined in vector format, the background image stored in the layer image storage memory is used. An image composition unit (6) that reads out the information and image information for each layer, superimposes the image in vector format and the image information for each layer, and performs image processing for each pixel to perform image composition for each pixel; And a result image storage memory (7) for storing the image synthesized by the image synthesis unit.

  The basic operation of the image generating apparatus will be described with reference to the drawings. FIG. 2 is a diagram for explaining the flow of an image obtained by the image generation apparatus according to the first aspect of the present invention. FIG. 2 (a) is a diagram showing an example of polygon shape data defined in the vector format stored in the vector data storage memory. FIG. 2B is a diagram showing an example of data including edge information of an image as a rasterization result written in the edge information storage memory. FIG. 2 (c) is a diagram showing an example of a synthesized image synthesized by the image synthesis unit and stored in the result image storage memory (7).

  The edge information storage memory (2) stores polygon edge information at a certain pixel. For example, polygon edge information defined by user input and polygon edge information calculated based on a predetermined calculation are stored in a writable manner. A vector data storage memory (3) stores polygon shape data defined in a vector format, for example. That is, as shown in FIG. 2 (a), polygon data defined in vector format is stored in the vector data storage memory (3). In FIG. 2A, 11 is an example of a two-dimensional memory space of the vector data storage memory. The vector data storage memory (3) stores vector shape data (12) defined by functions such as coordinate position information about polygon shapes and Bezier free curves, not in units of pixels.

  The edge information generation unit (4) performs rasterization processing based on the shape data in the vector format stored in the vector data storage memory, and writes the edge information of the image as the rasterization result in the edge information storage memory. Specifically, pixel information such as position information, inclination information, and direction information of an edge portion having a vector shape is obtained by rasterization processing, and information stored in the edge information storage memory is updated. FIG. 2B is a diagram showing an example of data including edge information of an image as a rasterization result written in the edge information storage memory. In FIG. 2B, 14 is an example of a two-dimensional memory space (for each pixel) of the edge information storage memory. In this example, polygon vector shape data (12) is converted into edge pixels (13) in pixel units, and this information is transmitted to the edge information storage memory (2). Then, the edge information stored in the edge information storage memory (2) is updated.

  The layer image storage memory (5) stores at least image information relating to the background and image information for each of a plurality of layers. When the image composition unit (6) uses the edge information stored in the edge information storage memory (2) to paint the inside of the image defined in the vector format, the image composition unit (6) relates to the background stored in the layer image storage memory. Read out one or more of the image information and image information for each layer, superimpose the vector image (or edge information such as edge pixel (13)) and the image information for each layer, Image synthesis is performed in units of pixels by performing image processing operations in units. The result image storage memory (7) stores the image information synthesized by the image synthesis unit (6). FIG. 2 (c) is a diagram showing an example of a synthesized image synthesized by the image synthesis unit and stored in the result image storage memory (7). Specifically, as shown in FIG. 2 (c), the image composition unit refers to the edge information, the layer image information stored in the layer image storage memory (5), etc. 15), an edge portion pixel (preferably an antialiased edge pixel) (16) of the vector area, and a layer image pixel (17) are obtained. Then, the obtained composite image information is transmitted to the result image storage memory (7), and the result image storage memory (7) updates the storage information based on the information. As a result, the memory space (18) of the result image storage memory (7) was classified into pixel area fill pixels (15), antialiased edge pixels (16), and layer image pixels (17) for each pixel. The composite image information is stored. Each element will be described below.

[Image generation device]
The image generation apparatus (1) is realized as a computer system used for three-dimensional computer graphics or the like, a circuit, a chip, or the like for generating such a three-dimensional computer image. Each element constituting the image generating apparatus (1) of the present invention is connected by a bus or the like so that information can be exchanged.

[Edge information storage memory]
The edge information storage memory (2) is a memory for storing polygon edge information in a certain pixel. The edge information storage memory is realized by a recording device such as a hard disk, a buffer, or a RAM. In the edge information storage memory, for example, polygon edge information defined by input from the user and polygon edge information calculated based on a predetermined calculation are stored so as to be writable.

[Vector data storage memory]
The vector data storage memory (3) is a memory for storing polygonal shape data in vector format. The vector data storage memory is realized by a recording device such as a hard disk, a buffer, or a RAM. The rasterization result in vector format is information obtained by a known rasterization circuit, and the corresponding frame buffer address is calculated from the position information in the screen coordinate system of the vertex of the polygon, which is a point in the three-dimensional space. It can be obtained by extracting the corresponding texture texel (pixel) from the texture coordinate information of the vertex. The information stored in the vector data storage memory (3) is, for example, polygon shape data defined in a vector format. Preferably, the edge information storage memory (2) stores coordinate position information and vector shape data defined by a predetermined function such as a Bezier free curve, not as pixels.

  The vector data storage memory is preferably one that stores information as stream format data. In order to store in such a stream format, the data may be returned to stream format data by the stream data generation circuit before the information is stored in the vector data storage memory. Since the information is stored in a stream format, the information can be read out effectively.

[Edge information generator]
An edge information generation unit (4) is a device for performing rasterization processing based on vector shape data stored in a vector data storage memory, and writing out the edge information of the image as the rasterization result to the edge information storage memory It is.

  FIG. 3 is a block diagram illustrating a configuration example of the edge information generation unit. As shown in FIG. 3, the edge information generation unit (4) performs command analysis of the vector shape data (12) read from the vector data storage memory (3), and the entire edge information generation unit (4). A command control unit (21) for controlling processing, and a rasterization unit for performing rasterization processing using shape data in vector format stored in a vector data storage memory in accordance with a control signal of the command control unit (21) (22), an edge information calculation unit (23) for obtaining edge information using shape data in the vector format stored in the vector data storage memory according to the control signal of the command control unit (21), and edge information And an edge memory control unit (24) for transmitting information to the storage memory (2) and updating the edge information stored in the edge information storage memory.

  The command control unit (21) analyzes the command of the vector shape data (12) read from the vector data storage memory (3) and controls the entire processing of the edge information generation unit (4). This process may be performed by hardware. In addition, software and hardware may cooperate to perform processing. Specifically, a CPU or the like functioning as a command control unit (21) analyzes a command based on input information, reads a control program stored in a main memory or the like as necessary, and a control algorithm for the read control program Thus, the predetermined information may be performed using the input information. Each information may be appropriately stored in a memory such as a buffer and updated as appropriate. Of course, not only the command control unit (21) but also the edge information generation unit (4) as a whole may be processed by the cooperation of hardware and software as described above, or only by the hardware. May be.

  The rasterizing unit (22) performs rasterizing processing using the vector format shape data stored in the vector data storage memory in accordance with the control signal of the command control unit (21). More specifically, the rasterizing unit (22) generates edge information using coordinate and function data in the analyzed command.

  The edge information calculation unit (23) obtains edge information using the shape data in the vector format stored in the vector data storage memory in accordance with the control signal of the command control unit (21). More specifically, the edge information calculation unit (23) receives the rasterized edge information obtained by the rasterization unit (22), and the edge information includes the position, inclination, Edge information to which information related to one or more of direction and anti-aliasing information is added.

  The edge memory control unit (24) receives the edge information from the edge information calculation unit (23), transmits the edge information to the edge information storage memory (2), and updates the edge information stored in the edge information storage memory. In this way, data including edge information as shown in FIG. 2 (b) is stored in the edge information storage memory.

  Note that the edge information generation unit uses the vector format rasterization result stored in the vector data storage memory, and the edge information storage memory stores the edge information of the image as the rasterization result, the transparency for each pixel, and the edge portion of the pixel. In the preferred embodiment of the present invention, one or two or more of the rasterization progress codes in the horizontal direction and the vertical direction and the number of overlapping edge portions at the time of rasterization are obtained and the obtained results are written to the edge information storage memory. is there.

  By using the transparency for each pixel, it is possible to effectively perform translucent processing or the like based on the control of the image composition unit (6) during image composition. If there is a rasterization progression code for the horizontal and vertical directions at the edge of the pixel, the image composition unit (6) will send the line unit information or block unit information for each line unit or block during the subsequent image composition. It can be easily read out for each unit. Furthermore, if the number of overlapping edge portions at the time of rasterization is used, it is possible to easily determine whether or not the image composition unit (6) will perform painting in the subsequent image composition.

[Layer image storage memory]
The layer image storage memory (5) is a device for storing at least image information relating to the background and image information for each of a plurality of layers. The layer image storage memory (5) is realized by a recording device such as a hard disk, a buffer, or a RAM. Note that if the image stored in the layer image storage memory (5) is stored together with the z-coordinate and the index indicating the position in the depth direction for each layer, the position viewed from the viewpoint becomes clear. This is preferable because a culling process can be easily performed at the time of synthesis.

[Image composition part]
The image composition unit (6) uses the edge information stored in the edge information storage memory (2) to fill the interior of the image defined in the vector format and relates to the background stored in the layer image storage memory. Read out one or more of the image information and image information for each layer, superimpose the vector image (or edge information such as edge pixel (13)) and the image information for each layer, It is an apparatus for performing image synthesis in units of pixels by performing unit image processing operations. The pixel-based image processing calculation means, for example, calculation processing for synthesizing an image, and includes, for example, a pixel-based filling calculation.

  FIG. 4 is a block diagram illustrating a configuration example of the image composition unit. As shown in FIG. 4, the image composition unit (6) performs at least one of overlay processing, pixel-by-pixel calculation, translucent processing, and other raster operations, and performs pixel-by-pixel filling processing. Information to the fill processing unit (31), the line memory (32) for storing the calculation result obtained by the fill processing unit (31) for each block or line, and the result image storage memory (7), A result memory control unit (33) for updating the result image information stored in the result image storage memory (7), and an image synthesis control unit (not shown) for controlling operations in the image synthesis unit (6) Things can be raised.

  The image composition control unit controls the calculation in the image composition unit (6). This process may be performed by hardware. Realization by hardware is preferable because the processing becomes faster and power consumption is reduced. In addition, software and hardware may cooperate to perform processing. Specifically, a CPU or the like that functions as an image composition control unit analyzes a command based on input information, reads a control program stored in a main memory or the like as necessary, and according to a control algorithm of the read control program, A predetermined process may be performed using the input information. Each information may be appropriately stored in a memory such as a buffer and updated as appropriate.

  FIG. 5 is a diagram for explaining the process of image composition performed in the image composition unit. In the image composition control unit, one or more of the edge information stored in the edge information storage memory (2), the image information related to the background stored in the layer image storage memory, and the image information for each layer is stored. Entered. The image composition control unit preferably issues a command to read out the information in units of one line or block, and performs the following processing for each unit thus read out. The image composition control unit analyzes necessary information based on the input information and issues a control command to perform various arithmetic processes.

  The fill processing unit (31), for example, based on the control command, the edge information stored in the edge information storage memory (2), the background-related image information stored in the layer image storage memory, and the image information for each layer By using at least one of the two or more pieces of information and performing at least one of the overlapping processing, pixel-by-pixel calculation, translucent processing, and other raster operations, Perform fill processing. As shown in FIG. 5, the fill processing unit (31) includes, for example, the edge information stored in the edge information storage memory (2), the background image information stored in the layer image storage memory, and the layer information for each layer. One or two or more pieces of image information are input in units of lines or blocks, respectively. The fill processing unit (31) performs pixel calculation in units of pixels. The obtained information is transmitted to the line memory (32) and stored. It should be noted that by reading out the z-coordinate of each image information or an index indicating the position in the depth direction with respect to each layer from the layer image storage memory, and analyzing them, the top-to-bottom relationship of the image in pixel units is grasped, and the pixel It is a preferred embodiment of the present invention to determine the fill image (color) in units.

  For example, the line memory (32) stores the calculation result obtained by the paint processing unit (31) based on the control command. The line memory (32) is preferably stored for each block or line. Also, for example, when processing for one line unit or block unit is completed based on the control command, the result memory control unit (33) is controlled based on the information stored in the line memory (32). A result image writing request is made, the information stored in the line memory (32) is read for each unit, and transmitted to the result memory control unit (33). At this time, the line memory is classified into the pixel area area fill pixel (15), vector area edge part pixel (preferably antialiased edge pixel) (16), and layer image pixel (17). Stored.

  For example, the result memory control unit (33) sequentially updates the stored result image information based on the control command. This update is performed in units of lines or blocks as shown in FIG. 5, for example. When the writing process is completed for all the lines, the memory state as shown in FIG. 2 (c) is obtained.

[Result image storage memory]
The result image storage memory (7) is a storage device for storing the image synthesized by the image synthesis unit (6). The result image storage memory (7) is a frame buffer. After the information stored in the result image storage memory (7) is read out, it is appropriately subjected to processing such as γ correction according to the characteristics of the display device, etc., transmitted to the display device, and displayed as an image It will be. The result image storage memory preferably stores information as stream format data. In order to store in such a stream format, the stream data generation circuit may return the data to the stream format before the information is stored in the result image storage memory. Since the information is stored in a stream format, the information can be read out effectively.

  As a preferred embodiment of the image composition unit, when the inside of the image defined in the vector format is painted using the edge information stored in the edge information storage memory, an image relating to the background stored in the layer image storage memory Information and image information for each layer are read out, vector images and image information for each layer are superimposed, and pixel-by-pixel blending is performed using the transparency for each pixel stored in the edge information storage memory. Based on the rasterized signal codes in the horizontal direction and the vertical direction stored in the edge information storage memory, image synthesis processing is performed in line units or block units, and the edge portion stored in the edge information storage memory Judge whether to fill using the number of overlaps, in pixels Include those to perform the image synthesis in pixels by performing an image processing operation.

  Examples of the edge information generation unit or the image synthesis unit include an anti-aliasing processing unit such as an anti-aliasing circuit that performs anti-aliasing processing. The anti-aliasing processing unit uses an edge information in the pixel and a plurality of sampling points in the pixel to determine an area S of a portion of the pixel that is divided by the edge; Using one or more sampling points used for color synthesis from a plurality of sampling points or a color selection circuit for selecting a color at the sampling points, an area S calculated by the area calculation circuit, and a color selected by the color selection circuit An antialiasing circuit including a color synthesis circuit for determining the color of the pixel can be given.

  The image synthesizing unit may include one or both of a color space conversion processing unit and a color correction processing unit, and may perform image synthesis by performing color space conversion processing or color correction processing in units of pixels. Further, the image composition unit includes a geometric operation processing unit including one or both of image rotation processing and image size adjustment processing, and performs image composition by performing rotation processing or image size adjustment processing on the layer image. It may be a thing.

  The image synthesis unit includes a geometric calculation processing unit including one or both of image rotation processing and image size adjustment processing, the geometric calculation processing unit including a vertex data output device that outputs vertex data, and the vertex data A vertex computing device connected to an output device for performing a fixed computation on a vertex; a polygon computing device connected to the vertex computing device for performing a fixed computation on a polygon; the vertex data output device as an input source; One or more general-purpose computing devices connected to one or more of the vertex computing device and the polygon computing device, and connected to one or two of the vertex computing device and the polygon computing device at the output destination; What is a geometric calculation processing unit comprising

[Anti-aliasing circuit]
For example, a display device with a small display screen, such as a mobile phone, is not intended to display 3D CG or the like, and moreover, it is not intended to display CG subjected to anti-aliasing processing. In a preferred embodiment of the present invention, the portable display device includes an anti-aliasing circuit that performs anti-aliasing in addition to the above-described image processing. The antialiasing circuit according to this aspect will be described below. By providing this anti-aliasing circuit, it is possible to provide an anti-aliasing technique that does not greatly increase the amount of calculation for rendering, does not significantly increase the communication bandwidth between the renderer and the memory, or provides high image quality. . Also, by providing this anti-aliasing circuit, the required bandwidth for memory access for anti-aliasing is narrow and the amount of processing in rendering is small, so it is possible to provide high-quality CG images with low power consumption and small area LSI. .

[Example of anti-aliasing circuit]
The antialiasing circuit of the present invention will be described below with reference to the drawings. FIG. 6 is a block diagram of the anti-aliasing circuit according to the first embodiment of the present invention. As shown in FIG. 6, the anti-aliasing circuit (41) according to this aspect uses the edge information in the pixel and a plurality of sampling points in the pixel, and the area S of the portion divided by the edge in the pixel. An area calculation circuit (42) for determining color, one or a plurality of sampling points used for color synthesis from a plurality of sampling points in the pixel, or a color selection circuit (43) for selecting a color at the sampling points, and the area calculation circuit Is an anti-aliasing circuit (41) including a color composition circuit (44) for determining the color of the pixel using the area S calculated by the above and the color selected by the color selection circuit. In the figure, 46 indicates an edge memory (or edge Z memory), and 47 indicates a color memory. Each memory and circuit are connected by a bus.

  With such an anti-aliasing circuit, the area S of the portion of the pixel that is divided by the edge can be determined using edge information in the pixel and a plurality of sampling points in the pixel. Provided is an antialiasing method in computer graphics that selects one or a plurality of sampling points used for color synthesis from a sampling point or a color at the sampling point, and determines the color of the pixel using an area S and the selected color. it can.

  The edge information is usually information including information on the slope and intercept of the edge, and may include any of the slope of the edge, the intercept, the start and end points, and the polygon normal in the pixel. The edge information is usually stored in the edge memory (46), and the edge information is read out by control by a control device such as a CPU, and is input to the area calculation circuit (42) or the color selection circuit through the bus.

  The edge memory (46) may include an edge Z memory that stores not only edge information but also Z values. By using such an edge Z memory, even when a plurality of polygon portions exist on a certain pixel, it is possible to effectively determine the foremost polygon.

FIG. 7 is a diagram illustrating an example of polygon edges and sampling points in a certain pixel. FIG. 7 is merely an example, and sampling points other than those shown in FIG. 7 may be adopted. Reference numeral 60 denotes a center point C ₀ of a pixel that is a sampling point. Reference numerals 61 to 64 indicate the vertices C _{1 to} C ₄ in the pixels which are sampling points. Each vertex C ₁ -C ₄ is a vertex shared with adjacent pixels. Reference numeral 66 represents an edge. An edge occurs when a part of a polygon occupies a certain pixel. Reference numerals 67 and 68 indicate intersections between the edge and the side of the pixel. Reference numeral 69 denotes an area including the center point of the pixel, out of the two areas of the pixel separated by the edge. Reference numeral 70 denotes an area that does not include the center point of the pixel, out of the two areas of the pixel separated by the edge.

  FIG. 8 is a diagram showing another example of polygon edges and sampling points in a certain pixel. FIG. 9 is a diagram showing another example of polygon edges and sampling points in a certain pixel. FIG. 10 is a diagram illustrating another example of polygon edges and sampling points in a certain pixel.

  As shown in FIG. 9, there may be a plurality of edges included in a certain pixel. The number of edges included in a pixel can be easily obtained by using a circuit that calculates the number of intersections between the edge and the side of the pixel. That is, half of the number of intersections is the number of edges. Having such an edge number calculation circuit is a preferred embodiment of the present invention. For example, it is determined whether or not the number of edges included in a pixel is 2 or more, and if it is 1, the color of the pixel is determined using each circuit shown below, and if 0 or 2 or more, You may make it determine the color of a pixel by calculating | requiring the average of one or all the colors of each sampling point. Such a circuit for obtaining an average of colors can be easily designed by appropriately using an addition circuit and a division circuit, an addition circuit and a table, or the like. Further, as shown in FIG. 10, there may be two or more polygons existing in a certain pixel.

[Area calculation circuit]
The area calculation circuit (42) is a circuit for determining an area S of a portion of the pixel divided by the edge, using edge information of the pixel and a plurality of sampling points in the pixel.

  The area S required by the area calculation circuit is, for example, the area of a region including the center point of the pixel among the two regions of the pixel divided by the edge. In addition, when there are two or more edges included in a pixel, it may be the area occupied by the pixel in a part of a polygon, or may be the area occupied by the pixel in a part of a polygon. It may be the area of a region (in the front direction) having a smaller Z value than other polygons. Also, if a pixel contains two or more polygons, the area of each polygon part that occupies that pixel and has a smaller Z value than the other polygons (in the front direction) is calculated. Alternatively, the area of the polygon that has the largest area in a certain pixel, that is, the area that occupies that pixel and that has a smaller Z value than other polygons (in the front direction) may be obtained. Alternatively, the area of a region that occupies the pixel in the portion of the polygon including the center point of the polygon and that has a smaller Z value than the other polygons (in the front direction) may be obtained.

An example of the area calculation circuit is one that calculates an area S of a portion divided by the edge in the pixel by referring to an area table that stores the relationship between the edge and the area S. More specifically, there is an area table that stores the relationship between the area S and the two intersections between the edge and the pixel side. By using such an area table, the area S can be quickly obtained from two intersections. Even when there are two or more edges included in a pixel, an area table storing the relationship between each intersection and the area S may be prepared. However, as the number of intersections increases, the number of patterns that must be stored increases and a large amount of memory is required. Therefore, the area table is a table that stores the areas S for two intersections (one edge). What is used is preferred. As shown in FIG. 10, when a certain pixel has two edges in a certain pixel, the area S of a certain polygon occupying a certain pixel is easily obtained by referring to the area table twice and subtracting with a subtraction circuit or the like. be able to. Assuming that the _four intersections in FIG. 9 are P _{1 to} P ₄ , first, the intersections P ₃ and P ₄ are used, the area of the trapezoid P ₃ C ₁ C ₂ C ₄ P ₄ is obtained from the area table, and the value is stored in the memory. Remember. Then, using the intersection points P ₁ and P ₂ , the area of the trapezoid P ₁ C ₁ C ₃ C ₄ P ₂ is obtained, the value is stored in the memory, and the subtraction circuit and / or the addition circuit is used to obtain the P ₁ C ₁ P ₃ C ₄ may be calculated the area of the C ₄ P _2. S = trapezoid P ₁ C ₁ C ₃ C ₄ P ₂ − (1-trapezoid P ₁ C ₁ C ₃ C ₄ P ₂ ), the area S can be obtained with only the subtractor circuit, and the area of the two trapezoids Therefore, the area S can be obtained using a subtracting circuit and an adding circuit.

[Color selection circuit]
The color selection circuit is a circuit for selecting one or a plurality of sampling points used for color synthesis from a plurality of sampling points in a pixel, or selecting a color at the sampling points. For simplicity, the color selected in the region including the center point of the pixel out of the two colors selected by the color selection circuit is Ca, and the center point of the pixel out of the two colors selected by the color selection circuit Let Cb be the color selected in the region that does not contain.

Examples of the color selection circuit include the following. That is, the plurality of sampling points in the pixel are composed of the four vertexes of the pixel and the center point of the pixel, the center point of the pixel is selected as the sampling point, and the color at the center point is selected as Ca. On the other hand, the average of the colors at the sampling points included in the area not including the center point of the pixel is obtained and selected from the two areas separated by the edge. For example, in the area indicated by 60 in FIG. 10, there are two sampling points C ₁ and C ₃ included in the area not including the center point of the pixel, so C ₁ and C ₃ are selected as sampling points for obtaining the color. , Cb, the average of C ₁ and C ₃ may be obtained. To select a sampling point, it can be easily determined by using edge information (intersection information). For example, when there is one edge, it is possible to easily determine the sampling point by using which side the intersection is located and by using the position information of the intersection. Then, Cb can be easily obtained by using an addition circuit and a division circuit, an addition circuit and a 1/2 table, or an addition circuit and a 1/3 table.

Another example of the color selection circuit is as follows. That is, the plurality of sampling points in the pixel are composed of the four vertexes of the pixel and the center point of the pixel, and the color at the center point of the pixel is selected as Ca. On the other hand, a color at an arbitrary sampling point included in an area not including the center point of the pixel is selected from two areas of the pixel separated by the edge. For example, in the case shown in FIG. 7, the C ₁ and C _3, are selected as a sampling point, any color is selected as Cb.

Another example of the color selection circuit is as follows. That is, a plurality of sampling points in a pixel are composed of four vertices of the pixel and the center point of the pixel, and at any sampling point included in the region including the center point of the pixel among the two regions of the pixel separated by the edge. A color and a color at an arbitrary sampling point included in an area that does not include the center point of the pixel among the two areas of the pixel separated by the edge are selected. In the case shown in FIG 7, C ₀ and C ₂ and C ₄ is selected as a sampling point, any color is chosen as Ca. C ₁ and C ₃ is selected as a sampling point, any color is selected as Cb.

  Another example of the color selection circuit is as follows. That is, the plurality of sampling points in the pixel are composed of the four vertexes of the pixel and the center point of the pixel, and the color at the sampling point included in the region including the center point of the pixel among the two regions of the pixel separated by the edge. And an average of colors obtained at sampling points included in an area not including the center point of the pixel out of two areas divided by edges.

  Another example of the color selection circuit is as follows. That is, two samplings used for color synthesis from a plurality of sampling points in a pixel by selecting an arbitrary point occupied by the polygon in the pixel and an arbitrary point not occupied by the polygon among the sampling points from the edge information. The color at the sampling point is selected by selecting a point or by selecting the color at the former point and the latter point.

[Color composition circuit]
The color composition circuit is a circuit for determining the color of the pixel using the area S calculated by the area calculation circuit and the color selected by the color selection circuit. As an example of a color synthesis circuit, the area of a pixel is 1, and the area S calculated by the area calculation circuit is the area of a region including the center point of the pixel among two regions of the pixel divided by the edge, Of the two colors selected by the color selection circuit, the color selected in the area including the center point of the pixel is Ca, and the area of the two colors selected by the color selection circuit does not include the center point of the pixel In this case, the color of the pixel is determined by obtaining Ca × S + Cb (1−S) where Cb is the color selected in step (b).

  As a more specific color composition circuit, the area of a pixel is 1 and the area S calculated by the area calculation circuit is the area of a region including the center point of the pixel among the two regions of the pixel delimited by the edge The color selected in the region including the center point of the pixel among the two colors selected by the color selection circuit is Ca, and the center point of the pixel is included among the two colors selected by the color selection circuit. When the color selected in the non-region is Cb, the multiplication circuit multiplies S and Ca by using a multiplication circuit, an addition circuit, and a division circuit (or [1-S table]), and S × Ca is obtained. The division circuit or [1-S table] obtains the value of (1-S), the multiplication circuit obtains (1-S) × Cb, and the addition circuit calculates S × Ca and (1-S) × Cb. To obtain S × Ca + (1−S) × Cb. That determine the color of the color.

Further, as a specific color synthesis circuit different from the above, a circuit for obtaining S x (Ca−Cb) + Cb can be mentioned. This is S x Ca + (1-S) x Cb = S x (Ca-Cb) +
It is based on being Cb. Such direct determination of S x (Ca−Cb) + Cb is preferable because the number of multipliers is reduced (from two to one). In addition, a 1-S table or the like is not necessary, which is preferable. Specifically, the area of a pixel is 1, and the area S calculated by the area calculation circuit is an area of a region including a center point of the pixel, out of two regions of the pixel divided by the edge, and the color Of the two colors selected by the selection circuit, the color selected in the area including the center point of the pixel is Ca, and the color selected in the area not including the center point of the pixel is selected from the two colors selected by the color selection circuit. When the color obtained is Cb, S x (Ca−Cb) + Cb may be obtained using a multiplier circuit, an adder circuit, and the like. For example, when the values of S, Ca, and Cb are input to the color synthesis circuit via a bus, an adder (subtracter) calculates the value of Ca-Cb, and the multiplier
The value of x (Ca-Cb) is obtained, and the adder may obtain S x (Ca-Cb) + Cb.

[Example of operation]
Hereinafter, an operation example of the anti-aliasing circuit will be described. The edge information of a polygon or edge information and the Z value are read from the edge memory 46. The read information is input to the area calculation circuit (42) and the color selection circuit (43) through the bus. The area calculation circuit (42) determines an area S of a portion of the pixel that is divided by the edge using edge information of the pixel and a plurality of sampling points in the pixel.

  As a method for calculating the area S by the area calculation circuit, the area S of the portion divided by the edge in the pixel is calculated by referring to an area table storing the relationship between the intersection point included in the edge information and the area S. What to do. In this way, the area S is obtained. The obtained area S is input to the color synthesis circuit (44) through the bus.

  On the other hand, a color selection circuit selects one or a plurality of sampling points used for color synthesis from a plurality of sampling points in a certain pixel, or selects a color at the sampling points. As an example of selecting a color, a center point of a certain pixel is selected as a sampling point, and a color at the center point is selected as Ca. The color information of each sampling point is stored in the color memory (47), and the color information at each sampling point can be obtained by reading the stored color information. On the other hand, the average of the colors at the sampling points included in the area not including the center point of the pixel is obtained and selected from the two areas separated by the edge. In this way, the colors Ca and Cb used for color synthesis are determined. The determined colors Ca and Cb are input to the color synthesis circuit (44) through the bus.

  The color composition circuit determines the color of the pixel using the area S calculated by the area calculation circuit and the color selected by the color selection circuit. Specifically, the area of a pixel is 1, and the area S calculated by the area calculation circuit is an area of a region including a center point of the pixel, out of two regions of the pixel divided by the edge, and the color Of the two colors selected by the selection circuit, the color selected in the area including the center point of the pixel is Ca, and the color selected in the area not including the center point of the pixel is selected from the two colors selected by the color selection circuit. The color of the pixel is determined by obtaining Ca × S + Cb (1−S) (or S x (Ca−Cb) + Cb) or the like, where Cb is the calculated color.

  [Another Example of Antialiasing Circuit] FIG. 11 is a block diagram of an antialiasing circuit different from the above. As shown in FIG. 11, the antialiasing circuit (41) according to this aspect includes an area type determination circuit (45) for determining an area type in which a pixel is divided from edge information, and the edge information or the edge. An area calculation circuit (42) for determining an area S of a portion of the pixel divided by the edge using information and area type information, and one or more used for color synthesis from a plurality of sampling points in the pixel A color selection circuit (43) for selecting a sampling point or a color at the sampling point, the area S calculated by the area calculation circuit, and the color selected by the color selection circuit are used to determine the color of the pixel. The present invention relates to an antialiasing circuit (41) including a color synthesis circuit (44). In the figure, 46 indicates an edge memory (or edge Z memory), and 47 indicates a color memory. Each memory and circuit are connected by a bus.

  In such an anti-aliasing circuit, an area type in which a pixel is divided is determined from edge information, and the edge of the pixel is divided by the edge using the edge information or the edge information and area type information. Since the area S of the portion can be determined, one or a plurality of sampling points used for color synthesis or a color at the sampling point is selected from a plurality of sampling points in the pixel, and the area S and the selected color are used. , An anti-aliasing method in computer graphics for determining the color of the pixel can be provided.

  The edge information is usually information including information on the slope and intercept of the edge, and may include any of the slope of the edge, the intercept, the start and end points, and the polygon normal in the pixel. The edge information is normally stored in an edge memory (46), read out by control by a control device such as a CPU, and is input to the area calculation circuit (42) or the color selection circuit (43) through the bus.

  The edge memory (46) includes an edge Z memory that stores not only edge information but also Z values. By using such an edge Z memory, even when a plurality of polygon portions exist on a certain pixel, it is possible to effectively determine the foremost polygon.

  Having an edge number calculation circuit is a preferred embodiment of the present invention. For example, it is determined whether or not the number of edges included in a pixel is 2 or more, and if it is 1, the color of the pixel is determined using each circuit shown below, and if 0 or 2 or more, You may make it determine the color of a pixel by calculating | requiring the average of one or all the colors of each sampling point. Such a circuit for obtaining an average of colors can be easily designed by appropriately using an addition circuit and a division circuit, an addition circuit and a table, or the like.

[Area type determination circuit]
The area type determination circuit (45) is a circuit for determining an area type in which pixels are divided from edge information. As a specific area type determination circuit (45), refer to an area type memory (area type table) that stores the relationship between the intersection information and the area type using the intersection information between the edge and the pixel side. To determine the area type.

  Area types include hexagons (example 9), pentagons (example 8), squares and triangles. Another area type includes a hexagon, a pentagon, a quadrangle, and a triangle. The quadrangle includes a quadrangle in which four intersections of the pixel and the polygon exist on opposite sides of the pixel, the pixel, and the triangle. Four intersections of polygons include a quadrangle that exists on adjacent sides of the pixel, and the triangle includes a triangle in which three intersections of the pixel and the polygon exist on opposite sides of the pixel; And the three intersections of the polygons include a triangle existing on an adjacent side of the pixel. Thus, since it classify | categorizes for every area type, an area can be calculated | required easily.

  The area type determination circuit (45) may determine the area type by referring to an area type association table in which the information indicating which side the intersection is on and the area type are stored in association with each other.

[Area calculation circuit]
The area calculation circuit (42) is a circuit for determining an area S of a portion of the pixel divided by the edge, using edge information of the pixel and a plurality of sampling points in the pixel.

  The area S required by the area calculation circuit is, for example, the area of a region including the center point of the pixel among the two regions of the pixel divided by the edge. In addition, when there are two or more edges included in a pixel, it may be the area occupied by the pixel in a part of a polygon, or may be the area occupied by the pixel in a part of a polygon. It may be the area of a region (in the front direction) having a smaller Z value than other polygons. Also, if a pixel contains two or more polygons, the area of each polygon part that occupies that pixel and has a smaller Z value than the other polygons (in the front direction) is calculated. Alternatively, the area of the polygon that has the largest area in a certain pixel, that is, the area that occupies that pixel and that has a smaller Z value than other polygons (in the front direction) may be obtained. Alternatively, the area of a region that occupies the pixel in the portion of the polygon including the center point of the polygon and that has a smaller Z value than the other polygons (in the front direction) may be obtained.

An example of the area calculation circuit is one that calculates an area S of a portion divided by the edge in the pixel by referring to an area table that stores the relationship between the edge and the area S. More specifically, there is an area table that stores the relationship between the area S and the two intersections between the edge and the pixel side. By using such an area table, the area S can be quickly obtained from two intersections. Even when there are two or more edges included in a pixel, an area table storing the relationship between each intersection and the area S may be prepared. However, as the number of intersections increases, the number of patterns that must be stored increases and a large amount of memory is required. Therefore, the area table is a table that stores the areas S for two intersections (one edge). What is used is preferred. As shown in FIG. 9, when a certain pixel has two edges in a certain pixel, the area S of a certain polygon occupying a certain pixel can be easily obtained by referring to the area table twice and subtracting with a subtraction circuit or the like. be able to. Assuming that the _four intersections in FIG. 9 are P _{1 to} P ₄ , first, the intersections P ₃ and P ₄ are used, the area of the trapezoid P ₃ C ₁ C ₂ C ₄ P ₄ is obtained from the area table, and the value is stored in the memory. Remember. Then, using the intersection points P ₁ and P ₂ , the area of the trapezoid P ₁ C ₁ C ₃ C ₄ P ₂ is obtained, the value is stored in the memory, and the subtraction circuit and / or the addition circuit is used to obtain the P ₁ C ₁ P ₃ C ₄ may be calculated the area of the C ₄ P _2. S = trapezoid P ₁ C ₁ C ₃ C ₄ P ₂ − (1-trapezoid P ₁ C ₁ C ₃ C ₄ P ₂ ), the area S can be obtained with only the subtractor circuit, and the area of the two trapezoids Therefore, the area S can be obtained using a subtracting circuit and an adding circuit.

  As another example of the area calculation circuit, an area calculation method is determined according to the area type determined by the area type determination circuit, and an area table storing the relationship between the edge and the area S is referred to, thereby Among them, there is one that calculates the area S of the portion divided by the edge.

  More specifically, the area calculation circuit uses the area type determined by the area type determination circuit and the edge information, selects a different area calculation circuit for each area type, and includes vertexes included in the edge information. Examples include determining the area S of the portion divided by the edge of the pixel by inputting value information and intersection information of the pixel and the polygon to the selected area calculation circuit.

  As another example, the area calculation circuit uses the area type determined by the area type determination circuit and the edge information, selects a different area table for each area type, and intersects the pixel and the polygon. Examples include determining the area S of a portion of the pixel divided by the edge by inputting information into the selected area table.

[Color selection circuit]
The color selection circuit is a circuit for selecting one or a plurality of sampling points used for color synthesis from a plurality of sampling points in a pixel, or selecting a color at the sampling points. For simplicity, the color selected in the region including the center point of the pixel out of the two colors selected by the color selection circuit is Ca, and the center point of the pixel out of the two colors selected by the color selection circuit Let Cb be the color selected in the region that does not contain.

Examples of the color selection circuit include the following. That is, the plurality of sampling points in the pixel are composed of the four vertexes of the pixel and the center point of the pixel, the center point of the pixel is selected as the sampling point, and the color at the center point is selected as Ca. On the other hand, the average of the colors at the sampling points included in the area not including the center point of the pixel is obtained and selected from the two areas separated by the edge. For example, in the area indicated by 60 in FIG. 10, there are two sampling points C ₁ and C ₃ included in the area not including the center point of the pixel, so C ₁ and C ₃ are selected as sampling points for obtaining the color. , Cb, the average of C ₁ and C ₃ may be obtained. To select a sampling point, it can be easily determined by using edge information (intersection information). For example, when there is one edge, it is possible to easily determine the sampling point by using which side the intersection is located and by using the position information of the intersection. Then, Cb can be easily obtained by using an addition circuit and a division circuit, an addition circuit and a 1/2 table, or an addition circuit and a 1/3 table.

Another example of the color selection circuit is as follows. That is, the plurality of sampling points in the pixel are composed of the four vertexes of the pixel and the center point of the pixel, and the color at the center point of the pixel is selected as Ca. On the other hand, a color at an arbitrary sampling point included in an area not including the center point of the pixel is selected from two areas of the pixel separated by the edge. For example, in the case shown in FIG. 7, the C ₁ and C _3, are selected as a sampling point, any color is selected as Cb.

Another example of the color selection circuit is as follows. That is, a plurality of sampling points in a pixel are composed of four vertices of the pixel and the center point of the pixel, and at any sampling point included in the region including the center point of the pixel among the two regions of the pixel separated by the edge. A color and a color at an arbitrary sampling point included in an area that does not include the center point of the pixel among the two areas of the pixel separated by the edge are selected. In the case shown in FIG 7, C ₀ and C ₂ and C ₄ is selected as a sampling point, any color is chosen as Ca. C ₁ and C ₃ is selected as a sampling point, any color is selected as Cb.

  Another example of the color selection circuit is as follows. That is, the plurality of sampling points in the pixel are composed of the four vertexes of the pixel and the center point of the pixel, and the color at the sampling point included in the region including the center point of the pixel among the two regions of the pixel separated by the edge. And an average of colors obtained at sampling points included in an area not including the center point of the pixel out of two areas divided by edges.

  Another example of the color selection circuit is as follows. That is, two samplings used for color synthesis from a plurality of sampling points in a pixel by selecting an arbitrary point occupied by the polygon in the pixel and an arbitrary point not occupied by the polygon among the sampling points from the edge information. The color at the sampling point is selected by selecting a point or by selecting the color at the former point and the latter point.

[Color composition circuit]
The color composition circuit is a circuit for determining the color of the pixel using the area S calculated by the area calculation circuit and the color selected by the color selection circuit. As an example of a color synthesis circuit, the area of a pixel is 1, and the area S calculated by the area calculation circuit is the area of a region including the center point of the pixel among two regions of the pixel divided by the edge, Of the two colors selected by the color selection circuit, the color selected in the area including the center point of the pixel is Ca, and the area of the two colors selected by the color selection circuit does not include the center point of the pixel In this case, the color of the pixel is determined by obtaining Ca × S + Cb (1−S) where Cb is the color selected in step (b).

  As a more specific color composition circuit, the area of a pixel is 1 and the area S calculated by the area calculation circuit is the area of a region including the center point of the pixel among the two regions of the pixel delimited by the edge The color selected in the region including the center point of the pixel among the two colors selected by the color selection circuit is Ca, and the center point of the pixel is included among the two colors selected by the color selection circuit. When the color selected in the non-region is Cb, the multiplication circuit multiplies S and Ca by using a multiplication circuit, an addition circuit, and a division circuit (or [1-S table]), and S × Ca is obtained. The division circuit or [1-S table] obtains the value of (1-S), the multiplication circuit obtains (1-S) × Cb, and the addition circuit calculates S × Ca and (1-S) × Cb. To obtain S × Ca + (1−S) × Cb. That determine the color of the color.

[Example of operation]
Hereinafter, an operation example of the above-described antialiasing circuit will be described. The edge information of a polygon or edge information and the Z value are read from the edge memory 46. The read information is input to the area type determination circuit (45), the area calculation circuit (42), and the color selection circuit (43) through the bus.

  The area type determination circuit (45) determines the area type from the edge information. For example, the area type is determined by referring to an area type memory (area type table) that stores the relationship between the intersection point information and the area type using the intersection point information between the edge and the pixel side. The obtained area type information is input to the area calculation circuit through the bus. Further, the obtained area type information may be input to the color selection circuit through the bus.

  The area calculation circuit (42) uses the edge information in the pixel and a plurality of sampling points in the pixel and / or uses the area type information to determine the area S of the portion divided by the edge in the pixel. decide.

  As a method for calculating the area S by the area calculation circuit, the area S of the portion divided by the edge in the pixel is calculated by referring to an area table storing the relationship between the intersection point included in the edge information and the area S. What to do. This area table may be provided for each area type, an area table corresponding to the area type may be selected, and the area S may be obtained by referring to the intersection information in the selected table. In this way, the area S is obtained. The obtained area S is input to the color synthesis circuit (44) through the bus.

  On the other hand, a color selection circuit selects one or a plurality of sampling points used for color synthesis from a plurality of sampling points in a certain pixel, or selects a color at the sampling points. The color information of each sampling point is stored in the color memory (47), and the color information at each sampling point can be obtained by reading the stored color information. As an example of selecting a color, a center point of a certain pixel is selected as a sampling point, and a color at the center point is selected as Ca. On the other hand, the average of the colors at the sampling points included in the area not including the center point of the pixel is obtained and selected from the two areas separated by the edge. In this way, the colors Ca and Cb used for color synthesis are determined. The determined color colors Ca and Cb are input to the color synthesis circuit (44) through the bus.

  The color composition circuit determines the color of the pixel using the area S calculated by the area calculation circuit and the color selected by the color selection circuit. Specifically, the area of a pixel is 1, and the area S calculated by the area calculation circuit is an area of a region including a center point of the pixel, out of two regions of the pixel divided by the edge, and the color Of the two colors selected by the selection circuit, the color selected in the area including the center point of the pixel is Ca, and the color selected in the area not including the center point of the pixel is selected from the two colors selected by the color selection circuit. When the obtained color is Cb, the color of the pixel is determined by obtaining Ca × S + Cb (1−S).

[program]
Although the circuit (hardware) has been described so far, it goes without saying that a program for performing anti-aliasing can be provided using the concept of the anti-aliasing circuit.

  That is, according to the present invention, the computer uses an edge information in a pixel and a plurality of sampling points in the pixel to determine an area S of a portion of the pixel that is divided by the edge; One or more sampling points used for color synthesis from a plurality of sampling points in the pixel or a color selection means for selecting a color at the sampling point, an area S calculated by the area calculation means, and the color selection means selected It is also possible to provide an anti-aliasing program that functions to include a color composition unit that determines the color of the pixel using the color.

  In another aspect, the computer uses an area type determination means for determining an area type in which a pixel is divided from edge information, and the edge information or the edge information and the area type information. An area calculating means for determining an area S of a portion divided by the edge, and one or a plurality of sampling points used for color synthesis from a plurality of sampling points in the pixel, or a color selection means for selecting a color at the sampling points An anti-aliasing program that functions as comprising an area S calculated by the area calculating means and a color synthesizing means for determining the color of the pixel using the color selected by the color selecting means.

  A computer in which these programs are used includes, for example, a main memory storing a program that causes the computer to function as each of the above means, an input device for inputting information, and an output device for outputting information outside the device. And a storage device such as a database for temporarily or semi-permanently storing information and a central processing unit (CPU) for performing various arithmetic processes. A CPU or the like may be instructed to receive an instruction of a control program (anti-alias program) in the main memory and perform an operation for realizing these means.

[Fill process flow]
FIG. 12 is a flowchart for explaining an example of the painting process in the present invention. In the figure, S indicates a step (process). Hereinafter, the filling process will be described in detail with reference to FIG.

  For image composition and vector images, the maximum layer image width of these compositing target images is set to the variable TotalX (S101). A variable State indicating the status is initialized (S102). PreEdgeInfo (pre-edge information), which is a memory for storing edge information of the previously drawn vector image, is initialized (S103). Two or all of the steps S101 to S103 are preferably performed simultaneously or in parallel. This completes the preprocessing.

  Thereafter, the block loop step (S104) starts. An image having the minimum width is obtained from each layer (step S105). Processing is performed in units of blocks defined by CurrentWidth (current width (minimum width in the current situation)), which is the minimum width variable obtained in step S105. At the same time, CurrentWidth is subtracted from variable TotalX, and unprocessed Keep the horizontal width of and update the block width. By S106, within the block loop step of S104, after updating the block width, the y-direction loop step (S107) advances the process in the vertical direction, and after the layer loop step (S108), the drawing target layer determination step (S124) The layer image and the vector image are determined in step. On the other hand, horizontal processing is performed after the x direction loop step (S125) and the vector image x direction loop step (S109) of each layer image.

  Regarding processing for vector images, the presence or absence of edges generated in the edge information generation unit (4) in the vector image edge information determination step after the vector image x-direction loop step (S109), the y-direction code of the target edge The presence / absence of an edge is determined using an edge information variable EdgeInfo consisting of 2 bits for holding (S110). If the target pixel has edge information, the value stored in PreEdgeInfo, which is an edge information information memory previously found, is compared with the current edge information (difference determination step with previous edge: S111). In S111, it is determined whether or not it is different from the previous edge information. If the result is different, the previous edge information variable information stored in PreEdgeInfo is updated at the edge information update step (S112) and at the same time, the status variable Enables / disables the filled area by performing State inversion.

  After that, if the status variable State is 1, it is defined as a filled area, and if it is 0, it is defined as a non-filled area. In the status determination step (S113), branching is performed. The background image data is read from the current line memory (S115). Then, the image data is read out, and the vector image and the background image at the time of painting the vector image are blended (S116). In S116, blending calculation is performed using, for example, a 4-bit variable EdgeAlpha indicating the transparency of the target pixel, and the vector image result at the time of filling the vector image is stored in the line memory (S117). In S117, the resultant pixel data is stored in the line memory.

  In the status determination step (S113), branching is performed. If the region is not to be filled, the edge transparency when the vector image is not filled is determined (S119). If the 4-bit variable EdgeAlpha indicating the transparency of the target pixel is not 0xf in S119, that is, if it is semi-transparent, the background image data is read from the line memory when the vector image is not filled (S120). Then, the image data is read and the vector image and the background image are blended when the vector image is not filled (S121). In S121, a 4-bit variable EdgeAlpha indicating the transparency of the target pixel is used to perform a blending operation, and the vector image result when the vector image is not filled is stored in the line memory (S122). In S122, the combined result pixel data to the line memory is stored. On the other hand, if the 4-bit variable EdgeAlpha indicating the transparency of the target pixel is 0xf, that is, if it is non-transparent, the blending operation is not performed, and the line memory of the vector image result when the vector image is not filled (S122). In S122, the combined result pixel data to the line memory is stored.

  Also, it is determined whether the target image to be synthesized is a layer image (S124). In the case of a layer image, horizontal processing is performed by processing after the layer image x-direction loop step (S125).

  In the horizontal processing after the layer image x-direction loop step (S125), a 4-bit variable indicating the transparency of the edge image at the target pixel position in the edge transparency determination step (S126) when rendering the layer image. Judge EdgeAlpha. If the 4-bit variable EdgeAlpha indicating the transparency of the edge image at the target pixel position is not 0xf, that is, if it is semi-transparent, the background image data is read from the layer image line memory (S127). Image data is read, and blending is performed using a 4-bit variable EdgeAlpha indicating the transparency of the target pixel in the blending step (S128) of the layer image and background image of the layer image. Thereafter, the layer image result of the layer image is stored in the line memory (S129).

  When the 4-bit variable EdgeAlpha indicating the transparency of the target pixel is 0xf, that is, when it is non-transparent, the blending operation is not performed, and the layer image result when the layer image blending is not performed is transferred to the line memory. In the storing step (S130), the combined result pixel data is stored in the line memory.

  After processing the vector image and the layer image in the horizontal direction (S131, S123), the status variable State and PreEdgeInfo which is the previous edge information memory are initialized, and the image overlay processing for each layer (S134). ) And horizontal processing (S135). After that, in the TotalX end determination step (S136), the end determination is made regarding the block loop, and when the processing is completed for all screens, the paint processing ends after the block loop end step (S137) (S138).

[program]
The image generation apparatus of the present invention is basically implemented by hardware or cooperation between hardware and software. As such software, a computer can be used as an edge information storage memory for storing polygon edge information at a pixel, and as a vector data storage memory for storing polygonal shape data in vector format. , Means for performing rasterization processing based on polygon shape data stored in the vector data storage memory, and writing out edge information of the polygon as a rasterization result to the edge information storage memory, and at least Means as a layer image storage memory for storing image information relating to the background and image information for each of a plurality of layers, and using the edge information stored in the edge information storage memory to fill the inside of an image defined in vector format In addition, the layer image storage memo The image information for each pixel is synthesized by reading the image information related to the background and the image information for each layer stored in the image, superimposing the vector format image and the image information for each layer, and performing the image processing operation for each pixel. A program that functions as a unit as a synthesis unit and a unit as a result image storage memory for storing the image synthesized by the image synthesis unit can be given. Since each of these functions functions in the same manner as described above, the above description will be applied here.

[recoding media]
The present invention can also provide a computer-readable recording medium storing the above program. Examples of such a recording medium include a CD-ROM, a DVD, a hard disk, or a memory in a computer. When predetermined information is input to the input unit of the computer, the program is read in response to a command from the control unit, and the arithmetic unit that receives the command from the control unit is input using the read program. Data, data stored in the storage unit, and the like are read out, and for example, the memory of the storage unit is used as a work area to perform predetermined calculations. The calculation result is temporarily stored in, for example, a memory and then output from the output unit. These data may be transmitted through a bus, for example. In this way, processing in which hardware resources and programs cooperate is performed.

[Computer configuration]
FIG. 13 is a block diagram showing an embodiment (computer) of the present invention. This embodiment relates to a computer based on computer graphics (such as a graphic computer). As shown in FIG. 13, the computer 101 includes a central processing unit (CPU) 102, a geometry calculation unit such as a geometry calculation circuit 103, a rendering unit such as a renderer 104, a texture generation unit such as a texture generation circuit 105, and an illumination processing circuit. An illumination processing unit such as 107, a display information creation unit such as a display circuit 108, a frame buffer 109, and a monitor 110 are provided. These elements are connected by a bus or the like and can transmit data to each other. In addition, a storage unit including a main memory (not shown), various tables, a work memory 111 serving as a work area, a texture memory 112 storing textures, and the like may be included. The hardware constituting each unit is connected via a bus, for example. The storage unit may be configured by a RAM such as a VRAM, a CR-ROM, a DVD, a hard disk, or the like.

  A central processing unit (CPU) 102 is a device for controlling a program or the like for generating an image. The work memory 111 may store data used by the CPU 102, a display list, and the like. Then, the CPU 102 may read a program or the like stored in the main memory and perform a predetermined process. However, the predetermined processing may be performed only by hardware processing. For example, the CPU 102 reads polygon data as world coordinate three-dimensional object data from the work memory 111 and outputs the polygon data to the geometry calculation circuit 103. Specifically, a processor having a main processor, a coprocessor, a data processor, four arithmetic operation circuits, a general-purpose operation circuit, or the like as appropriate. These are connected by a bus or the like so that signals can be exchanged. In addition, a data expansion processor for expanding compressed information may be provided.

  The geometry calculation circuit 103 is a circuit for performing coordinate conversion or the like on the input polygon data to data in a viewpoint coordinate system with the viewpoint as the origin. The geometry calculation circuit 103 outputs the processed polygon data to the renderer 104. Specific geometry operation circuits include a geometry processor, coprocessor, data processor, four arithmetic operation circuit, or general-purpose operation circuit connected to the main processor through a bus.

  The renderer 104 is a circuit or device for converting polygon unit data into pixel unit data. The renderer 104 outputs data in units of pixels to the texture generation circuit 105. Specific examples of the renderer 104 include a data processor, four arithmetic operation circuits, or a general-purpose arithmetic circuit connected to the main processor through a bus.

  The texture generation circuit 105 is a circuit for generating a texture color in units of pixels based on the texture data stored in the texture memory 112. The texture generation circuit 105 outputs pixel unit data having texture color information to the illumination processing circuit 107. Specific examples of the texture generation circuit 105 include a data processor connected to the main processor through a bus, a four arithmetic operation circuit, or a general-purpose operation circuit.

  The illumination processing circuit 107 is a circuit for performing shading on a polygon having texture color information using a normal vector, a barycentric coordinate, and the like in pixel units. The illumination processing circuit 107 outputs the shaded image data to the display circuit 108. Specific examples of the illumination processing circuit 107 include a data processor connected to the main processor through a bus, a four arithmetic operation circuit, or a general-purpose operation circuit. Then, information relating to light may be appropriately read out from a table stored in the memory and the like to perform shading.

  The display circuit 108 is a circuit for writing the image data input from the illumination processing circuit 107 to the frame buffer 109, reading the image data written in the frame buffer 109, and controlling it to obtain display image information. The display circuit 108 outputs the display image information to the monitor 110. Specific examples of the display circuit include a drawing processor, a data processor, four arithmetic operation circuits, and a general-purpose operation circuit connected to the main processor through a bus.

  The monitor 110 is a device for displaying a computer graphics image in accordance with input display image information.

  Since the computer of the present invention includes the image generation apparatus of the present invention as a renderer, a texture generation circuit, and a display device, the scale of hardware can be reduced by sharing the circuit elements in these. In addition, by applying the geometry part to 2D vector images, it is possible to perform geometry conversion on 2D vector images, and shape transformation and scaling by matrix operations can be performed on vector images without adding dedicated hardware or software operations. Can be done. In addition, 2D and 3D display commands that have been treated as separate objects can be handled in a unified manner, and the composition of these 2D / 3D images can be performed at the same time. The situation which becomes complicated can be prevented effectively.

[Computer operation]
Hereinafter, an operation example of generating an image using a computer will be described. The CPU 102 reads polygon data from the work memory 111 and outputs the polygon data to the geometry calculation circuit 103. The geometry calculation circuit 103 performs processing such as coordinate conversion of the input polygon data into data of a viewpoint coordinate system with the viewpoint as the origin. The geometry calculation circuit 103 outputs the processed polygon data to the renderer 104. The renderer 104 converts polygon unit data into pixel unit data. The renderer 104 and the texture generation circuit 105 generate a texture color in units of pixels based on the texture data stored in the texture memory 112. The texture generation circuit 105 outputs pixel unit data having texture color information to the illumination processing circuit 107. The illumination processing circuit 107 shades a polygon having texture color information using a normal vector, barycentric coordinates, etc. in pixel units. The illumination processing circuit 107 outputs the shaded image data to the display circuit 108. The display circuit 108 writes the image data input from the illumination processing circuit 107 into the frame buffer 109, reads out the image data written into the frame buffer 109, and obtains display image information. At the same time, 2D / 3D synthesis processing can be performed by using information such as an edge buffer. The display circuit 108 outputs the display image information to the monitor 110. The monitor 110 displays a computer graphics image according to the input display image information.

  Since the computer of the present invention includes the image generation apparatus of the present invention as a renderer, a texture generation circuit, and a display device, the scale of hardware can be reduced by sharing the circuit elements in these. In addition, by applying the geometry part to 2D vector images, it is possible to perform geometry conversion on 2D vector images, and shape transformation and scaling by matrix operations can be performed on vector images without adding dedicated hardware or software operations. Can be done. In addition, 2D / vector and 3D display commands that have been handled as separate objects can be handled in a unified manner, and the 2D / 3D and vector images can be combined simultaneously. Therefore, it is possible to effectively prevent the system from becoming complicated.

[Game console configuration]
FIG. 14 is a block diagram of an embodiment (game machine) according to the present invention. The embodiment represented by this block diagram can be suitably used particularly as a portable, home or business game machine. Therefore, in the following, it will be described as a game machine. Note that the game machine shown in the figure may include at least the processing unit 200 (or may include the processing unit 200 and the storage unit 270, or the processing unit 200, the storage unit 270, and the information storage medium 280). These blocks (for example, the operation unit 260, the display unit 290, the sound output unit 292, the portable information storage device 294, and the communication unit 296) can be arbitrary constituent elements.

The processing unit 200 performs various processes such as control of the entire system, instruction instruction to each block in the system, game processing, image processing, and sound processing. The function of the processing unit 200 can be realized by hardware such as various processors (CPU, DSP, etc.) or ASIC (gate array, etc.) and a given program (game program).

  The operation unit 260 is for the player to input operation data. The function of the operation unit 260 can be realized by, for example, a controller including a lever, a button, an outer frame, and hardware. In particular, in the case of a portable game machine, the operation unit 260 may be formed integrally with the game machine body. Processing information from the controller is transmitted to the main processor via a serial interface (I / F) or bus.

The storage unit 270 is a work area such as the processing unit 200 or the communication unit 296. In addition, programs and various tables may be stored. The storage unit 270 may include, for example, a main memory 272, a frame buffer 274, and a texture storage unit 276, and may also store various tables. The function of the storage unit 270 can be realized by hardware such as ROM and RAM.
Examples of the RAM include VRAM, DRAM, and SRAM, and may be appropriately selected depending on the application. A VRAM or the like constituting the frame buffer 274 is used as a work area for various processors.

An information storage medium (storage medium usable by a computer) 280 stores information such as programs and data. The information storage medium 280 can be sold as a so-called game cassette. The function of the information storage medium 280 can be realized by hardware such as an optical disk (CD, DVD), a magneto-optical disk (MO), a magnetic disk, a hard disk, a magnetic tape, or a memory (ROM). The processing unit 200 performs various processes based on information stored in the information storage medium 280. The information storage medium 280 stores information (program or program and data) for executing the means of the present invention (this embodiment) (particularly, the blocks included in the processing unit 200). Note that the information storage medium 280 is not necessarily required when information such as programs and data is stored in the storage unit. Part or all of the information stored in the information storage medium 280 is transferred to the storage unit 270 when the system is powered on, for example. Further, as information stored in the information storage medium 280, program code for performing a predetermined process, image data, sound data, display object shape data, table data, list data, and instructions for instructing the processing of the present invention. Information including at least two of information, information for processing according to the instruction, and the like.

The display unit 290 outputs an image generated according to the present embodiment, and functions thereof are CRT (CRT), LCD (Liquid Crystal), OEL (Organic Electroluminescent Device), PDP (Plasma Display Panel), or HMD. It can be realized by hardware such as (head mounted display).

  The sound output unit 292 outputs sound. The function of the sound output unit 292 can be realized by hardware such as a speaker. The sound output is processed by a sound processor connected to the main processor or the like via a bus, for example, and output from a sound output unit such as a speaker.

  The portable information storage device 294 stores player personal data, save data, and the like. Examples of the portable information storage device 294 include a memory card and a portable game device. The functions of the portable information storage device 294 can be achieved by known storage means such as a memory card, flash memory, hard disk, and USB memory.

The communication unit 296 is an arbitrary unit that performs various controls for communicating with the outside (for example, a host device or other image generation system). The function of the communication unit 296 can be realized by various processors, hardware such as a communication ASIC, a program, or the like.

  The program or data for executing the game machine may be distributed from the information storage medium included in the host device (server) to the information storage medium 280 via the network and the communication unit 296.

  Examples of the processing unit 200 include a game processing unit 220, an image processing unit 230, and a sound processing unit 250. Specific examples include a main processor, a coprocessor, a geometry processor, a drawing processor, a data processor, four arithmetic operation circuits, or a general-purpose operation circuit. These are appropriately connected by a bus or the like so that signals can be exchanged. In addition, a data expansion processor for expanding compressed information may be provided.

  Here, the game processing unit 220 accepts coins (price), sets various modes, progresses the game, sets a selection screen, and positions and rotation angles of objects (rotation angles around the X, Y, or Z axes). , Processing to move the object (motion processing), processing to determine the position of the viewpoint (virtual camera position) and line-of-sight angle (virtual camera rotation angle), processing to place objects such as map objects in the object space, Operation data from the operation unit 260 includes various game processes such as a hit check process, a process for calculating game results (results, results), a process for a plurality of players to play in a common game space, or a game over process. Or based on personal data, stored data, game programs, etc. from the portable information storage device 294.

  The image processing unit 230 performs various types of image processing in accordance with instructions from the game processing unit 220 and the like. The sound processing unit 250 performs various types of sound processing in accordance with instructions from the game processing unit 220.

All of the functions of the game processing unit 220, the image processing unit 230, and the sound processing unit 250 may be realized by hardware, or all of them may be realized by a program. Alternatively, it may be realized by both hardware and a program. The image processing unit 230 includes one including a geometry calculation unit 232 (three-dimensional coordinate calculation unit) and a drawing unit 240 (rendering unit).

  The geometry calculation unit 232 performs various geometry calculations (three-dimensional coordinate calculation) such as coordinate conversion, clipping processing, perspective conversion, or light source calculation. Then, the object data (after the perspective transformation) after the geometry processing (object vertex coordinates, vertex texture coordinates, luminance data, or the like) is stored in the main memory 272 of the storage unit 270 and saved, for example.

  The drawing unit 240 draws the object in the frame buffer 274 based on the object data after the geometry calculation (after perspective transformation) and the texture stored in the texture storage unit 276.

  Examples of the drawing unit 240 include a texture mapping unit 242 and a shading processing unit 244. Specifically, it can be implemented by a drawing processor. The drawing processor is connected to a texture storage unit, various tables, a frame buffer, a VRAM, and the like via a bus and further connected to a display.

  The texture mapping unit 242 reads the environment texture from the texture storage unit 276, and maps the read environment texture to the object.

  The shading processing unit 244 performs shading processing on the object. For example, the geometry processing unit 232 performs light source calculation, and obtains the luminance (RGB) of each vertex of the object based on the light source information for shading processing, the illumination model, the normal vector of each vertex of the object, and the like. Based on the luminance of each vertex, the shading processing unit 244 obtains the luminance of each dot on the primitive surface (polygon, curved surface) by, for example, phone shading or Gouraud shading.

  An example of the geometry calculation unit 232 includes a normal vector processing unit 234. The normal vector processing unit 234 may perform a process of rotating the normal vector of each vertex of the object (in a broad sense, the normal vector of the object surface) with a rotation matrix from the local coordinate system to the world coordinate system. .

  The game machine of the present invention includes the image generation device of the present invention in the image processing unit. As a result, the circuit elements can be shared, and the control destination from the game processing unit 220 can be unified with respect to the image processing. By combining the processing unit for vector, 2D, and 3D image processing into one, it is possible to System control can be avoided and the complexity of the system can be reduced. If the configuration of the game machine is used as appropriate, it is possible to obtain a device that can also function as an image display device in a slot machine, a pachinko gaming machine, or the like.

[Basic operation of game console]
When the system is turned on, part or all of the information stored in the information storage medium 280 is transferred to the storage unit 270, for example. A game processing program is stored in, for example, the main memory 272, and various data is stored in the texture storage unit 276, a table (not shown), or the like.

  Operation information from the operation unit 260 is transmitted to the processing unit 200 via, for example, a serial interface or a bus (not shown), and sound processing and various image processing are performed. The sound information processed by the sound processing unit 250 is transmitted to the sound output unit 292 via the bus and released as sound. Also, save information stored in a portable information storage device 194 such as a memory card is transmitted to the processing unit 200 via a serial interface or bus (not shown), and predetermined data is read from the storage unit 170.

  The image processing unit 230 performs various image processing in accordance with instructions from the game processing unit 220 and the like. Specifically, the geometry calculation unit 232 performs various geometry calculations (three-dimensional coordinate calculation) such as coordinate conversion, clipping processing, perspective conversion, or light source calculation. Then, the object data (after the perspective transformation) after the geometry processing (object vertex coordinates, vertex texture coordinates, luminance data, or the like) is stored in the main memory 272 of the storage unit 270 and saved, for example. Next, the drawing unit 240 draws the object in the frame buffer 274 based on the object data after the geometry calculation (after perspective transformation) and the texture stored in the texture storage unit 276.

  The information stored in the frame buffer 274 is transmitted to the display unit 290 via the bus and drawn. In this way, it functions as a game machine having computer graphics.

  Since the game machine of the present invention includes the image generation apparatus of the present invention in the image processing unit, the hardware scale can be reduced by sharing circuit elements and the like, and the vector, 2D, and 3D image processing unit is unified. As a result, it is possible to reduce the wasteful hardware / control processing by preventing the system from becoming complicated. As described above, since development / manufacturing costs and power consumption can be reduced, the present invention is particularly suitable for portable game machines and the like.

[Configuration of mobile phone]
FIG. 15 is a block diagram of an embodiment of the present invention (a mobile phone with a computer graphic function). The embodiment shown in this block diagram can be suitably used particularly as a mobile phone with a three-dimensional computer graphic function, particularly as a mobile phone with a game function or a mobile phone with a navigation function.

  As shown in FIG. 15, this mobile phone includes a control unit 221, a memory unit 222 that stores a program and image data for the control unit 221, and serves as a work area such as a control unit and a communication unit, and a wireless A wireless communication function unit 223 for communication, an imaging unit 224 such as a CCD camera that captures still images and moving images and converts them into digital signals, and an LCD display for displaying images and characters Unit 225, operation unit 226 including numeric keys and various function keys, voice input unit 227 such as a microphone for voice calls, voice output unit 228 for outputting sounds such as a receiver and a speaker, and the mobile phone A battery 229 for operating the terminal and a power supply unit 230 that stabilizes the battery 229 and distributes the battery 229 to each functional unit are included.

The control unit 201 performs various processing such as control of the entire mobile phone system, instruction instruction to each block in the system, game processing, image processing, and sound processing. The function of the control unit 221 can be realized by hardware such as various processors (CPU, DSP, etc.) or ASIC (gate array, etc.), or a given program (game program).

  More specifically, the control unit includes an image processing unit (not shown), and the image processing unit includes a geometry calculation unit such as a geometry calculation circuit and a drawing unit (renderer). Furthermore, a texture generation circuit, an illumination processing circuit, or a display circuit may be provided. Furthermore, the drawing processing circuit in the computer or game machine described above may be provided as appropriate.

  Since the mobile phone of the present invention includes the image generation apparatus of the present invention as a geometry calculation unit and a drawing unit included in the control unit, the hardware scale can be reduced by sharing circuit elements and the like. By unifying the 3D image processing unit, it is possible to prevent a situation where the system is complicated, thereby reducing wasteful hardware / control processing. As described above, since development / manufacturing costs and power consumption can be reduced, the present invention is suitably used for small-sized telephones such as mobile phones.

[Operation example of mobile phone]
First, the voice communication operation will be described. For example, voice input to the voice input unit 227 is converted into digital information by the interface, subjected to predetermined processing by the control unit 221, and output as a radio signal from the radio communication function unit 223. Also, when receiving the other party's sound information, the wireless communication function unit 223 receives the wireless signal, undergoes a predetermined conversion process, and then is output from the audio output unit 228 under the control of the control unit 221. The

  Next, the operation and processing for processing an image are basically the same as the operation and processing in the computer or game machine described above. When processing information is input from the operation unit 224 via an interface or bus (not shown), for example, based on an instruction of the image processing unit in the control unit 221, a geometry processor or the like can change a work area such as a RAM, various tables, or the like. Is used as appropriate to perform geometry calculations. Further, the renderer of the control unit 221 performs a rendering process based on a command from the image processing unit in the control unit 221. Image information appropriately subjected to culling processing, clipping processing, anti-aliasing processing, etc. is subjected to predetermined drawing processing by a drawing processor, stored in a frame buffer, and displayed as an image on a display unit. In this way, 3D computer graphics are displayed.

  Since the mobile phone of the present invention includes the image generation device of the present invention as a geometry calculation unit and drawing unit included in the control unit, the hardware scale can be reduced by sharing circuit elements and the system is complicated. Therefore, it is suitable for small phones such as mobile phones.

[Configuration of car navigation system]
FIG. 16 is a block diagram of an embodiment (navigation system) of the present invention. The embodiment represented by this block diagram can be suitably used particularly as a car navigation with a three-dimensional computer graphic function. As shown in FIG. 16, this navigation system includes a GPS unit 241, an autonomous positioning unit 242 as an arbitrary element, a map storage unit 243, a control unit 244, a display unit 245, and a map matching as an arbitrary element. And part 246.

  The GPS unit 241 includes a GPS receiver, and is a GPS unit that simultaneously receives radio waves from a plurality of GPS satellites and obtains vehicle positioning data. The GPS unit 241 obtains the absolute position of the vehicle from the data received by the GPS receiver. This positioning data includes the vehicle traveling direction information and the elevation angle information in addition to the vehicle position information.

  The autonomous positioning unit 242 includes an autonomous sensor, and is an autonomous positioning unit that calculates the moving distance and moving direction of the vehicle from the output data of the autonomous sensor. Examples of the autonomous sensor include a wheel side sensor that detects a signal corresponding to the number of rotations of the wheel, an acceleration sensor that detects the acceleration of the vehicle, and a gyro sensor that detects the angular velocity of the vehicle. In this example, a three-dimensional gyro sensor that can also detect the attitude angle in the pitch motion direction of the vehicle (hereinafter referred to as “pitch angle”) is used as the gyro sensor. Therefore, the positioning output from the autonomous positioning unit 242 is used. The data includes the vehicle pitch angle.

  The map storage unit 243 is a map storage unit that stores digital map data having 2D map information, 3D road information, and 3D building information. As a storage medium constituting the map storage unit 243, a CD-ROM and a hard disk can be cited. The map data is preferably divided and stored in a plurality of blocks because it takes a long time to read the map data. The road information may include information indicating major points (nodes) such as intersections and inflection points. The node information includes coordinate data at the points, and the road connects each node. You may approximate as a straight line (link). The three-dimensional road information in this system means that the node information has three-dimensional coordinate data.

  The control unit 244 performs predetermined control such as reading out map data of a predetermined area corresponding to the position of the vehicle from the map storage unit 243 based on the vehicle position information obtained from the GPS unit 241 or the autonomous positioning unit 242. belongs to.

The display unit 245 is for displaying the map data read by the positioning control unit 244.

  The map matching unit 246 is for correcting the position of the vehicle on the road based on the positioning data of the vehicle and the three-dimensional road information of the map data.

  The car navigation system of the present invention includes, for example, a control unit including a geometric operation unit and a drawing unit, and includes the image generation apparatus of the present invention. As a result, by unifying the vector, 2D, and 3D image processing units, it is possible to prevent a situation where the system is complicated, thereby reducing control processing.

[Operation example of car navigation system]
The GPS unit 241 simultaneously receives radio waves from a plurality of GPS satellites and obtains vehicle positioning data. The autonomous positioning unit 242 calculates the moving distance and moving direction of the vehicle from the output data of the autonomous sensor. The control unit 244 performs predetermined processing on the data obtained from the GPS unit 241 or the autonomous positioning unit 242 to obtain vehicle position information. Based on the vehicle position information, map data of a predetermined area related to the vehicle position is read from the map storage unit 243. In addition, in response to operation information from an operation unit (not shown), the display mode is changed, and map data corresponding to the display mode is read. Further, the control unit 244 performs predetermined drawing processing based on the position information, and displays a 3D building image, 3D map image, 3D car image, and the like. Further, culling processing is performed based on the Z value. The display unit 245 displays the map data read by the control unit 244.

  The car navigation system of the present invention includes, for example, the image generation apparatus of the present invention in the geometric operation unit and the drawing unit, so that the hardware scale can be reduced by sharing circuit elements and the like, and vector, 2D, and 3D image processing can be performed. By unifying the parts, it is possible to prevent the system from becoming complicated.

  FIG. 17 is a block diagram showing the main control circuit 361 of the pachislot machine. As shown in FIG. 17, the main control circuit 361 includes a microcomputer (hereinafter referred to as “microcomputer”) 363 as a main component, and is added to a circuit for random number sampling. The microcomputer 363 has a main CPU (central processing unit) 364 that performs control operations in accordance with a preset program, a ROM 365 that stores programs (including image rendering programs) and various table data, and a backup function. And a control RAM (hereinafter simply referred to as RAM) 366.

  Connected to the main CPU 364 are a clock pulse generation circuit 367 and a frequency divider 368 for generating a reference clock pulse, a random number generator 369 for generating a random number within a certain range, and a sampling circuit 370 for specifying one of the generated random numbers. Has been. Further, the main CPU 364 is connected to an I / O port 371 that exchanges signals with peripheral devices (actuators) described later.

  Here, the storage unit of R0M365 is divided so as to store a winning probability table, a symbol table, a winning symbol combination table, a sequence program, a notification effect table, and an effect image program, and further, the start lever 328 is operated (start operation). A probability lottery table used for determination of random number sampling performed each time, a stop table for determining a reel stop mode according to the operation of the stop button, and the like are stored.

  The main actuators whose operation is controlled by a control signal from the microcomputer 363 include stepping motors 345L, 345C, 345R for rotating the reels 305, 306, 307, various lamps (betting number display lamps 319-321, start lamps). 329, WIN lamp 330, insert lamp 332), various display units (credit display lamp 323, gaming state display lamps 324 to 327, bonus count display lamp 318, dividend display lamp 322), and hopper 372 for storing medals. . These are driven by a motor drive circuit 373, lamp drive circuits 374, display drive circuits 375 and hopper drive circuits 376, respectively. These drive circuits 373 to 376 are connected to the main CPU 364 via the I / O port 371 of the microcomputer 363.

  The main input signal generating means for generating an input signal necessary for the microcomputer 363 to generate a control signal is a inserted medal sensor 331S for detecting a medal inserted from a medal slot, and detecting a start lever operation. There are a start switch 328S, the BET switch 33 described above, and a credit medal settlement switch 334. Further, there is a reel position detection circuit 377 that receives the output pulse signal from the photo sensor and detects the rotational position of each reel 305, 306, 307. Note that the photosensor is included in the drive mechanism of each of the reels 305 to 307 and is not shown in the drawing.

  Further, the input signal generating means includes a reel stop signal circuit 378 that generates a signal for stopping the corresponding reel when the stop buttons 335 to 337 are pressed, and a medal that counts the number of medals paid out from the hopper 372. There are a detection unit 372S and a payout completion signal generation circuit (not shown).

  A sub control circuit 381 is connected to the I / O port 371. FIG. 18 is a block diagram showing a sub control circuit of the pachislot machine.

  The sub control circuit 381 executes display control of the display device 350 and sound output control from the speakers 382L and 382R based on a control command (command) from the main control circuit 361. The sub-control circuit 381 is preferably formed on a substrate different from the substrate constituting the main control circuit 361, and the sub-microcomputer 83 is a main component, and an image control circuit as display control means of the display device 350. 391, a sound source IC 388 that controls output sound from the speakers 382L and 382R, and a power amplifier 389 as an amplifier.

  The sub microcomputer 383 includes a sub CPU 384 that performs a control operation in accordance with a control command transmitted from the main control circuit 61, and a program ROM 385 and a work RAM 386 as storage means. In this example, the sub control circuit 381 does not include a clock pulse generation circuit, a frequency divider, a random number generator, and a sampling circuit, but is configured to execute random number sampling on the operation program of the sub CPU 384.

  The program ROM 385 stores a control program executed by the sub CPU 84. The work RAM 386 is configured as a temporary storage unit when the control program is executed by the sub CPU 384.

  The image control circuit 391 includes an image control CPU 392, an image control program ROM 394, an image control work RAM 393, an image control IC 398, an image ROM 396, and a video RAM 397.

  Here, the image control CPU 392 determines the display contents on the display device 350 in accordance with the image control program stored in the image control program ROM 394 based on the parameters set by the sub microcomputer 383. The image control program ROM 394 stores an image control program related to display on the display device 350 and various selection tables. The image control work RAM 393 is configured as a temporary storage unit when the image control CPU 392 executes the image control program. The image control IC 398 forms an image corresponding to the display content determined by the image control CPU 392 and outputs the image to the display device 350. The image ROM 396 stores dot data for forming an image. The video RAM 397 is configured as a temporary storage unit when the image control IC 398 forms an image.

  The output from the main control circuit 361 is input to the sub CPU 384 via the IN port 387, and the output from the sub CPU 384 is input to the image control CPU 392 via the OUT port 390 and the IN port 395.

  Next, the operation of the pachislot machine of this embodiment will be described. When the player inserts a medal into the medal slot, a detection signal is sent from the inserted medal sensor 331S to the main CPU 364, and the main CPU 364 detects the insertion of the medal, and bet number display lamps 319 to 321 corresponding to the bet number are turned on. To do. When the player presses the start lever 328, an operation signal is transmitted from the start switch 328S to the main CPU 364, and the main CPU 364 detects the operation of the start lever 328 and sends a start signal to the motor drive unit 373 via the I / O port 371. To rotate the reels 305, 306, and 307 all at once.

  When the start switch 328S detects the operation of the start lever, the main CPU 364 fetches the random number value generated by the random number generator 369 by the sampling circuit 370 and compares the fetched random number value with the determination value stored in the ROM 365. Then, an internal lottery will be performed to determine the winning and losing. The lottery result is stored in a predetermined area of the RAM 366. When an internal winning is made, a flag corresponding to the type of winning is set in the predetermined area of the RAM 366. Here, the flag set in the game is basically extinguished when the game ends, but only the BB or RB with a low internal winning probability wins all the symbols corresponding to the set flag. May be carried over multiple games.

  Furthermore, when the start switch 328S detects the operation of the start lever, the main CPU 364 reads out an effect instruction command for displaying an effect image on the display device 350 over a plurality of games from the ROM 365, and this is read via the I / O port 371. The data is sent to the control circuit 381. The main CPU 364 holds an effect instruction command to be sent to the sub control circuit 381 in a predetermined area of the RAM 366.

  The sub-control circuit 381 displays an effect image according to the effect instruction command input from the main CPU 364 on the display device 350, and an effect instruction command input for each effective operation of the start lever 328 that triggers the internal winning. Follow the steps to display the image.

  Next, the main CPU 364 checks the internal lottery result on the RAM 366, selects and determines a stop table corresponding to the internal lottery determination result, and reads the corresponding stop table from the ROM 365 onto the RAM 366.

  Thereafter, when the player operates one of the stop buttons 335, 336, and 337, an operation signal is transmitted from the reel stop signal circuit 378 to the main CPU 364, and the main CPU 364 receives the reels 305 and 306 from the reel position detection circuit 377. , 307 and the stop table on the RAM 366, the reels 305, 306, 307 are controlled to stop.

  As a result, unless the player has won the internal lottery, the reels 305, 306, and 307 are controlled so that the winning symbols are not aligned even if the player operates the stop buttons 335, 336, and 337 at any timing. Is done. On the other hand, when a winning table is selected in the internal lottery and the symbol corresponding to the internal winning result is selected, the symbol corresponding to the internal winning is determined depending on the operation timing of the stop buttons 335, 336 and 337 of the player. There is a stop control in which

  That is, when the internal lottery result is a win, the main CPU 364 sends a stop signal based on the pull-in stop control to the motor drive unit 373, and releases the reels 305, 306, 307 corresponding to the operated stop buttons 335, 336, 337. At this time, the reel stop control is performed such that the winning symbols on the reels 305, 306, and 307 are stopped on an effective stop line.

  When the internal lottery result is out, the main CPU 364 operates the stop buttons 335, 336, and 337 so that the symbols related to winning are not stopped on the valid stop line by operating the stop buttons 335, 336, and 337. The reels 305, 306, and 307 corresponding to are stopped.

The pachislot machine of the present invention includes, for example, the image generation apparatus of the present invention as an image control program or an image control CPU included in the sub-control circuit 381, so that the hardware scale can be reduced by sharing circuit elements and the like. In addition, by unifying the vector, 2D, and 3D image processing units, it is possible to prevent the system from becoming complicated. As a result, useless hardware / control processing can be reduced. As described above, since development / manufacturing costs and power consumption can be reduced, it is also suitably used in pachislot machines and the like.

Claims (14)

Edge information storage memory (2) for storing polygon edge information at a pixel;
A vector data storage memory (3) for storing polygonal shape data in vector format;
An edge information generating unit (4) for performing rasterization processing based on polygon shape data stored in the vector data storage memory, and writing out polygon edge information as a rasterization result to the edge information storage memory;
A layer image storage memory (5) for storing at least image information on the background and image information for each of a plurality of layers;
Using the edge information stored in the edge information storage memory, when painting the inside of the image defined in the vector format, the image information on the background and the image information for each layer stored in the layer image storage memory are read out. An image composition unit (6) that performs image composition in units of pixels by superimposing vector format images and image information for each layer and performing image processing operations in units of pixels;
A result image storage memory (7) for storing the image synthesized by the image synthesis unit;
An image generation apparatus (1) comprising:   2. The image generation device according to claim 1, wherein the vector data storage memory and the result image storage memory store information as stream format data. The edge information generation unit includes an anti-aliasing processing unit that performs anti-aliasing processing, writes the edge information subjected to anti-aliasing processing to the edge information storage memory,
The image generation apparatus according to claim 1, wherein the image composition unit performs image composition subjected to anti-aliasing processing using edge information subjected to anti-aliasing processing. The edge information generation unit is configured to store, in the edge information storage memory, image edge information, transparency for each pixel, pixel edge based on a vector format rasterization result stored in the vector data storage memory. Write the rasterization progress code in the horizontal and vertical directions in the part and the number of overlapping edge parts at the time of rasterization to the edge information storage memory,
The image synthesis unit uses the edge information stored in the edge information storage memory to fill the inside of the image defined in the vector format with the background image information stored in the layer image storage memory and a plurality of pieces of image information. The image information for each layer is read out, and the vector format image and the image information for each layer are superimposed,
Perform blending calculation for each pixel using the transparency for each pixel stored in the edge information storage memory,
Based on the rasterized signal code in the horizontal direction and the vertical direction stored in the edge information storage memory, image synthesis processing is performed in units of lines or blocks,
A determination is made as to whether or not to fill using the number of overlapping edge portions stored in the edge information storage memory;
Perform pixel-by-pixel image composition by performing pixel-by-pixel image processing operations.
The image generation apparatus according to claim 1. The edge information generation unit includes an anti-aliasing processing unit that performs anti-aliasing processing,
The anti-aliasing processing unit
Edge information at the pixel;
An area calculation circuit for determining an area S of a portion of the pixel divided by the edge using a plurality of sampling points in the pixel;
One or a plurality of sampling points used for color synthesis from a plurality of sampling points in the pixel or a color selection circuit for selecting a color at the sampling points;
An anti-aliasing circuit comprising an area S calculated by the area calculation circuit and a color synthesis circuit that determines a color of the pixel using a color selected by the color selection circuit;
The image generation apparatus according to claim 1.   The image generation apparatus according to claim 1, wherein the image composition unit performs image processing calculation in units of lines or blocks, and performs image composition in units of lines or blocks.   2. The image according to claim 1, wherein the image composition unit includes one or both of a color space conversion processing unit and a color correction processing unit, and performs image composition by performing color space conversion processing or color correction processing on a pixel basis. Generator.   The image composition unit includes a geometric operation processing unit including one or both of an image rotation process and an image size adjustment process, and performs image composition by performing a rotation process or an image size adjustment process on a layer image. The image generating apparatus according to 1. The image composition unit includes a geometric operation processing unit including one or both of image rotation processing and image size adjustment processing,
The geometric calculation processing unit
A vertex data output device for outputting vertex data;
A vertex computing device connected to the vertex data output device and performing a fixed computation on the vertex;
A polygon computing device connected to the vertex computing device and performing fixed computations on polygons;
Connected to one or more of the vertex data output device, the vertex computing device, and the polygon computing device at the input source, and connected to one or two of the vertex computing device and the polygon computing device at the output destination The image generation apparatus according to claim 1, wherein the image generation apparatus is a geometric calculation processing unit including one or a plurality of general-purpose calculation devices.   A computer comprising the image generation apparatus according to claim 1.   A game machine comprising the image generating apparatus according to claim 1.   A mobile phone comprising the image generating apparatus according to claim 1.   A navigation system comprising the image generation apparatus according to claim 1.   A slot machine comprising the image generating apparatus according to claim 1.

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