JPWO2007000798A1 - Semiconductor device - Google Patents

Abstract

The IC card chip 1c has an IC card function and a memory card function. A semi-finished module (SFM) 4 having a memory card function part of the IC card chip 1c is prepared. The SFM 4 includes a wiring board 4c, two semiconductor chips 4d and 4e mounted on the first main surface, and a resin sealing body 4f for sealing them. A memory circuit is formed on the semiconductor chip 4d, and an interface controller circuit for controlling the operation of the memory circuit M is formed on the semiconductor chip 4e. A plurality of external terminals 4 a are arranged on a part of the upper surface of the SFM 4 so as to be exposed to the outside of the SFM 4.

Description

  The present invention relates to a semiconductor device technology, and more particularly to a technology effective when applied to a semiconductor device used for a card type information medium such as an IC card.

  Card-type information media such as IC cards and memory cards are small, thin, and light, and thus are excellent in portability, portability, and convenience, and are widely used in various fields.

  An IC card is a card-type information medium in which an IC chip is embedded in a cash card-sized plastic thin plate so that information can be recorded. IC cards are excellent in authenticity and tamper resistance. For example, credit cards, cash cards, ETC (Electronic Toll Collection system) system cards, commuter passes, mobile phone cards or authentication cards, etc. In the fields where high security such as communication, distribution and authentication is required, the spread is progressing. As for such an IC card, for example, FIG. 9 of Japanese Patent Laid-Open No. 2001-357376 (Patent Document 1) has a configuration in which a SIM (Subscriber Identify Module) type card is fixed by providing a bridge at the opening of the frame card. It is disclosed.

On the other hand, the memory card is a card type information medium that employs a flash memory as a storage medium. Since a memory card is smaller than an IC card and can easily write and read a large amount of information at a high speed, the memory card is, for example, a digital camera, a notebook personal computer, a portable music player, a cellular phone or the like. It has become widespread as a recording medium for portable information devices that require high portability. Typical memory card standards include SD (Secure Digital) memory cards (standards standardized by the SD Card Association), miniSD, MMC (Multi Media Card, registered trademark of Infineon Technologies AG), RS- There are MMC (Reduced Size MMC). Such a memory card is described in, for example, International Patent Publication No. WO 02/099742 A1 (Patent Document 2). For the purpose of improving security, a flash memory chip and an IC card chip capable of executing security processing are described. And a configuration of a memory card including a controller chip for controlling the circuit operation of these chips.
JP 2001-357376 A (FIG. 9 etc.) International Patent Publication Number WO 02/099742 A1

  By the way, the present inventor studied to improve the function of the IC card by integrating the function of the IC card and the function of the memory card. As a result, it has been found that how to efficiently provide a card type information medium having a function having a function of an IC card and a function of a memory card and a high reliability is an important issue.

  An object of the present invention is to propose a technique capable of efficiently providing a card type information medium having a function having an IC card function and a memory card function and a high reliability.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The present invention relates to a wiring board, a semiconductor chip having a memory card function mounted on a main surface of the wiring board, and a resin for sealing the semiconductor chip in a semiconductor device having a memory card function of a card type information medium. A plurality of terminals electrically connected to the semiconductor chip are arranged on a part of the main surface of the wiring board, and at least a part of the plurality of terminals is It is exposed outside the resin sealing body.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  That is, it is possible to efficiently provide a card type information medium having a function having an IC card function and a memory card function and high reliability.

It is a whole top view of the 1st main surface of an IC card which has a semiconductor device which is one embodiment of the present invention. It is a whole top view of the 2nd main surface opposite to the 1st main surface of the IC card of FIG. FIG. 3 is a side view of the IC card of FIGS. 1 and 2. It is a whole top view of the 2nd main surface of an IC card chip. FIG. 5 is an overall plan view of the inside of the IC card chip of FIG. 4 as seen through the first main surface side. It is sectional drawing of the X1-X1 line | wire of FIG. It is explanatory drawing of the wiring connection of an IC card chip. It is a whole top view of the 1st main surface of the wiring board of an IC card chip. It is a whole top view of the 1st main surface of the IC card chip which shows the modification of the formation state of the resin sealing body of an IC card chip. FIG. 10 is a side view of the IC card chip of FIG. 9. It is a whole top view of the 1st main surface of the IC card chip which shows the modification of the formation state of the resin sealing body of an IC card chip. It is a side view of the IC card chip of FIG. It is explanatory drawing which shows a mode that the IC card chip of FIG. 11 is bent. It is a whole top view of the 1st main surface of the IC card chip which shows the modification of the formation state of the resin sealing body of an IC card chip. It is explanatory drawing of an example of the IC card microcomputer circuit formed in the IC chip in an IC card chip. It is explanatory drawing of an example of the interface controller circuit formed in the semiconductor device in an IC card chip. It is a principal part enlarged plan view by the side of the 1st main surface of the tape for wiring board formation in the manufacturing process of the IC card chip which has the semiconductor device which is one embodiment of this invention. FIG. 18 is an enlarged plan view of a main part on the first main surface side of the tape for forming a wiring board during the manufacturing process of the IC card chip following FIG. 17. FIG. 19 is an enlarged plan view of a main part on the first main surface side of the wiring board forming tape in the manufacturing process of the IC card chip following FIG. 18. FIG. 20 is an enlarged plan view of the main part of the first main surface side of the wiring board forming tape in the IC card chip manufacturing process following FIG. 19; FIG. 21 is an enlarged plan view of the main part of the first main surface side of the wiring board forming tape in the manufacturing process of the IC card chip following FIG. 20; 1 is an overall perspective view of a semiconductor device according to an embodiment of the present invention. It is the top view which looked at the semiconductor device of FIG. 22 from the upper surface. It is the top view which looked at the semiconductor device of FIG. 22 from the back surface. FIG. 23 is an overall plan view of the inside of the semiconductor device of FIG. 22 as seen through the top surface side. It is sectional drawing of the X2-X2 line | wire of FIG. FIG. 26 is an enlarged plan view of a main part of the semiconductor device of FIG. 25. It is sectional drawing of the X3-X3 broken line of FIG. FIG. 23 is a plan view of an external terminal of the semiconductor device of FIG. 22. FIG. 23 is a perspective view showing an example of wire connection between semiconductor chips using relay wiring in the semiconductor device of FIG. 22. FIG. 23 is a perspective view showing another example of wire connection of a semiconductor chip of the semiconductor device of FIG. 22. FIG. 32 is a side view of a wire connection example of a semiconductor chip of the semiconductor device of FIG. 31. It is principal part sectional drawing of the semiconductor chip which shows an example of the mitigation countermeasure of the damage by a bonding wire. It is principal part sectional drawing of the semiconductor chip which shows the other example of the mitigation countermeasure of the damage by a bonding wire. FIG. 28 is a perspective view showing still another example of wire connection of a semiconductor chip of the semiconductor device of FIG. 27. FIG. 36 is a side view of a wire connection example of a semiconductor chip of the semiconductor device of FIG. 35. FIG. 23 is an overall plan view of the first main surface side of the wiring board base body during the manufacturing process of the semiconductor device of FIG. 22; FIG. 38 is an overall plan view of the first main surface side of the wiring board mother body during the manufacturing process of the semiconductor device following FIG. 37; FIG. 39 is a cross-sectional view of the wiring board base body during the manufacturing process of the semiconductor device following FIG. 38; FIG. 40 is a cross-sectional view of the wiring board matrix during the manufacturing process of the semiconductor device following FIG. 39; FIG. 41 is an enlarged cross-sectional view of a main part of the wiring board base body in the manufacturing process of the semiconductor device at the stage of FIG. 40; The entire first main surface of the wiring board base body showing the direction in which the sealing resin is poured and the direction in which the air in the cavity of the mold escapes to the outside during the sealing resin injection process, which is the manufacturing process of the semiconductor device subsequent to FIG. It is a top view. FIG. 43 is an overall plan view of a first main surface of a wiring board base body showing a modification of FIG. 42. FIG. 43 is a cross-sectional view of the wiring board base body during the manufacturing process of the semiconductor device following FIG. 41 and FIG. 42; FIG. 45 is a cross-sectional view of the wiring board base body during the manufacturing process of the semiconductor device following FIG. 44. FIG. 46 is a cross-sectional view of the wiring board base body during the manufacturing process of the semiconductor device following FIG. 45; It is a whole top view of the 2nd main surface of an IC card chip which has a semiconductor device which is other embodiments of the present invention. It is the whole top view which looked at the inside of the IC card chip of FIG. 47 through the 1st main surface side. It is sectional drawing of the X4-X4 line | wire of FIG. It is a whole top view of the 2nd main surface of an IC card chip which has a semiconductor device which is other embodiments of the present invention. It is sectional drawing of the X5-X5 line | wire of FIG. It is the whole top view which looked at the inside of the IC card chip which has a semiconductor device which is other embodiments of the present invention from the 1st principal surface side. It is sectional drawing of the X6-X6 line | wire of FIG. It is explanatory drawing of the thickness of an IC card chip. FIG. 53 is an explanatory diagram of the thickness of the IC card chip of FIG. 52. It is a whole perspective view of the semiconductor device which is other embodiments of the present invention. FIG. 57 is a plan view of the semiconductor device of FIG. 56 viewed from above. FIG. 57 is a plan view of the semiconductor device of FIG. 56 viewed from the back side. FIG. 57 is an overall plan view of the inside of the semiconductor device of FIG. 56 as seen through the top surface side. FIG. 60 is an overall plan view of the inside of the semiconductor device of FIG. 59 viewed from the top side with the semiconductor chip of FIG. 59 removed; FIG. 60 is an enlarged plan view of a main part of the semiconductor device of FIG. 59. It is sectional drawing of the X7-X7 broken line of FIG. It is the whole top view which looked at the inside of the IC card chip which has a semiconductor device which is other embodiments of the present invention from the 1st principal surface side. FIG. 64 is an overall plan view showing a route of IC chip wiring on the first main surface of the wiring board of the IC card chip of FIG. 63; It is the whole top view which looked at the inside of the IC card chip which has a semiconductor device which is other embodiments of the present invention from the 1st principal surface side. FIG. 66 is an overall plan view of the semiconductor device of FIG. 65. It is a whole perspective view of the semiconductor device which is other embodiments of the present invention. FIG. 68 is an overall plan view of an example of the back surface of the semiconductor device of FIG. 67. FIG. 68 is an overall plan view of another example of the back surface of the semiconductor device of FIG. 67; FIG. 68 is an overall plan view of an example when the inside of the semiconductor device of FIG. 67 is viewed through the top surface side; FIG. 71 is an enlarged plan view of a main part of the semiconductor device of FIG. 70. It is sectional drawing of the X8-X8 broken line of FIG. FIG. 68 is an overall plan view of another example in which the inside of the semiconductor device of FIG. 67 is viewed through the top surface side. FIG. 74 is an essential part enlarged plan view of the semiconductor device of FIG. 73; FIG. 75 is a cross sectional view taken along broken line X9-X9 in FIG. 74. FIG. 68 is an overall plan view of the inside of an IC card chip having the semiconductor device of FIG. 67 viewed through the first main surface side. FIG. 77 is a cross-sectional view taken along line X10-X10 in FIG. 76. FIG. 68 is a cross-sectional view of an example of a mounted state of the semiconductor device of FIG. 67. FIG. 68 is a cross-sectional view of another example of the mounting state of the semiconductor device of FIG. 67; FIG. 68 is a cross-sectional view of still another example of the mounted state of the semiconductor device of FIG. 67. It is the whole top view which looked at the inside of the IC card chip which has a semiconductor device which is other embodiments of the present invention from the 1st principal surface side. It is sectional drawing of the X11-X11 line | wire of FIG. 83 is a cross-sectional view taken along line X11-X11 in FIG. 81 when a solder resist is provided on the second main surface of the wiring board of the IC card chip in FIGS. 81 and 82. FIG. It is a principal part enlarged plan view by the side of the 1st main surface of the tape for wiring board formation in the manufacturing process of the IC card chip which has the semiconductor device which is other embodiment of this invention. FIG. 85 is an essential part enlarged plan view of the first main surface side of the wiring board forming tape in the IC card chip manufacturing process following FIG. 84; FIG. 85 is an essential part enlarged plan view of the first main surface side of the wiring board forming tape in the IC card chip manufacturing process following FIG. 85; FIG. 89 is an essential part enlarged plan view of the first main surface side of the wiring board forming tape in the IC card chip manufacturing process following FIG. 86; FIG. 89 is an essential part enlarged plan view of the first main surface side of the wiring board forming tape in the manufacturing process of the IC card chip following FIG. 87; FIG. 89 is an essential part enlarged plan view of the first main surface side of the tape for forming a wiring board in the IC card chip manufacturing process following FIG. 88; It is sectional drawing of the semiconductor device before mounting. It is sectional drawing of the semiconductor device after mounting. It is the whole top view which looked at the inside of the IC card chip which has a semiconductor device which is other embodiments of the present invention from the 1st principal surface side. FIG. 93 is an overall plan view of the semiconductor device of FIG. 92.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges. Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted as much as possible. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is an overall plan view of a first main surface of an IC (Integrated Circuit) card 1 having the semiconductor device of the first embodiment, and FIG. 2 is a second surface opposite to the first main surface of the IC card 1 of FIG. FIG. 3 shows a side view of the IC card 1 of FIGS. 1 and 2. In addition, the code | symbol X shows the 1st direction (longitudinal direction of the IC card 1), and the code | symbol Y has shown the 2nd direction (width direction of the IC card 1) orthogonal to a 1st direction.

  The IC card 1 is a subscriber identity module (card type information medium) called, for example, a SIM (Subscriber Identity Module) card or a UIM (User Identity Module) card. The external shape of the IC card 1 is formed in, for example, a rectangular shape, and the external size is, for example, about 85.6 mm × 54 mm × 0.76 mm.

  For example, polyvinyl chloride (PVC), polycarbonate, polyolefin (polypropylene, etc.), polyethylene terephthalate (polyethylene terephthalate: PET), polyethylene terephthalate glycol (PET-G). Alternatively, it is made of a plastic such as ABS (acrylonitrile / butadiene / styrene resin).

  An opening 1b penetrating between the first main surface and the second main surface is formed at a position away from the center of the frame body portion 1a of the IC card 1 to the corner portion side. The IC card chip (IC card main body) 1c is fitted and well fitted in a state of being supported by being joined to and supported by the frame body portion 1a by the support portion 1d.

  This IC card chip (hereinafter referred to as a card chip) 1c combines a function as a so-called IC card capable of executing security processing and a function as a so-called memory card having a larger capacity and a higher function than the IC card. This is a highly functional subscriber identification module. That is, the card chip 1c can be used as a mobile phone card in which information such as a telephone number and a telephone directory is stored. The card chip 1c has high security such as a credit card, a cash card, an ETC (Electronic Toll Collection system) system card, a commuter pass or an authentication card, such as finance, transportation, communication, distribution and authentication. Can be used in various required fields. In addition, the card chip 1c can be used as a recording medium for portable information devices such as a digital camera, a notebook personal computer, a portable music player, and a mobile phone that require portability. .

  The outer shape of the card chip 1c is formed in, for example, a substantially rectangular shape in conformity with the outer shape standard of a SIM card or UIM card, and one corner on the front side thereof is greatly chamfered for an index. The external dimensions of the card chip 1c are, for example, about 21.4 mm × 12.3 mm × 0.76 mm. On the second main surface of the card chip 1c, eight ISO connection external CA terminals for IC card functions and a plurality of external connection terminals CB for other memory card functions are exposed. Has been. Of the external connection terminals CA for IC card function, the external connection terminal CA1 is a terminal for supplying a high potential side circuit voltage (Vcc), the external connection terminal CA2 is a reset signal terminal, and the external connection terminal CA3 is a clock signal terminal. The external connection terminal CA4 is a reserve terminal that can be used in the future. The external connection terminal CA5 is a reference potential (GND) supply terminal, the external connection terminal CA6 is a program (write) supply terminal, the external connection terminal CA7 is a data input / output signal I / O terminal, and an external connection terminal CA8. Is a reserve terminal that can be used in the future. The card chip 1c can be cut out by cutting the support portion 1d with a simple cutting tool such as a cutter knife or manually.

  4 is an overall plan view of the second main surface of the card chip 1c, FIG. 5 is an overall plan view of the inside of the card chip 1c of FIG. 4 as seen through the first main surface side, and FIG. 5 is a sectional view taken along line X1-X1, FIG. 7 is an explanatory diagram of wiring connection of the card chip 1c, and FIG. 8 is an overall plan view of the first main surface of the wiring board 2 of the card chip 1c.

  The wiring board 2 of the card chip 1c is composed of, for example, a tape board or a printed wiring board having a multilayer (two-layer) wiring configuration, and the first main surface and the second main surface that are opposite to each other along the thickness direction. And have. The insulating base material 2a of the wiring board 2 is made of, for example, glass epoxy resin or polyimide resin. Further, the wirings L1 and L2, the die pad DP and the external connection terminals CA and CB of the wiring board 2 are made of, for example, copper (Cu), and the exposed surface thereof has, for example, nickel (Ni) base plating and gold (Au) plating. Is given. A solder resist SR1 is formed on the first main surface of the wiring board 2 so as to cover the wirings L1 and L2. Part of the solder resist SR1 is formed with an opening from which a part of the wirings L1, L2 is exposed, and the part of the wiring L1, L2 exposed from the opening serves as an electrode (connection region). The wirings L1 and L2 on the first main surface of the wiring board 2 and the external connection terminals CA and CB on the second main surface are in the through hole TH1 penetrating between the first and second main surfaces of the insulating base 2a. It is electrically connected through a conductor (for example, copper).

  An IC chip 3 and a semi-finished module (hereinafter referred to as “SFM”) 4 are mounted on the first main surface of the wiring board 2.

  The IC chip 3 is made of a semiconductor chip having, for example, a silicon (Si) single crystal as a substrate, and is mounted on the die pad DP with its main surface facing upward. The IC chip 3 is disposed closer to the end side where the external connection terminal CA is disposed. For example, an IC card microcomputer circuit is formed on the main surface of the IC chip 3. This IC card microcomputer circuit is a circuit having a function as a security controller, and realizes an authenticated function by an evaluation / certification organization of ISO / IEC15408 that can be used for an electronic payment service, for example. A plurality of bonding pads (external terminals, hereinafter referred to as pads) on the main surface of the IC chip 3 are electrically connected to the electrodes of the wiring L1 on the first main surface of the wiring board 2 through bonding wires (hereinafter referred to as wires) W1. It is connected to the. The wire W1 is made of, for example, gold (Au). The first bonding of the wire W1 is performed on the pad side of the IC chip 3, and the second bonding is performed on the electrode side of the wiring board 2. By performing the second bonding with a large impact on the base on the wiring substrate 2 side, damage to the IC chip 3 due to the wire W1 can be prevented, so that the yield and reliability of the card chip 1C can be improved.

  The SFM 4 is a module in which a memory card circuit is formed. A plurality of external terminals 4 a are arranged on a part of the upper surface of the SFM 4 so as to be exposed to the outside of the SFM 4. The SFM 4 is fixed on the first main surface of the wiring board 2 by the adhesive 5 with the plurality of external terminals 4a facing upward. The SFM 4 is arranged on the side where the external connection terminal CB is arranged, that is, on the end side where the large chamfered portion for the index of the wiring board 2 is formed. The SFM 4 is arranged such that the arrangement area of the plurality of external terminals 4 a faces the arrangement side of the IC chip 3. The plurality of external terminals 4a of the SFM 4 are electrically connected to the electrodes of the wiring L2 on the first main surface of the wiring board 2 through the wires W2. The first bonding of the wire W2 is performed on the electrode side of the wiring board 2, and the second bonding is performed on the external terminal 4a side of the SFM 4 (reverse bonding). As shown in FIG. 7, the first bonding of the wire W2 can be performed by the external terminal 4a of the SFM 4 and the second bonding can be performed by the electrode of the wiring board 2, but the external terminal 4a of the SFM 4 and the electrode of the wiring board 2 Therefore, as shown by the broken line A, the wire W2 may come into contact with a part of the SFM 5 (area touch), and a wiring disconnection failure or a wiring short-circuit failure may occur. On the other hand, when the first bonding of the wire W2 is performed on the electrode side of the wiring substrate 2 and the second bonding is performed on the external terminal 4a side of the SFM 4, the loop of the wire W2 can be formed so as to be away from the SFM 4. Even if the distance between the external terminal 4a and the electrode of the wiring board 2 is short, wire bonding can be performed without causing area touch. Further, the second bonding of the wire W2 has a greater impact on the ground than the first bonding, but the external terminal 4a of the SFM 4 is more resistant to impact than the pad of the IC chip 3, so that there is no particular problem. A detailed description of the SFM 4 will be given later.

  Here, the card chip 1c may be inserted into or removed from the socket of the external processing device while being bent in a direction intersecting the first and second main surfaces. In that case, if a module or a semiconductor chip having an IC card function and a memory card function is arranged in the center of the first main surface of the wiring board 2, it is disadvantageous for the bending of the card chip 1c. On the other hand, in the first embodiment, the IC chip 3 for the IC card function and the SFM 4 for the memory card function are separately arranged so that the bending between the IC chip 3 and the SFM 4 is prevented. Advantageous area can be secured.

  The IC chip 3, the wire W1, the electrode, and the like are sealed with a resin sealing body 6 such as an epoxy-based potting resin or an ultraviolet (UV) curable resin. Thereby, the reliability in the connection part including the IC chip 3 and the wire W1 can be ensured. Moreover, in this Embodiment 1, the external terminal 4a of the said SFM4, the wire W2, an electrode, etc. are sealed by a part of the resin sealing body 6. FIG. As a result, the reliability of the connection portion including the wire W2 of the SFM 4 can be improved, and the fixed state of the SFM 4 can be strengthened. FIG. 9 is an overall plan view of the first main surface of the card chip 1c showing a modification of the formation state of the resin sealing body 6, and FIG. 10 is a side view of the card chip 1c of FIG. As shown in FIGS. 9 and 10, a resin sealing body 6 may be provided at the lower part of the side surface of the entire circumference of the SFM 4. Thereby, the fixed state of SFM4 can further be strengthened.

  Further, considering that the card chip 1c may be bent as described above, the resin sealing body 6 is formed of a plastic material having a high elastic ability with respect to a mechanical force such as a silicone gel. Is preferred. Thereby, it is possible to suppress or prevent the resin sealing body 6 from being cracked or cracked when the card chip 1c is bent. In consideration of the bending of the card chip 1c, as shown in FIGS. 6 and 8, the resin sealing body 6 part between the IC chip 3 and the SFM 4 is planarly and cross-sectionally more than other parts. Can also be recessed. FIG. 11 is an overall plan view of the first main surface of the card chip 1c showing a modification of the formation state of the grease sealing body 6, FIG. 12 is a side view of the card chip 1c of FIG. 11, and FIG. It shows how 1c is bent. As shown in FIGS. 11 and 12, the resin sealing body 6 may be completely separated by the IC chip 3 and the SFM 4. As a result, as shown by a broken line in FIG. 11, a region B that is advantageous for bending can be secured between the IC chip 3 and the SFM 4, so that the structure advantageous for bending the card chip 1c as shown in FIG. can do. FIG. 14 is an overall plan view of the first main surface of the card chip 1c showing a modification of the formation state of the resin sealing body 6. In order to completely separate the resin sealing body 6 between the IC chip 3 side and the SFM 4 side, as shown in FIG. 14, the SFM 4 arrangement may be reversed 180 degrees with respect to that shown in FIG. good. That is, the SFM 4 is arranged such that the plurality of external terminals 4a face the end side where the large chamfered portion for the index of the wiring board 2 is formed. Thereby, the resin sealing body 6 can be completely separated between the IC chip 3 side and the SFM 4 side, and as shown by a broken line in FIG. 14, a region B advantageous for bending between the IC chip 3 and the SFM 4. Therefore, it is possible to make the structure advantageous for bending the card chip 1c. Here, when the resin sealing body 6 is completely separated on the IC chip 3 side and the SFM 4 side, for example, the resin sealing body 6 on the IC chip 3 side is intended to ensure reliability such as corrosion resistance. The resin sealing body 6 on the IC chip 3 side and the resin sealing body on the SFM 4 side are formed, for example, by forming the resin sealing body 6 on the SFM 4 side with a material intended to ensure the adhesive strength of the SFM 4. 6 and 6 may be changed in materials and components.

  As shown in FIGS. 6 and 13, the first main surface side of the wiring board 2 is covered with a cap 7 so as to cover the IC chip 3 and the SFM 4. The cap 7 is made of the same material as the frame body 1a of the IC card 1 and the like. The cap 7 and the wiring board 2 are firmly joined by an adhesive 8 filled between them.

  Next, FIG. 15 shows an example of an IC card microcomputer circuit formed on the IC chip 3. The IC card microcomputer circuit 10 includes a CPU (Central Processing Unit) 10a, a RAM 10b as a work RAM (Random Access Memory), a timer 10c, an EEPROM (Electrically Erasable Programmable Read Only Memory) 10d, a coprocessor unit 10e, a mask ROM 10f, a system control. It has an integrated circuit such as a logic 10g, an input / output port (I / O port) 10h, a data bus 10i, an address bus 10j, and other arithmetic circuits.

  The mask ROM 10f is used to store an operation program (encryption program, decryption program, interface control program, etc.) and data of the CPU 10a. The RAM 10b is a work area or a temporary data storage area of the CPU 10a, and is composed of, for example, SRAM or DRAM. When an IC card command is supplied to the I / O port 10h, the system control logic 10g decodes it and causes the CPU 10a to execute a processing program necessary for executing the command. That is, the CPU 10a accesses the mask ROM 10f with an address instructed by the system control logic 10g, fetches an instruction, decodes the fetched instruction, and performs operand fetch and data operation based on the decoding result. The coprocessor unit 10e performs a remainder calculation process in RSA or elliptic curve cryptographic calculation according to the control of the CPU 10a.

  The I / O port 10h has a 1-bit input / output terminal I / O, and is used both for data input / output and external interrupt signal input. The I / O port 10h is coupled to a data bus 10i, and the CPU 10a, RAM 10b, timer 10c, EEPROM 10d, coprocessor unit 10e, and the like are electrically connected to the data bus 10i.

  The system control logic 10g controls the operation mode and interrupt of the IC card microcomputer circuit 10, and further includes a random number generation logic used for generating an encryption key. When a reset operation is instructed by the reset signal / RES, the IC card microcomputer circuit 10 is initialized, and the CPU 10a starts executing an instruction from the top address of the program in the EEPROM 10d. The IC card microcomputer circuit 10 operates in synchronization with the clock signal CLK.

  The EEPROM 10d is electrically erasable and writable, and is used as an area for storing data such as ID (Identification) information and an authentication certificate used to identify an individual. A flash memory or a ferroelectric memory may be used instead of the EEPROM 10d. The IC card microcomputer circuit 10 supports a contact interface using an external terminal for an interface with the outside.

  On the other hand, the SFM 4 has, for example, an interface controller circuit. The interface controller circuit has a function of controlling the external interface operation and the memory interface operation in accordance with a control mode according to an instruction from the outside or a setting determined in advance inside. The interface control mode possessed by the SFM 4 is, for example, an MMC mode (Multi Media Card, a registered trademark of Infine on Technologies AG, including RS-MMC (Reduced Size MMC)). The function of the interface controller circuit is to recognize the memory card interface control mode according to the command and bus state exchanged with the outside via the external connection terminal CB, change the bus width according to the recognized memory card interface control mode, and the recognized memory Data format conversion according to card interface control mode, power-on reset function, interface control with IC card microcomputer circuit 10 in IC chip 3, interface control with memory circuit in semiconductor chip in SFM, power supply voltage conversion, etc. It is said.

  FIG. 16 shows an example of the interface controller circuit 11. Note that a memory circuit M in FIG. 16 is a memory circuit formed on a semiconductor chip in the SFM 4.

  The interface controller circuit 11 includes a host interface circuit 11a, a microcomputer 11b, a flash controller 11c, a buffer controller 11d, a buffer memory 11e, and an IC card interface circuit 11f. The buffer memory 11e is composed of DRAM (Dynamic RAM) or SRAM (Static RAM). The IC card microcomputer circuit 10 is electrically connected to the IC card interface circuit 11f. The microcomputer 11b has a CPU (central processing unit) 11b1, a program memory (PGM) 11b2 that holds an operation program of the CPU 11b1, a work memory (WRAM) 11b3 used for a work area of the CPU 11b1, and the like. A control program of the SD (Secure Digital) card (there is a standard standardized by the SD card association), MMC (including RS-MMC), and HSMMC (High Speed Multi Media Card) interface control mode is stored in the program memory 11b2. Has been.

  When the host interface circuit 11a detects the issuance of a memory card initialize command or the like, the host interface circuit 11a enables an interface control mode control program corresponding to the microcomputer 11b by an interrupt. The microcomputer 11b controls the external interface operation by the host interface circuit 11a by executing the control program, controls the access (write, erase and read operations) and data management to the memory circuit M by the flash controller 11c, and the buffer controller. It controls the format conversion between the data format specific to the memory card according to 11d and the common data format for the memory. The buffer memory 11e temporarily holds data read from the memory circuit M or data written to the memory circuit M. The flash controller 11c operates the memory circuit M as a hard disk compatible file memory and manages data in units of sectors. The flash controller 11c includes an ECC circuit (not shown), adds an ECC code when data is stored in the memory circuit M, and performs selection error detection / correction processing on the read data using the ECC code.

  Next, an example of a method for manufacturing a single card chip 1c that does not have the frame 1a will be described with reference to FIGS. 17 to 21 are enlarged plan views of main parts on the first main surface side of the tape 15 for forming the wiring board during the manufacturing process of the card chip 1c.

  The tape 15 shown in FIG. 17 is formed by using, for example, a flexible flat band-shaped thin insulating material 15a formed of polyimide resin or the like as a base, and is a first main body that is opposite to each other along the thickness direction. A surface and a second main surface. A plurality of card chip 1c forming regions (broken lines) are arranged on the tape 15 along the extending direction. In the first main surface of the tape 15, the wirings L <b> 1 and L <b> 2 are arranged in the formation region of each card chip 1 c. External connection terminals CA and CB as shown in FIG. 4 are arranged in the formation region of each card chip 1 c on the second main surface of the tape 15. A plurality of tape feed holes 15 b are regularly arranged in the vicinity of both long sides of the tape 15 along the extending direction of the tape 15.

  First, as shown in FIG. 18, the adhesive 5 is applied on the first main surface of the tape 15, and then the SFM 4 is applied on the first main surface of the tape 15 via the adhesive 5 as shown in FIG. 19. Glue. Further, the IC chip 3 is bonded on the first main surface of the tape 15. The adhesive 5 may be the one used for bonding the IC chip 3. Subsequently, as shown in FIG. 20, the pad of the IC chip 3 and the electrode on the tape 15 are connected by the wire W1, and the external terminal 4a of the SFM 4 and the electrode on the tape 15 are connected by the wire W2. After that, as shown in FIG. 21, a part of the IC chip 3 and the SFM 4 is sealed with the resin sealing body 6 by applying a potting resin on the first main surface of the tape 15. Thereafter, each card chip 1c portion is cut out from the tape 15, and the cap 7 is put on to manufacture the card chip 1c. As described above, in the first embodiment, since the SFM 4 prepared in advance only needs to be mounted on the tape 15, the card having both functions of the IC card and the memory card and a highly reliable card. The chip 1c can be provided efficiently. Each process is performed at each stage while feeding the tape 15.

  Next, an example of the configuration of the SFM 4 will be described.

  FIG. 22 is an overall perspective view of the SFM 4, FIG. 23 is a plan view of the SFM 4 in FIG. 22 as viewed from above, and FIG. 24 is a plan view of the SFM 4 in FIG.

  The SFM 4 is a module configured by combining the memory card functions into one. In this state, electrical characteristics and function tests as a memory card have been completed. The external dimensions of the SFM 4 are, for example, about 10 mm × 14 mm × 0.50 (MAX) mm. One end of the SFM 4 in the longitudinal direction is not stepped on the upper surface side of the SFM 4, and a plurality of (for example, seven) external terminals 4 a are exposed to the outside along the width direction of the SFM 4. Are arranged side by side.

  Of the external terminals 4a, the external terminal 4a1 is a reserve terminal that can be used in the future, the external terminal 4a2 is a command (CMD) terminal, the external terminal 4a3 is a terminal for supplying a circuit voltage (Vss1) on the first low potential side, an external terminal The terminal 4a4 is a high potential side circuit voltage (Vdd) supply terminal. The external terminal 4a5 is a clock signal terminal, the external terminal 4a6 is a second low potential side circuit voltage (Vss2) supply terminal, and the external terminal 4a7 is a data input / output signal I / O terminal.

  On the other hand, on the back surface side of the SFM 4, a plurality of test terminals 4 b (here, seven in accordance with the external terminals 4 a) are exposed in the width direction of the SFM 4 at positions corresponding to the back side of the external terminals 4 a. They are arranged side by side.

  Next, FIG. 25 is an overall plan view of the inside of the SFM 4 as seen through the top surface side, and FIG. 26 is a sectional view taken along line X2-X2 of FIG.

  The SFM 4 encloses the wiring substrate 4c, the semiconductor chip (first semiconductor chip) 4d mounted thereon, the semiconductor chip (second semiconductor chip) 4e stacked thereon, and the semiconductor chips 4d and 4e. And a resin sealing body 4f to be stopped.

  The wiring board 4c of the SFM 4 is composed of, for example, a printed wiring board having a multilayer (two-layer) wiring configuration, and has a first main surface and a second main surface that are opposite to each other along the thickness direction. Yes. The insulating base 4c1 of the wiring board 4c is formed of, for example, a glass epoxy resin. The material of the insulating base material 4c1 is not limited to this, and can be variously changed. For example, a BT resin or an aramid nonwoven material may be used.

  The external terminal 4a, the wiring L3, and the relay wiring L4 are disposed on the first main surface of the insulating base 4c1 of the wiring board 4c. Further, the test terminal 4b and the wiring L5 are arranged on the second main surface of the insulating base 4c1 of the wiring board 4c. The external terminals 4a, the test terminals 4b, the wirings L3 and L5, and the relay wiring L4 are made of, for example, copper (Cu), and a part of the surface thereof is subjected to, for example, nickel (Ni) base plating and gold (Au) plating. ing. The external terminal 4a and the wiring L3 are integrally patterned. A part of the wiring L3 is disposed in the resin sealing body 4f (here, a portion of the wiring L3 outside the resin sealing body 4f is used as an external terminal 4a). The relay wiring L4 is an isolated pattern and is entirely enclosed in the resin sealing body 4f. The test terminal 4b and the wiring L5 are integrally patterned.

  The relatively large semiconductor chip 4d has a semiconductor substrate made of, for example, silicon (Si) single crystal, and the main surface thereof has, for example, a flash memory that can electrically erase and write data. Such a non-volatile memory circuit M (see FIG. 16) is formed. The storage capacity of the semiconductor chip 4d is the largest compared to the memory portion of the other semiconductor chip 4e. The pad P1 on the main surface of the semiconductor chip 4d is electrically connected to the external terminal 4a and the relay wiring L4 through a wire W3 formed of, for example, gold (Au). In the plurality of memory cells constituting the memory circuit M of the semiconductor chip 4d, the threshold voltage rises when electrons are injected into the floating gate of the memory cell, for example, and when the electrons are extracted from the floating gate or the like, the threshold voltage is increased. Has come to decline. The memory cell stores information corresponding to the level of the threshold voltage with respect to the word line voltage for reading data. Although not particularly limited, for example, a state in which the threshold voltage of the memory cell transistor is low is defined as an erased state, and a state in which the threshold voltage is high is defined as a written state.

  The relatively small semiconductor chip 4e on the semiconductor chip 4d has a semiconductor substrate made of, for example, silicon (Si) single crystal, and the interface controller circuit 11 is formed on the main surface thereof. Yes. The operation of the memory circuit M of the semiconductor chip 4d is controlled by the interface controller circuit 11 of the semiconductor chip 4e. The pad P2 on the main surface of the semiconductor chip 4e is electrically connected to the external terminal 4a and the relay wiring L4 through a wire W4 formed of, for example, gold (Au).

  A part of the wiring L3, the whole relay wiring L4, the semiconductor chips 4d and 4e, and the wires W3 and W4 are sealed with a resin sealing body 4f. The resin sealing body 4f is made of, for example, an epoxy resin.

  27 is an enlarged plan view of the main part of the SFM 4 in FIG. 25, FIG. 28 is a sectional view taken along the broken line X3-X3 in FIG. 27, and FIG. 29 is a plan view of the external terminal 4a of the SFM 4 in FIG. .

  On the first main surface and the second main surface of the insulating base 4c1 of the wiring board 4c, a solder resist SR2 is formed so as to cover a part of the wirings L3, L5 and the relay wiring L4. An opening is formed in a part of the solder resist SR2 to expose a part of the wirings L3 and L5 and the relay wiring L4. A portion of the wiring L3 exposed from the opening of the solder resist SR2 is a connection region E1 of the external terminal 4a outside the resin sealing body 4f, and a connection region E2 inside the resin sealing body 4f. Yes. The pad P1 of the semiconductor chip 4d is electrically connected to the connection region E2 of the wiring L3 or the connection region of the relay wiring L4 through the wire W3. The pad P2 of the semiconductor chip 4e is electrically connected to the connection region E2 of the wiring L3 or the connection region of the relay wiring L4 through the wire W4. The materials of the wires W3 and W4 are the same as those of the wire W1. Further, a portion exposed from the opening of the solder resist SR2 in the wiring L5 is a connection region E3 of the test terminal 4b.

  The external terminal 4a and the test terminal 4b are electrically connected to the test terminal 4b and the wiring L5 through a conductor portion (for example, copper) in the through hole TH2 penetrating between the first main surface and the second main surface of the wiring board 4c. Connected. The reason why the test terminal 4b is provided on the second main surface of the wiring board 4c as described above is, for example, as follows. That is, from the viewpoint of downsizing the SFM 4, the width of the external terminal 4 a (the length in the second direction Y) should be kept to a minimum size necessary for the connection of the wire W 2. However, there is a problem that the width of the external terminal 4a necessary for the connection of the wire W2 is too small to apply a test probe and is difficult to test. Therefore, in the first embodiment, the external terminal 4a on the first main surface of the wiring board 4c is drawn out to the test terminal 4b on the second main surface of the wiring board 4c through the through hole TH2. Since the back surface side of the wiring board 4c can secure the dimension of the test terminal 4b having a size necessary for applying a test probe, the test can be easily performed. Of course, the test terminal 4b can also be used as a normal external terminal.

  The desired external terminal 4a among the plurality of external terminals 4a is bent and extends in the second direction Y in which the plurality of external terminals 4a are arranged, for example, formed in a planar L shape. Has been. That is, the external terminal 4a is patterned so as to have two regions having different widths, a region having a relatively narrow width (length in the second direction Y) and a region having a relatively wide width. The through hole TH2 is disposed on the distal end side in the second direction Y of the external terminal 4a. The reason for such a configuration is as follows, for example.

  That is, as described above, in order to electrically connect the external terminal 4a on the first main surface of the wiring board 4c to the test terminal 4b on the second main surface of the wiring board 4c, it is necessary to arrange the through hole TH2. . However, if the through hole TH2 is disposed in the connection region E1 of the wire W2, a connection failure of the wire W2 may occur. Therefore, it is necessary to separate the connection area E1 of the wire W2 and the arrangement area of the through hole TH2. Here, as shown in the lower part of FIG. 29, the length of the external terminal 4a can be extended in the first direction X, and the through hole TH2 can be arranged in the extending region. However, if this is done, the length XA of the external terminal 4a in the first direction X becomes longer, and the dimension in the first direction X of the SFM 4 that is strict in terms of dimensions must also be increased. Therefore, in the first embodiment, the tip of the external terminal 4a is extended in the second direction Y in which the plurality of external terminals 4a are arranged side by side, and the through hole TH2 is arranged in the extending region. ing. Since the second direction Y of the SFM 4 has a dimensional margin, the dimension of the second direction Y of the SFM 4 must be increased just because the tip of the external terminal 4a extends in the second direction Y direction. There is no need to be. That is, the through hole TH2 can be arranged without increasing the dimension of the SFM 4. In the plurality of external terminals 4a, it is also preferable to alternately arrange one having a region extending in the second direction Y and one having no region.

  In addition, in the case where the plane of the plurality of external terminals 4a is formed in a rectangular shape, the end portion of the wiring L3 covered with the resin sealing body 4f is the second in the same manner as the desired external terminal 4a. It extends in the direction Y. The wiring L3 is electrically connected to the test terminal 4b on the second main surface of the wiring board 4c through a through hole TH2 arranged in a region extending in the second direction Y. The reason why the connection region E2 in which the wires W3 and W4 are in contact with the connection region in which the through-hole TH2 is disposed is separated in order to prevent a connection failure between the wires W3 and W4. The reason why the leading end portion of the wiring L3 is bent in the second direction Y is to arrange the through hole TH2 without increasing the dimension of the SFM 4 as described above.

  Next, an example of wire connection between the semiconductor chips 4d and 4e and the wiring board 4c will be described with reference to FIGS.

  First, FIG. 30 shows a perspective view of an example of wire connection between the semiconductor chips 4d and 4e using the relay wiring L4. When the semiconductor chips 4d and 4e are electrically connected, the pad P1 of the semiconductor chip 4d and the pad P2 of the semiconductor chip 4e may be directly connected by a wire. However, as described above, since the second bonding of the wire has a large impact on the base, damage may occur under the pads of the semiconductor chip on which the second bonding is performed. Therefore, in the first embodiment, the first bonding of the wires W3 and W4 is performed by the pads P1 and P2 of the semiconductor chips 4d and 4e, and the second bonding of the wires W3 and W4 is performed on the wiring substrate 4c which is resistant to damage. Perform at L4. As a result, wire connection can be performed without causing damage to the semiconductor chips 4d and 4e, so that the yield and reliability of the SFM 4 can be improved.

  In this case, if the second bonding portions of the wires W3 and W4 are arranged side by side in the first direction X, the length of the relay wiring L4 in the first direction X is also increased. You have to make it longer. Therefore, in the first embodiment, the second bonding portions of the wires W3 and W4 are arranged side by side in the second direction Y. As a result, the length of the relay wiring L4 in the first direction X can be kept short, so that the relay wiring L4 can be arranged without increasing the dimension of the SFM 4 in the first direction X.

  Next, FIGS. 31 and 32 show a perspective view and a side view of a wire connection example between the semiconductor chips 4d and 4e and the wiring board 4c. Here, in order to lower the loop of the wire W4 connecting the upper semiconductor chip 4e and the wiring substrate 4c, the second bonding of the wire W4 is intentionally performed by the pad P2 of the semiconductor chip 4e, and the first bonding of the wire W4 is performed. Is performed by the wiring L3 or the relay wiring L4 of the wiring board 4c. In this case, since the height h1 from the first main surface of the wiring board 4c to the highest position of the wire W4 can be kept low, the resin sealing body 4f can be thinned, and the thinning of the SFM 4 can be promoted. . As a result, the ceiling portion of the cap 7 can be thickened, and cracking of the cap 7 can be suppressed or prevented.

  However, in this case, as described above, the portion below the pad P2 of the semiconductor chip 4e may be damaged by the second bonding of the wire W4. As a countermeasure, it is preferable to adopt the following configuration. For example, before connecting the wire W4, a metal bump made of, for example, gold (Au) or the like is formed as a buffer member on the pad P2 of the semiconductor chip 4e. Further, as shown in FIG. 33, the pad P1 has a laminated structure of the uppermost layer wiring 18a and the lower layer wiring 18b. The wirings 18a and 18b are made of, for example, aluminum. By laminating the wirings 18a and 18b, the impact caused by the second bonding of the wire W4 can be mitigated, and the occurrence of damage under the pad P2 can be suppressed or prevented. As another countermeasure, as shown in FIG. 34, the active region 19 where the integrated circuit element is formed may be arranged away from the damaged region 20 under the pad P2.

  Note that the connection of the lower semiconductor chip 4d and the wiring board 4c by the wire W3 is the same as described in FIG. That is, the first bonding of the wire W3 is performed by the pad P1 of the semiconductor chip 4d, and the second bonding of the wire W3 is performed by the relay wiring L4 or the external terminal 4a on the wiring substrate 4c which is resistant to damage.

  Next, FIGS. 35 and 36 show a perspective view and a side view of a wire connection example between the semiconductor chips 4d and 4e. Here, for the same reason as described in FIGS. 31 and 32, when the semiconductor chips 4d and 4e are directly connected by the wire W5, the first bonding of the wire W5 is performed by the pad P1 of the lower semiconductor chip 4d. The second bonding of the wire W5 is performed on the pad P2 of the upper semiconductor chip 4e. In this case, since the height h1 from the first main surface of the wiring board 4c to the highest position of the wire W5 can be kept low, the resin sealing body 4f can be thinned and the SFM 4 can be made thinner. . However, also in this case, it is preferable to take the above-mentioned measures from the viewpoint of suppressing or preventing damage under the pad P2 due to the second bonding of the wire W5. The wire W5 is made of the same material as the wires W3 and W4. Further, the pads on the power supply (high potential side and low potential side) of the semiconductor chips 4d and 4e are electrically connected to the wiring substrate 4c through the wires W3 and W4. Thereby, wiring resistance can be reduced.

  Next, an example of the manufacturing method of SFM4 is demonstrated. Here, for example, a case where a MAP (Mold Array Package) method for collectively sealing a plurality of semiconductor chips mounted on a substrate will be described.

  First, as shown in FIG. 37, for example, a flat rectangular substrate substrate (hereinafter referred to as a substrate) 25 is prepared. FIG. 37 shows an overall plan view of the first main surface of the substrate matrix 25. The substrate mother body 25 is a mother body of the wiring substrate 4c.

  In the substrate matrix 25, for example, a total of six wiring substrate 4c formation regions are arranged in 2 rows × 3 columns. The external terminals 4a, the wirings L3, the relay wirings L4, and the like are patterned on the first main surface of the substrate base 25 where the wiring boards 4c are formed. In addition, the test terminals 4b and the wirings L5 are patterned on the second main surface of the substrate base 25 where the wiring boards 4c are formed. The cross-sectional configuration of the substrate matrix 25 is the same as that of the wiring substrate 4c.

  The formation regions of the respective wiring boards 4c of the substrate base body 25 are arranged such that the arrangement regions of the respective external terminals 4a and the like are positioned on the end side in the first direction X. That is, the back surfaces of the two wiring boards 4c arranged along the first direction X are arranged so as to contact each other.

  Subsequently, as shown in FIG. 38, after the semiconductor chips 4d and 4e are mounted on the formation region of each wiring substrate 4c of the substrate base 25, the wires W3, W4 and W5 are connected. FIG. 38 is an overall plan view of the first main surface of the substrate base body 25 after the wire connection process.

  Next, as shown in FIG. 39, the substrate matrix 25 is placed on the lower mold of the molding die. FIG. 39 shows a cross-sectional view of the substrate matrix 25 at the stage where it is placed on the molding die. An upper mold 27 is installed above a first main surface of the substrate matrix 25 via a laminate film (hereinafter referred to as a film) 26. The film 26 is formed of a flexible insulating film having high heat resistance such as a fluorine resin. A cavity 27a having a concave cross section having a planar dimension is formed on the surface of the upper mold 27 facing the substrate base 25 so as to cover the formation region of the plurality of wiring boards 4c. The planar size of the film 26 is formed so as to cover almost the entire inner wall surface of the cavity 27a of the upper mold 27 of the molding die.

  Subsequently, as shown in FIG. 40, after the film 26 is vacuum-sucked to the upper mold 27 side and brought into close contact with the cavity 27a of the upper mold 27, the substrate base 25 is sandwiched between the lower mold and the upper mold 27. Hold. In this way, a substantial cavity 28 surrounded by the cavity 27a of the upper mold 27 and the first main surface of the substrate base 25 is formed. At this time, the outer peripheral portion of the first main surface of the substrate base body 25 is pressed against the outer peripheral portion of the cavity 27a of the upper mold 27 through the film 26, and is in a state of being crushed by about several percent of the total thickness of the substrate base body 25. Is done. For this reason, as shown in FIG. 41, the arrangement area of the external terminals 4a and the like on the first main surface of the substrate base 25 is also an area that is finally exposed to the outside of the resin sealing body. Is pressed by. At this time, in the first embodiment, since the film 26 is interposed between the bottom surface of the outer peripheral portion of the upper mold 27 and the first main surface of the substrate base body 25, the upper mold 27 adds to the external terminals 4a and the like. The force can be relaxed by the film 26. Thereby, damage etc. of the external terminal 4a etc. can be prevented.

  Thereafter, a thermosetting sealing resin (mold resin) such as an epoxy resin is poured into the cavity 28. 42 and 43 show directions R1 and R2 in which the sealing resin is poured and directions V1 and V2 in which the air in the cavity 27a escapes to the outside. In FIG. 42, the sealing resin is poured along the direction intersecting the arrangement direction of the external terminals 4a. On the other hand, in FIG. 43, sealing resin is poured along the arrangement direction of the external terminals 4a. In this way, the semiconductor chips 4d and 4e and the wires W3, W4, W5 and the like in the formation region of the plurality of wiring boards 4c on the first main surface of the substrate base body 25 are collectively sealed.

  Then, after the sealing resin is cured, the vacuum suction to the film 25 is stopped, and the substrate mother body 25 on which the collective sealing body 30 is formed as shown in FIG. Separate from upper mold 27. Subsequently, as shown in FIG. 45, the upper surface of the collective sealing body 30 is polished by about 10 mm with a polishing grindstone or the like. On the upper surface of the collective sealing body 30, a component such as a release wax for improving the releasability from the upper mold 27 is absorbed and deteriorated, and therefore the adhesive 8 that bonds the cap 7 and the SFM 4 together. There is a problem that the adhesiveness of the resin deteriorates. This problem is particularly a problem when the collective sealing body 30 is molded without using the film 25. Therefore, the upper surface of the collective sealing body 30 is polished as described above to remove the deteriorated layer. Thereby, the adhesiveness of the resin sealing body 4f of SFM4 and the adhesive agent 8 can be improved.

  Thereafter, the substrate base 25 is turned over, and the collective sealing body 30 is fixed with an adhesive tape or the like, and then a dicing blade 31 is applied to the second main surface side of the substrate base 25 in the same manner as dicing as shown in FIG. Then, the substrate base body 25 and the collective sealing body 30 are cut for each wiring board 4c. In this way, a plurality of SFMs 4 are manufactured simultaneously.

(Embodiment 2)
In the second embodiment, an example in which the wiring board 2 of the card chip 1c has a one-layer wiring configuration will be described.

  47 is an overall plan view of the second main surface of the card chip 1c of the second embodiment, FIG. 48 is an overall plan view of the inside of the card chip 1c of FIG. 47 as seen through the first main surface side, and FIG. Shows cross-sectional views taken along line X4-X4 of FIG.

  In the second embodiment, the wiring board 2 of the card chip 1c has a one-layer wiring configuration. The plurality of external connection terminals CB on the second main surface of the wiring board 2 extend toward the center of the wiring board 2, and a wide pattern CBw is formed at the end thereof. The first main surface of the wiring board 2 is formed with a through hole TH3 in which a back surface of the external connection terminal CA and a part of the back surface of the wide pattern CBw of the external connection terminal CB are exposed. The wire W1 connected to the pad of the IC chip 3 is electrically connected to the external connection terminal CA by directly contacting the end of the wire W1 through the through hole TH3. Further, the wire W2 connected to the external terminal 4a of the SFM 4 is also electrically connected to the external connection terminal CB by directly contacting the wide pattern CBw of the external connection terminal CB through the through hole TH3. Yes. Other configurations are the same as those in the first embodiment.

  In the second embodiment, the wiring board 2 of the card chip 1c has a single-layer wiring configuration, so that the height from the first main surface of the wiring board 2 to the upper surface of the resin sealing body 6 can be kept low. Therefore, the ceiling part of the cap 7 can be made thicker by that amount, and cracking of the cap 7 can be suppressed or prevented. Moreover, the cost of the card chip 1c can be reduced because the wiring board 2 has a single-layer wiring configuration.

(Embodiment 3)
In the third embodiment, another example in which the wiring board 2 of the card chip 1c has a one-layer wiring configuration will be described.

  50 is an overall plan view of the second main surface of the card chip 1c of the third embodiment, and FIG. 51 is a sectional view taken along line X5-X5 of FIG.

  In the third embodiment, the second main surface of the wiring board 2 of the card chip 1c is covered with the solder resist SR3. An opening 35 is formed in a part of the solder resist SR3 so as to expose all the external connection terminals CA and a part of all the external connection terminals CB.

  Since the external connection terminal CB is thin and has a small adhesion area with respect to the wiring board 2, its adhesion strength is lower than that of the two-layer wiring configuration, and the external connection terminal CB may be peeled off. Therefore, in the third embodiment, both end portions in the longitudinal direction of each external connection terminal CB are covered with the solder resist SR3. Thereby, peeling of the external connection terminal CB of the card chip 1c can be suppressed or prevented. For this reason, it is possible to reduce the occurrence rate of short-circuit defects due to peeling of the external connection terminals CB.

(Embodiment 4)
In the fourth embodiment, another example in which the wiring board 2 of the card chip 1c has a one-layer wiring configuration will be described.

  FIG. 52 is an overall plan view of the interior of the card chip 1c according to the fourth embodiment viewed through the first main surface side, and FIG. 53 is a cross-sectional view taken along line X6-X6 of FIG.

  In the fourth embodiment, openings 37 a and 37 b are formed in the first main surface of the wiring board 2. A part of the back surface of the external connection terminal CA on the second main surface of the wiring board 2 is exposed from the bottom surface of the one opening 37a. The IC chip 3 is accommodated in the opening 37a in a state of being mounted on the external connection terminal CA via the adhesive layer 5a.

  From the bottom surface of the other opening 37b, the back surface of the conductor pattern 38 on the second main surface of the wiring board 2 is exposed. The conductor pattern 38 is formed in the same layer as the external connection terminals CA and CB, and is formed of the same metal material as the external connection terminals CA and CB. The SFM 4 is accommodated in the opening 37b while being mounted on the conductor pattern 38 via the adhesive layer 5b. The SFM 4 is arranged so that the arrangement portion of the plurality of external terminals 4 a faces the end portion on the corner portion side of the wiring board 2 that is largely chamfered.

  Here, FIG. 54 and FIG. 55 are explanatory views of the thickness of the card chip 1c. FIG. 54 shows a case where the SFM 4 is mounted on the first main surface of the wiring board 2, and FIG. 55 shows a case where the SFM 4 is mounted on the wiring layer as in the fourth embodiment. The thickness D1 of the card chip 1c is, for example, 0.76 mm, the thickness D2 of the wiring board 2 is, for example, 0.15 mm, and the thickness of the SFM 4 is, for example, about 0.45 mm. Therefore, in the case of FIG. 54, the height D3 from the back surface of the external connection terminal CB to the upper surface of the SFM 4 is, for example, about 0.6 mm, and the distance D4 from the upper surface of the SFM 4 to the ceiling surface in the cap 7 is, for example, 0. If the thickness is 01 mm, the thickness D5 of the ceiling portion of the cap 7 can be ensured, for example, only about 0.15 mm.

  On the other hand, in the case of the fourth embodiment shown in FIG. 55, the height D6 from the back surface of the external connection terminal CB to the upper surface of the SFM 4 can be reduced to, for example, about 0.55 mm. For this reason, when the distance D4 to the ceiling surface in the cap 7 is, for example, 0.01 mm, the thickness D7 of the ceiling portion of the cap 7 can be set to, for example, about 0.2 mm, which is more than the case of FIG. Can be thicker.

  As described above, in the fourth embodiment, since the IC chip 3 and the SFM 4 are mounted on the first conductor layer of the wiring board 2, the resin sealing body 6 and the SFM 4 are formed from the first main surface of the wiring board 2. Since the height to the upper surface can be further reduced, the ceiling portion of the cap 7 can be made thicker accordingly, and cracking of the cap 7 can be suppressed or prevented.

(Embodiment 5)
In the fifth embodiment, another example in which the wiring board 4c of the SFM 4 has a one-layer wiring configuration will be described.

  56 is an overall perspective view of the SFM 4 of the fifth embodiment, FIG. 57 is a plan view of the SFM 4 of FIG. 56 viewed from the top, and FIG. 58 is a plan view of the SFM 4 of FIG.

  In the fifth embodiment, the wiring board 4c of the SFM 4 has a one-layer wiring configuration. Also in the case of the fifth embodiment, one end portion in the longitudinal direction of the SFM 4 is not stepped on the upper surface side of the SFM 4, and a plurality of (for example, seven in this case) external terminals 4 a are exposed to the outside. In the state, they are arranged side by side along the width direction of the SFM 4. On the other hand, on the back surface of the SFM 4, a plurality of test terminals 4 b (here, seven in accordance with the external terminals 4 a) are arranged in a staggered manner along the width direction of the SFM 4 with the test terminals 4 b exposed to the outside. .

  Next, FIG. 59 is an overall plan view of the inside of the SFM 4 as seen through the top surface, and FIG. 60 is a view of the inside of the SFM 4 as seen from the top with the semiconductor chips 4d and 4e in FIG. 59 removed. 61 is an overall plan view, FIG. 61 is an enlarged plan view of a main part of the SFM 4 in FIG. 59, and FIG. 62 is a sectional view taken along the broken line X7-X7 in FIG.

  The wiring board 4c of the SFM 4 of the fifth embodiment is formed by a printed wiring board having a one-layer wiring configuration, for example. The external terminal 4a on the first main surface of the wiring board 4c is formed in a planar rectangular shape. Each external terminal 4a extends toward the center of the wiring board 4c through the wiring L3, and a wide pattern L3w is integrally formed at the end thereof. The surfaces of the wiring L3 and the wide pattern L3w are covered with the solder resist SR2 except for the connection region E2. Thereby, the semiconductor chip 4d and the wiring L3 or the wide pattern L3w are prevented from being short-circuited. On the other hand, a plurality of openings 40 are arranged in a staggered pattern on the second main surface of the wiring board 2. From each opening 40, a part of the back surface of the wide pattern L3w on the first main surface of the wiring board 2 is exposed. The exposed portion of the wide pattern L3w is a test terminal 4b. Since other than this is the same as the first to fourth embodiments, the description thereof is omitted.

  In the fifth embodiment, the thickness of the SFM 4 can be reduced by adopting a single-layer wiring configuration for the wiring board 4c of the SFM 4. For this reason, the ceiling part of the cap 7 can be made thicker as described above, and cracking of the cap 7 can be suppressed or prevented. Moreover, the cost of the SFM 4 can be reduced by adopting a single-layer wiring configuration for the wiring board 4c.

(Embodiment 6)
In the sixth embodiment, an example in which the arrangement of the IC chip 3 and the SFM 4 is reversed will be described.

  63 is an overall plan view of the inside of the card chip 1c of the sixth embodiment viewed through the first main surface side, and FIG. 64 is an IC chip on the first main surface of the wiring board 2 of the card chip 1c of FIG. 3 is an overall plan view showing a route of wiring for No. 3.

  In the card chip 1c according to the sixth embodiment, the SFM 4 is arranged on the first main surface of the wiring board 2 directly behind the external connection terminal CA for the IC chip 3, and the SFM 4 is used on the first main surface of the wiring board 2. The IC chip 3 is disposed on the external connection terminal CB side.

  As the wiring board 2, for example, the wiring board having the two-layer wiring structure described in the first embodiment is used. On the first main surface of the wiring board 2, the wiring L1 connected to the external connection terminal CA for the IC chip 3 is drawn out to the IC chip 3 side through the wiring L1a, and is electrically connected to the terminal electrode L1b of the wiring L1a. It is connected. The pad of the IC chip 3 is electrically connected to the electrode L1a through the wire W1. The wirings L1 and L1a and the electrode L1a are made of copper, for example, and are integrally patterned on the first main surface of the wiring board 2. On the other hand, the external terminal 4a of the SFM 4 is electrically connected to the wiring L2 on the first main surface of the wiring board 2 through the wire W2. The wiring L2 is electrically connected to the external connection terminal CB on the second main surface of the wiring board 2 through the conductor portion in the through hole TH1.

  In the sixth embodiment as described above, the following effects can be obtained. That is, in the card chip 1c, the arrangement area side of the external connection terminal CB for the SFM4 is formed with a large chamfered portion for index at the corner, so the arrangement area side of the external connection terminal CA for the IC chip 3 is formed. Is smaller than the area. For this reason, when the area of the SFM 4 is increased, it may be difficult to dispose the SFM 4 on the arrangement region side of the external connection terminal CB for the SFM 4. Therefore, in the sixth embodiment, the SFM 4 is arranged on the first main surface of the wiring board 2 on the arrangement region side of the external connection terminal CA for the IC chip 3. Since the arrangement area side of the external connection terminal CA for the IC chip 3 can secure a larger area than the arrangement area side of the external connection terminal CB for the SFM 4, the area of the SFM 4 can be increased.

(Embodiment 7)
In the seventh embodiment, another example in which the arrangement of the IC chip 3 and the SFM 4 is reversed will be described.

  FIG. 65 is an overall plan view of the inside of the card chip 1c of the seventh embodiment viewed through the first main surface side, and FIG. 66 is a simplified overall plan view of the SFM 4 of FIG.

  In the card chip 1c of the seventh embodiment, the SFM 4 is arranged on the first main surface of the wiring board 2 directly behind the external connection terminal CA for the IC chip 3 in the same manner as in the sixth embodiment. On the first main surface, the IC chip 3 is arranged on the external connection terminal CB side for SFM4. The difference from the sixth embodiment is that the IC chip 3 and the external connection terminal CA on the second main surface of the card chip 1c are electrically connected to the wiring board 4c of the SFM 4 of the seventh embodiment. That is, wiring paths for power supply and / or signal are formed.

  That is, the pad of the IC chip 3 is electrically connected to the external terminal 4ai of the SFM 4 through the wire W1. The configuration of the external terminal 4ai is the same as that of the external terminal 4a, but the external terminal 4ai is external to the second main surface of the wiring board 4c through the wiring L3i formed on the first main surface of the wiring board 4c of the SFM4. It is electrically connected to the terminal 4gi. The configuration of the external terminal 4gi is the same as that of the test terminal 4b. The external terminal 4gi is electrically connected to the wiring L1 on the first main surface of the wiring board 2 of the card chip 1c, and further outside the second main surface of the wiring board 2 through the conductor portion in the through hole TH1. It is electrically connected to the connection terminal CA. Note that the test terminal 4b may not be connected to the external terminal 4ai.

  A wiring path (external terminals 4ai and 4gi and wiring L3i) connected to all the external connection terminals CA for the IC chip 3 may be formed in the SFM 4 or connected to some external connection terminals CA. A wiring path may be formed. When providing wiring paths for some external connection terminals CA on the wiring board 4c of the SFM 4, the wiring paths for other external connection terminals CA are the wiring of the card chip 1c as described in the sixth embodiment. It may be provided on the substrate 2. The configuration other than the above is the same as that described in the first to fifth embodiments.

  In this seventh embodiment, as in the sixth embodiment, it is possible to cope with an increase in the area of the SFM 4. Further, compared to the sixth embodiment, the wiring length from the IC chip 3 to the external connection terminal CA can be shortened (the length of the wiring L3i can be shortened and the length of the wire W1 can be shortened). The parasitic capacitance can be reduced, and the operation performance and reliability of the IC chip 3 can be ensured. In addition, the wiring route for the IC chip 3 can be easily routed compared to the sixth embodiment.

(Embodiment 8)
In the eighth embodiment, another example of the SFM 4 will be described.

  67 is an overall perspective view of the SFM 4 of the eighth embodiment, FIG. 68 is a plan view of the back surface of the SFM 4 when the wiring board 4c of the SFM 4 has a two-layer wiring configuration, and FIG. 69 is a one-layer wiring of the wiring board 4c of the SFM 4. The top view of the back surface of SFM4 in the case of a structure is shown, respectively.

  In the eighth embodiment, no external terminals are arranged on the upper surface of the SFM 4, and a plurality of external terminals 4 a are exposed on one end side of the back surface (second main surface of the wiring board 4 c) of the SFM 4. Has been. In FIG. 68, the plurality of external terminals 4a are arranged in a straight line along one edge of the back surface of the SFM 4. In FIG. 69, a plurality of external terminals 4a are arranged in a staggered manner along one edge of the back surface of the SFM 4.

  Next, FIG. 70 is an overall plan view of the inside of the SFM 4 according to the eighth embodiment viewed through the top surface side when the wiring board 4c has a two-layer wiring configuration, and FIG. 71 is an enlarged plan view of the main part of the SFM 4 in FIG. 72 and 72 show cross-sectional views taken along the broken line X8-X8 in FIG.

  The configuration of the SFM 4 in this case is almost the same as that described in FIGS. 22 to 28 of the first embodiment. The difference is that the wiring L3 portion corresponding to the external terminal 4a in the first embodiment is covered with the resin sealing body 4f, and the portion used as the test terminal 4b in the first embodiment is the eighth embodiment. Then, it is the external terminal 4a for testing and normal circuit operation.

  Next, FIG. 73 is an overall plan view of the inside of the SFM 4 according to the eighth embodiment when the wiring board 4c has a single-layer wiring configuration as seen through the top surface side, and FIG. FIG. 75 and FIG. 75 respectively show sectional views taken along the broken line X9-X9 in FIG.

  The configuration of the SFM 4 in this case is almost the same as that described in FIGS. 56 to 62 of the fifth embodiment. The difference is that the portion of the wiring L3 and the wide pattern L3w corresponding to the external terminal 4a in the fifth embodiment is covered with the resin sealing body 4f, and the portion used as the test terminal 4b in the fifth embodiment is In the eighth embodiment, the external terminal 4a is used for testing and normal circuit operation. Further, the external terminal 4a is arranged close to one end side in the first direction X on the back surface of the SFM 4.

  Next, a mounting example of the SFM 4 according to the eighth embodiment will be described. 76 is an overall plan view of the inside of the card chip 1c having the SFM 4 as seen through the first main surface side, and FIG. 77 is a sectional view taken along line X10-X10 in FIG.

  The wiring board 2 of the card chip 1c is a wiring board having a two-layer wiring structure similar to that described in the first embodiment with reference to FIGS. The arrangement of the IC chip 3 and the SFM 4 is the same as that described in the first embodiment.

  The SFM 4 of the eighth embodiment is mounted on the first main surface of the wiring board 2 with its back surface (second main surface of the wiring board 4c) facing the first main surface of the wiring board 2. The external terminal 4a on the back surface of the SFM 4 is electrically connected to the electrode of the wiring L2 of the wiring board 2 through the conductor portion 45. The conductor 45 is made of, for example, silver (Ag) paste, lead (Pb) ball, or the like.

  Next, FIGS. 78 to 80 are cross-sectional views of examples of mounting states of the SFM 4. FIG. 78 shows an example in which the SFM 4 is fixed to the wiring board 2 with the adhesive 46. The adhesive 46 is formed on the back surface of the SFM 4 and the first surface of the wiring board 2 on the side of the back surface of the SFM 4 (the second main surface of the wiring board 4c) opposite to the end where the external terminals 4a are disposed. It is interposed between the main surface.

  FIG. 79 shows an example in which the SFM 4 is fixed by a resin sealing body 6 that seals the IC chip 3. The resin sealing body 6 is coated on the lower part of the outer peripheral side surface of the SFM 4 and is filled between the opposing surfaces of the back surface of the SFM 4 and the first main surface of the wiring board 2. Thereby, the fixed strength of SFM4 can be improved.

  FIG. 80 shows an example in which the SFM 4 is fixed to the wiring board 2 by the conductor portion 47. In this case, a fixing conductor pattern 48 is formed on the back surface of the SFM 4. The conductor pattern 48 is made of, for example, copper (Cu), and is patterned at the same time when the wiring is formed on the second main surface of the wiring board 4c. However, the conductor pattern 48 is electrically separated from the circuit of the SFM 4. On the other hand, a fixing conductor pattern 49 is formed on the first main surface of the wiring board 2 at a position where the conductor pattern 48 faces. The conductor pattern 49 is made of, for example, copper (Cu), and is patterned at the same time when the wiring is formed on the first main surface of the wiring board 2. However, this conductor pattern 49 is also electrically separated from the circuit. The conductor portion 47 is interposed between the conductor patterns 48 and 49. The conductor portion 47 is formed at the same time as the conductor portion 45, and is formed of, for example, a silver (Ag) paste or a lead (Pb) ball. In this way, by bonding the SFM 4 and the wiring board 2 by the conductor portion 47, the fixing strength of the SFM 4 can be further improved.

  Also in the eighth embodiment, the card chip 1c having high function and reliability can be efficiently provided.

(Embodiment 9)
In the ninth embodiment, an example in which the wiring board 2 of the card chip 1c on which the SFM 4 of the eighth embodiment is mounted has a one-layer wiring configuration will be described.

  81 is an overall plan view of the inside of the card chip 1c of the ninth embodiment viewed through the first main surface side, and FIG. 82 is a sectional view taken along line X11-X11 in FIG.

  The wiring board 2 of the card chip 1c is a wiring board having a single-layer wiring structure similar to that described in FIGS. 47 to 49 of the second embodiment. The arrangement of the IC chip 3 and the SFM 4 is the same as that described in the second embodiment.

  The SFM 4 of the ninth embodiment is mounted on the first main surface of the wiring board 2 with its back surface (second main surface of the wiring board 4c) facing the first main surface of the wiring board 2. The external terminal 4a on the back surface of the SFM 4 is electrically connected to the wide pattern CBw and the external connection terminal CB of the wiring board 2 through the conductor portion 45 in the through hole TH3 of the wiring board 2. The conductor 45 is made of, for example, silver (Ag) paste, lead (Pb) ball, or the like. In the ninth embodiment, the same effect as in the second embodiment can be obtained.

  83 shows a cross-sectional view taken along the line X11-X11 in FIG. 81 when the solder resist SR3 is provided on the second main surface of the wiring board 2 of the card chip 1c in FIGS. 81 and 82. This example is the same as that described in the third embodiment. That is, both end portions in the longitudinal direction of each external connection terminal CB are covered with the solder resist SR3. As a result, as in the third embodiment, it is possible to suppress or prevent the peeling of the external connection terminal CB of the card chip 1c, and thus it is possible to reduce the occurrence rate of short circuit failure due to the peeling of the external connection terminal CB.

  Next, an example of a method for manufacturing the card chip 1c according to the ninth embodiment will be described with reference to FIGS. 84 to 89 show enlarged views of main parts on the first main surface side of the tape 15 for forming the wiring board during the manufacturing process of the card chip 1c.

  The tape 15 shown in FIG. 84 is formed using, for example, a flexible flat band-shaped thin insulating material 15a formed of, for example, polyimide resin or the like as a base, and is a first main body that is opposite to each other along the thickness direction. A surface and a second main surface. A plurality of card chip 1c forming regions (broken lines) are arranged on the tape 15 along the extending direction. In the second main surface of the tape 15, the external connection terminals CA and CB shown in FIG. 81 and the like are arranged in the formation area of each card chip 1c. Further, a through hole TH3 is formed in the formation region of each card chip 1c on the first main surface of the tape 15. A part of the back surface of the external connection terminals CA and CB is exposed from the through hole TH3.

  First, as shown in FIG. 85, after applying the adhesive 5 on the first main surface of the tape 15, as shown in FIG. 86, silver paste or lead (for example) is placed in the through hole TH3 on the SFM4 mounting region side. Pb) A conductor 45 such as a ball is filled. Subsequently, as shown in FIG. 87, the SFM 4 is mounted on the first main surface of the tape 15. At this time, with the position of the external terminal 4a of the SFM 4 and the through hole TH3 filled with the conductor portion 45 aligned, the back surface of the SFM 4 is pressed against the first main surface of the tape 15 and adhered to the tape 15 with the adhesive 5 At the same time, the external terminal 4a of the SFM 4 and the conductor portion 45 on the tape 15 side are joined. The adhesive 5 may be the one used for bonding the IC chip 3.

  Subsequently, as shown in FIG. 88, after the IC chip 3 is mounted on the first main surface of the tape 15, the pad of the IC chip 3 and the external connection terminal CA are connected by the wire W1 through the through hole TH3. Thereafter, as shown in FIG. 89, the IC chip 3 is sealed with the resin sealing body 6 by applying a potting resin or the like on the first main surface of the tape 15. Thereafter, each card chip 1c portion is cut out from the tape 15, and the cap 7 is put on to manufacture the card chip 1c.

  In the above example, the case where the conductor portion 45 is filled in the through hole TH3 in the mounting process of the SFM 4 has been described. However, the present invention is not limited to this. FIG. 90 shows a cross-sectional view of the SFM 4 before mounting. A conductor portion 45 made of, for example, a lead (Pb) ball or the like is joined to the external terminal 4a of the SFM 4 in advance. The conductor portion 45 joined to the external terminal 4a of the SFM 4 may be joined to the external connection terminal CB through the through hole TH3 as shown in FIG.

  As described above, also in the ninth embodiment, since it is only necessary to mount the SFM 4 prepared in advance on the tape 15, both functions of the IC card and the function of the memory card are provided. A high card chip 1c can be provided efficiently. Each process is performed at each stage while feeding the tape 15.

(Embodiment 10)
In the tenth embodiment, an example in which the arrangement of the IC chip 3 and the SFM 4 is reversed in the card chip 1c using the SFM 4 of the eighth embodiment will be described.

  FIG. 92 is an overall plan view of the inside of the card chip 1c according to the tenth embodiment viewed through the first main surface side, and FIG. 93 is a simplified overall plan view of the SFM 4 in FIG.

  In the card chip 1c of the tenth embodiment, the SFM 4 is arranged on the first main surface of the wiring board 2 directly behind the external connection terminal CA for the IC chip 3 in the same manner as in the sixth and seventh embodiments. On the first main surface of the substrate 2, the IC chip 3 is disposed on the side of the external connection terminal CB for SFM4. Wiring for power supply and / or signal for electrically connecting IC chip 3 and external connection terminal CA on the second main surface of card chip 1c is provided on wiring board 4c of SFM 4 of the tenth embodiment. A path is formed.

  That is, the pad of the IC chip 3 is electrically connected to the wiring L7 on the first main surface of the wiring board 2 of the card chip 1c through the wire W1. The wiring L7 is electrically connected to the external terminal 4ai on the back surface of the SFM 4. The configuration of the external terminal 4ai is the same as that of the external terminal 4a described in the eighth embodiment, etc., but this external terminal 4ai is connected to the wiring board through the wiring L3i formed on the first main surface of the wiring board 4c of the SFM4. 4c is electrically connected to the external terminal 4gi on the second main surface. The configuration of the external terminal 4gi is the same as that of the external terminal 4ai. The external terminal 4gi is electrically connected to the wiring L1 on the first main surface of the wiring board 2 of the card chip 1c, and further outside the second main surface of the wiring board 2 through the conductor portion in the through hole TH1. It is electrically connected to the connection terminal CA.

  Also in the case of the tenth embodiment, wiring paths (external terminals 4ai and 4gi and wiring L3i) connected to all the external connection terminals CA for the IC chip 3 may be formed in the SFM 4, or a part of them may be formed. A wiring path connected to the external connection terminal CA may be formed. When providing wiring paths for some external connection terminals CA on the wiring board 4c of the SFM 4, the wiring paths for other external connection terminals CA are the wiring of the card chip 1c as described in the sixth embodiment. It may be provided on the substrate 2. The configuration other than the above is the same as described in the eighth and ninth embodiments.

  In this tenth embodiment, as in the sixth embodiment, it is possible to cope with an increase in the area of the SFM 4. Further, compared to the sixth embodiment, the wiring length from the IC chip 3 to the external connection terminal CA can be shortened (the length of the wiring L3i can be shortened and the length of the wire W1 can be shortened). The parasitic capacitance can be reduced, and the operation performance and reliability of the IC chip 3 can be ensured. In addition, the wiring route for the IC chip 3 can be easily routed compared to the sixth embodiment.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the above description, the case where the invention made mainly by the present inventor is applied to the SIM card, which is the field of use behind the present invention, has been described. However, the present invention is not limited to this and can be applied in various ways. It can also be applied to cards.

  The semiconductor device of the present invention can be applied to the manufacturing industry of semiconductor devices used for card type information media.

Claims (17)

(A) a wiring board having a first surface and a second surface opposite to each other along the thickness direction;
(B) a semiconductor chip mounted on the first surface of the wiring board and having a memory circuit and a control circuit for controlling its operation;
(C) a resin sealing body coated on the first surface of the wiring board so as to seal the semiconductor chip;
A plurality of terminals electrically connected to the semiconductor chip are disposed on a part of the first surface of the wiring board, and at least a part of the plurality of terminals is formed of the resin sealing body. A semiconductor device which is exposed to the outside.   2. The semiconductor device according to claim 1, wherein at least one terminal of the plurality of terminals is electrically connected to a test terminal disposed on the second surface of the wiring board through a connection hole formed in the wiring board. A semiconductor device which is connected.   2. The semiconductor device according to claim 1, wherein a part of at least one of the plurality of terminals is exposed on a second surface of the wiring board through a connection hole formed in the wiring board, and the exposed portion thereof. Is a terminal for testing.   2. The semiconductor device according to claim 1, wherein at least one terminal of the plurality of terminals has regions having different widths.   5. The semiconductor device according to claim 4, wherein the terminals having the regions having different widths are formed on the wiring board, and are arranged on the second surface of the wiring board through connection holes arranged in a part of the terminals. A semiconductor device, wherein the semiconductor device is electrically connected to a test terminal.   6. The semiconductor device according to claim 5, wherein a bonding wire is connected to a region other than an arrangement region of the connection hole of the terminal. The semiconductor device according to claim 1,
The semiconductor chip includes a first semiconductor chip in which the memory circuit is formed and a second semiconductor chip in which the control circuit is formed in a state where the second semiconductor chip is stacked on the first semiconductor chip. Have
A connection configuration in which a desired terminal of the first semiconductor chip and a desired terminal of the second semiconductor chip are electrically connected to the same wiring on the first surface of the wiring board via bonding wires, respectively. A semiconductor device comprising: The semiconductor device according to claim 1,
The semiconductor chip includes a first semiconductor chip in which the memory circuit is formed and a second semiconductor chip in which the control circuit is formed in a state where the second semiconductor chip is stacked on the first semiconductor chip. Have
The desired terminal of the second semiconductor chip is electrically connected to the desired terminal of the first semiconductor chip through a bonding wire, and the desired terminal of the first semiconductor chip is connected to the first surface of the wiring board through the bonding wire. A semiconductor device having a connection configuration electrically connected to a desired terminal among the plurality of terminals.   2. The semiconductor device according to claim 1, wherein the plurality of terminals on the first surface of the wiring board are only terminals for a memory card circuit formed by the memory circuit and the control circuit. Semiconductor device.   2. The semiconductor device according to claim 1, wherein a terminal electrically connected to an external terminal for an IC card circuit is disposed among the plurality of terminals on the first surface of the wiring board. Semiconductor device. (A) a wiring board having a first surface and a second surface opposite to each other along the thickness direction;
(B) a semiconductor chip mounted on the first surface of the wiring board and having a memory circuit and a control circuit for controlling its operation;
(C) a resin sealing body coated on the first surface of the wiring board so as to seal the semiconductor chip;
A semiconductor device, wherein a plurality of terminals electrically connected to the semiconductor chip are arranged on the second surface of the wiring board so as to extend along one outer periphery of the second surface of the wiring board. The semiconductor device according to claim 11.
The semiconductor chip includes a first semiconductor chip in which the memory circuit is formed and a second semiconductor chip in which the control circuit is formed in a state where the second semiconductor chip is stacked on the first semiconductor chip. Have
The desired terminal of the first semiconductor chip and the desired terminal of the second semiconductor chip are electrically connected to the same wiring arranged on the first surface of the wiring board via bonding wires, respectively. A semiconductor device having a connection structure. The semiconductor device according to claim 11.
The semiconductor chip includes a first semiconductor chip in which the memory circuit is formed and a second semiconductor chip in which the control circuit is formed in a state where the second semiconductor chip is stacked on the first semiconductor chip. Have
The desired terminal of the second semiconductor chip is electrically connected to the desired terminal of the first semiconductor chip through a bonding wire, and the desired terminal of the first semiconductor chip is connected to the first surface of the wiring board through the bonding wire. A semiconductor device having a connection structure electrically connected to a desired terminal.   12. The semiconductor device according to claim 11, wherein the plurality of terminals on the second surface of the wiring board are only terminals for a memory card circuit formed by the memory circuit and the control circuit. Semiconductor device.   12. The semiconductor device according to claim 11, wherein a terminal electrically connected to an external terminal for an IC card circuit is disposed among the plurality of terminals on the second surface of the wiring board. Semiconductor device. (A) a wiring board having a first surface and a second surface opposite to each other along the thickness direction;
(B) a semiconductor chip mounted on the first surface of the wiring board and having a memory circuit and a control circuit for controlling its operation;
(C) a resin sealing body coated on the first surface of the wiring board so as to seal the semiconductor chip;
A plurality of terminals electrically connected to the semiconductor chip are arranged on the second surface of the wiring board,
Among the plurality of terminals on the second surface of the wiring board, a terminal electrically connected to an external terminal for an IC card circuit is disposed. The semiconductor device according to claim 16.
The semiconductor chip includes a first semiconductor chip in which the memory circuit is formed and a second semiconductor chip in which the control circuit is formed in a state where the second semiconductor chip is stacked on the first semiconductor chip. Have
The terminals of the first and second semiconductor chips have a connection structure that is electrically connected to a plurality of terminals disposed on the first surface of the wiring board through bonding wires,
The plurality of terminals on the first surface of the wiring board are electrically connected to the plurality of terminals on the second surface of the wiring board through connection holes formed in the wiring board. Semiconductor device.

Images