JPWO2006129356A1 - Information processing apparatus and error calculation detection method thereof - Google Patents

Abstract

The present invention relates to an apparatus and method for improving tamper resistance of an IC chip used in a smart card or a GSM mobile phone. In particular, in operations executed inside the IC chip, by limiting the register size that can be used by the user in real time, the calculation system is changed so that erroneous operations can be dynamically detected without adding physical memory. . The information processing apparatus of the present invention has a plurality of copies of the value by limiting the size of the general-purpose register used for the operation, and simultaneously processes the plurality of values by the arithmetic unit, and checks the resulting value Detects the erroneous operation of the arithmetic unit due to disturbance.

Description

  The present invention relates to an information processing apparatus and an error calculation detection method thereof, and more particularly, an IC used for smart cards, GSM mobile phones, and the like that have tamper resistance and perform high security for performing personal authentication and billing processing. The present invention relates to an information processing apparatus suitable for use in a chip and the like, and an erroneous calculation detection method thereof.

  The microcomputer operates with a clock signal and power input from the outside. If the clock signal and power are supplied as expected, it is designed to perform the calculation correctly. However, when the clock signal and power are unstable, the expected calculation cannot always be completed. Also, an attack method is known in which such an unstable state is intentionally created to generate an erroneous operation, and an attempt is made to decipher the cipher by a method as shown in Non-Patent Document 1 below. Therefore, it can be said that a module that performs cryptographic processing is particularly preferably configured so that no erroneous operation occurs or can be detected even if it occurs.

JP 2001-306346 A "On the Importance of Checking Cryptographic Protocols for Faults," Proc. Of EUROCRYPT'97, Lecture Notes in Computer Science, Advances in Cryptology, pp.37-51, 1997.

  Hereinafter, the relationship between the configuration of a general microcomputer processor and an erroneous operation will be described.

A processor mounted on a microcomputer includes a plurality of registers and an arithmetic and logical operation unit (hereinafter referred to as “ALU”) for performing an operation between the registers. The register is a temporary storage device that can be accessed by software in units of 8 bits, 16 bits, 32 bits, and is generally named and distinguished as R0, R1,..., R31. The ALU performs an operation between designated registers, and outputs an operation result to the designated register. What kind of calculation is performed is instructed by a machine language. Machine language is often defined to have little redundancy for the purpose of improving the mounting area. Therefore, it is difficult for humans to understand directly. Therefore, the operation is described in a language that can be understood by humans such as an assembler, and is translated into a machine language that can be interpreted by the processor by a compiler. For example, “add R0, R1” is an example of an operation described by an assembler. This description means that the values of registers R0 and R1 are added and the result is stored in R1. A detailed description of the procedure of operations performed internally by the processor is as follows.

step 1. Read R0 and set as input 1 of the adder.
step 2. Read R1 and set as input 2 of the adder.
step 3. Operate the adder and obtain the addition result of input 1 and input 2.
step 4. Write the addition result to R1.

  Therefore, after executing the addition instruction according to this description, the register R1 discards the previous value and holds the new result. In some cases, the input value may not be discarded by designating another register name of the output destination in addition to the two registers serving as input values.

  Here, the mechanism when an erroneous operation occurs is considered as follows. The values stored in the registers R0 and R1 are described as r0 and r1, respectively. For example, if the reading process of R0 is incorrect in step 1, not the value r0 but the value r0 ′ including the error is read. In this case, the values processed by the adder at step 3 are not originally intended r0 and r1, but r0 ′ and r1. Therefore, the value written to R1 in step 4 is not r0 + r1, but r0 ′ + r1. The same result is obtained when the read processing of R1 is incorrect in step 2. Even if the read processing of R0 and R1 is performed correctly, if the addition processing at step 3 is incorrect, the value written to R1 at step 4 will be different from the originally expected value. Furthermore, if the writing process to R1 is incorrect in step 4, the value held by R1 is still different from the originally expected value.

  As a basic method for inspecting whether or not there is an erroneous operation, there is a method in which the same operation is repeated a plurality of times and whether or not the results match is inspected. These multiple calculations may be performed by a method in which one processor is operated multiple times, or may be performed in parallel using a plurality of processors. However, in the method of performing the repetitive calculation twice or more with one processor, the processing time is increased at least twice, and in the method using a plurality of processors, the circuit is complicated and the mounting area is increased at least twice. Therefore, it is difficult to apply to a small device such as a smart card, which does not necessarily have a high calculation capability as compared with a personal computer or the like and whose mountable area is limited.

  As a conventional method for solving this problem, Patent Document 1 is cited.

Hereinafter, the outline of the processing of the arithmetic processing apparatus according to Patent Document 1 will be described with reference to FIG.
FIG. 2 is a block diagram showing the configuration of the arithmetic processing apparatus according to Patent Document 1. As shown in FIG.

  In this arithmetic processing unit, first, a conventional 2n-bit arithmetic unit 30 is configured to be separated into two n-bit arithmetic units 31 and 32 and can be used independently. When it is desired to detect an erroneous operation, after making a copy of the lower n bits 10 and 12 of the 2n bit register by the selection signals 150 and 151, the two n bit arithmetic units 31 and 32 respectively perform the operation. The comparator 41 confirms that the contents of the registers 14 and 15 for storing the results coincide with each other, thereby checking whether or not there is an erroneous operation, and notifies the result to the outside through the output line 400. However, in this method, if an attack is received during the period from when the register is transferred to the computing unit until the copy of the lower n bits is made, both values input to the two n-bit computing units are erroneous. Therefore, it is impossible to detect an erroneous operation. In addition, in order to increase the processing speed of the arithmetic unit, it has not been possible to cope with the case where a circuit for dividing a 2n-bit arithmetic unit into two n-bit arithmetic units cannot be added. .

  The present invention has been made to solve the above-described problems, and its purpose is to enable detection of an error that occurs during a period from when a value of a calculation source is stored to when it is transferred to a calculation unit. An object of the present invention is to provide an information processing apparatus capable of improving tamper resistance and increasing the calculation processing speed as compared with the prior art, and an erroneous calculation detection method thereof.

  The basic arithmetic processing of the information processing apparatus of the present invention is as follows.

Only when it is necessary to ensure security, the following processing is performed to detect an erroneous operation, and when security is not necessary, normal arithmetic processing is performed.
(1) The size of the register that can be used by the user is limited, and a copy of the data that cannot be used is created.
(2) Perform the operation with the original register size.
(3) The operation result of the copy source part is compared with the operation result of the copy destination.
(4) The comparison result is inspected to detect an operation error.

  Also, a special mode or special instruction is provided to the processor for executing the above.

  The processor is equipped with an erroneous operation detection mode (or an operational instruction capable of detecting an erroneous operation). When operating in this mode, the size of the internal register is limited, and the remainder of the register is simultaneously used to multiplex the operation results. An erroneous operation is detected by comparing. The error calculation detection mode and the normal mode can be switched by the user at any timing by preparing a special bit and setting it as the error calculation detection mode operation designation bit (or issuing an operation instruction capable of detecting an error calculation). be able to.

  The error calculation detection mode may be used particularly when security is required, for example, when a personal authentication process or billing process logic is run with a smart card or the like.

  According to the present invention, it is possible to detect an error that occurs during a period from when a value of an operation source is stored to when it is transferred to an arithmetic unit, thereby improving tamper resistance as compared with the prior art and reducing the processing speed. It is possible to provide an information processing apparatus capable of speeding up and a method for detecting an erroneous operation thereof.

  Hereinafter, each embodiment according to the present invention will be described with reference to FIGS. 1 and 3 to 14.

Embodiment 1
Hereinafter, a first embodiment according to the present invention will be described with reference to FIGS. 1, 3 to 7.

First, the general configuration of the information processing apparatus according to the first embodiment of the present invention will be described with reference to FIG.
FIG. 1 is a general configuration diagram of the information processing apparatus according to the first embodiment of the present invention.

  The information processing apparatus of the present embodiment includes a first n-bit register 10, a second n-bit register 11, a third n-bit register 12, a fourth n-bit register 13, and a fifth n-bit register. Register 14, sixth n-bit register 15, 2n-bit arithmetic unit 30, status register 16, first copy controller 20, second copy controller 21, inspection device 40, and inspection result output Line 400 is provided. As shown in FIG. 1, these are the first data line 102, the second data line 103, the third data line 104, the fourth data line 105, the fifth data line 106, and the sixth data line. 107 is connected.

  The first n-bit register 10 and the second n-bit register 11 are configured so that the two can be handled as a first 2n-bit register. The n-bit register 12 and the fourth n-bit register 13 are configured so as to be handled as a second 2n-bit register. The fifth n-bit register 14 and the sixth n-bit register 15 is configured to be handled as a third 2n-bit register.

  The first copy controller 20 can copy the contents of the second n-bit register 11 to the first n-bit register 10, and the second copy controller 21 can copy the contents of the fourth n-bit register 13. It can be copied to the third n-bit register 12. The arithmetic unit 30 receives the first 2n-bit register and the second 2n-bit register as inputs, performs a predetermined operation, and then updates the contents of the third 2n-bit register and the status register 16. The inspection device 40 receives the third 2n-bit register and the status register 16 as input, verifies the correctness of the processing of the arithmetic unit 30, and outputs the inspection result to the output signal line 400.

  This information processing apparatus has two types of modes, a normal operation mode and an error calculation detection mode, and operates by appropriately switching between these modes.

  The normal operation mode is an original operation mode in which a 2n-bit operation is performed by an arithmetic unit and a result is output. The error calculation detection mode is a mode for improving security and detecting an error calculation, and is a mode in which the calculator performs an n-bit calculation and outputs a result.

  The operation of the information processing apparatus of the present embodiment in the normal operation mode is as follows.

  The first n-bit register 10 and the second n-bit register 11 are treated as a first 2n-bit register, and the third n-bit register 12 and the fourth n-bit register 13 are a second 2n-bit register. Are treated as These two 2n-bit registers are processed in a 2n-bit arithmetic unit 30 and the operation result is stored in a third 2n-bit register including a fifth n-bit register 14 and a sixth n-bit register 15.

  In addition, the state such as the carry of the calculated value is stored in the state register 16. This operation is understood to be exactly the same as a general information processing apparatus including a 2n-bit arithmetic unit and a 2n-bit register. At this time, the information processing apparatus according to the present embodiment reduces the power consumption by stopping the operations of the first copy controller 20, the second copy controller 21, and the inspection apparatus 40, or uses these circuits. It can also be configured such that it can be continuously operated so that there is no change in the operating characteristics such as power consumption when it is present and when it is not being used.

  The operation of the information processing apparatus of this embodiment in the error calculation detection mode is as follows.

  The contents of the second n-bit register 11 are copied to the first n-bit register 10 by the first copy controller 20, and the contents of the fourth n-bit register 13 are copied to the third n-bit register 10 by the second copy controller 21. Copy to n-bit register 12. At this time, the values stored in the first n-bit register 10 and the third n-bit register 12 are overwritten. The first n-bit register 10 and the second n-bit register 11 are regarded as a first 2n-bit register, the third n-bit register 12 and the fourth n-bit register 13 are regarded as a second 2n-bit register, Processed by the 2n-bit computing unit 30, and the 2n-bit processing result is stored in a fifth n-bit register 14 and a sixth n-bit register 15 which are regarded as a third 2n-bit register. At the same time, the status register 16 is also updated.

  Next, the values of the third 2n-bit register 12 and the status register 16 are input to the inspection device 40. In the inspection apparatus 40, the input value is corrected and then compared to determine whether or not the processing in the arithmetic unit 30 has been normally performed, and the result is transmitted to the outside through the output signal line 400.

In this erroneous operation detection mode, an error in each of the following phases can be detected after the second n-bit register 11 and the fourth n-bit register are written.
(1) When the value of the second n-bit register 11 is copied to the first n-bit register 10 by the copy controller 20, or the value of the fourth n-bit register 13 is changed to the first value by the copy controller 21. When copying to n-bit register 12.
(2) During data transfer by the first data line 102 and the second data line 103.
(3) When data from the first data line 102 and the second data line 103 are written into the arithmetic unit 30.
(4) During calculation by the calculator 30.
(5) At the time of status transfer to the status register of the arithmetic unit 30 and at the time of writing.
(6) During transfer by the data line 104 from the arithmetic unit 30 to the third 2n-bit register.
(7) When data from the data line 104 is written to the third 2n-bit register.
(8) During transfer to the inspection apparatus by the data lines 105 and 106.

Next, a detailed configuration of the information processing apparatus according to the first embodiment of the present invention will be described with reference to FIGS. 3 to 7.
FIG. 3 is a diagram showing a register configuration of a general 32-bit CPU.
FIG. 4 is a diagram showing restrictions on register usage of the CPU in the error calculation detection mode of the information processing apparatus of the present invention.

  ER0 to ER6 are general-purpose registers, and normally can be freely used by the user as Ex (16 bits), RxH, RxL (each 8 bits), or as Rx (16 bits) or ERx (32 bits). In the information processing apparatus of the present invention, an erroneous operation detection mode is newly set as an operation mode of the CPU, and in this mode, as shown in FIG. 4, the user is restricted from using at least some of the Ex registers. . Further, the arithmetic operation using the Rx register is multiplexed in parallel using the same register, and the erroneous operation is detected by checking the result when the result of the arithmetic unit is output.

FIG. 5 and FIG. 6 are diagrams showing a connection relationship among the copy controller, the register, the arithmetic unit, and the inspection device.
The information processing apparatus shown in FIG. 5 includes a first data bus 110 and a second data bus 111, and each register and arithmetic unit are connected to these data buses. The first n-bit register 10 and the second n-bit register 11 can also be read as the first 2n-bit register, and the value of the read first 2n-bit register is the first data The data is input to the arithmetic unit 30 through the bus 110 and the first data line 102 or the second data line 103. If the arithmetic unit performs an operation for obtaining one result from two inputs, such as addition and multiplication, the third n-bit register 12 and the fourth n-bit register 13 are used.

  The value of the second 2n-bit register is read to the first data bus 110 and further input to the arithmetic unit 30 through the first data line 102 or the second data line 103. The operation result is sent to the second data bus 111 through the third data line 104 and stored in a third 2n-bit register including the fifth n-bit register 14 and the sixth n-bit register 15. In addition, the value of the state register 16 that stores the state of the operation is read out during the operation, and is rewritten according to the result of the operation.

  Next, the third 2n-bit register storing the operation result is sent to the inspection device 40 through the fourth data line 105 and the fifth data line 106, respectively, as two n-bit registers. At the same time, the contents of the status register 16 are also sent to the inspection device 40 through the sixth data line 107. The inspection device 40 uses these input values to inspect whether or not the processing by the arithmetic unit 30 has been performed correctly, and transmits the result to the outside through the output signal line 400. Here, an example in which the fifth n-bit register and the sixth n-bit register are read out independently using two data lines of the fourth data line 105 and the fifth data line 106 is shown. The values of the two registers do not necessarily need to be read separately, but can be read as a 2n-bit register and sent to the inspection device 40.

  On the other hand, the configuration of the information processing apparatus shown in FIG. 6 is different from the example shown in FIG. 5 in the connection location of the copy controller. Note that FIG. 6 particularly shows a copy controller unit that is different from the information processing apparatus shown in FIG. In the configuration of this information processing apparatus, the first copy controller 20 first receives data when writing data to the first n-bit register 10, the second n-bit register 11, or both, When it is necessary to write the same value as the first n-bit register 10 to the second n-bit register 11, the same value is output to the data lines 200 and 201.

  Values are written through the second data bus 111 in the case of data transfer from other registers or memories, or in the case of storing the result of the operation by the arithmetic unit. In this configuration, the copy controller 20 simultaneously Since values are written in the first n-bit register 10 and the second n-bit register 11, the normal state can be switched to the erroneous operation inspection state more quickly than the information processing apparatus having the configuration of FIG.

Further, as in the configuration shown in FIG. 7, a controller 60 for controlling the operations of the copy controllers 20 and 21 and the inspection apparatus 40 may be provided.
FIG. 7 is a block diagram of an information processing apparatus including a controller 60 for controlling the operations of the copy controllers 20 and 21 and the inspection apparatus 40.

  The information processing apparatus having the configuration shown in FIG. 7 receives an instruction from the input signal line 600 to the controller 60 and controls activation and stop of the copy controllers 20 and 21 and the inspection apparatus 40. In this way, by configuring the inspection function so that it can be switched between start and stop, if erroneous operation detection is required, the size of the register that can be used is limited, but erroneous operation detection is possible. When it is unnecessary, an information processing apparatus that can use a normal register size can be configured without increasing the register layout area.

  In the information processing apparatus according to the present embodiment, in the erroneous operation detection mode, the controller 60 restricts user access to the n-bit registers 11 and 13, so that the user can select n of the registers physically existing in 2n bits. Controls so that only bits are present. Therefore, it is possible to provide an information processing apparatus with higher reliability without being detected as an operation error when the user mistakenly rewrites the register.

[Embodiment 2]
Hereinafter, a second embodiment according to the present invention will be described with reference to FIGS. 8 and 9.

In the first embodiment, the information processing apparatus having a general arithmetic unit is described. However, in this embodiment, the arithmetic unit is specifically described as an adder, and a specific example of addition is shown. is there.
FIG. 8 is a configuration diagram of an information processing apparatus according to the second embodiment of the present invention.
FIG. 9 is a diagram showing a specific example of numerical values in the case of detecting an erroneous operation in addition.

  The information processing apparatus illustrated in FIG. 8 includes a mechanism that detects an erroneous operation of the adder. In the information processing apparatus of this embodiment, the first copy controller 20 copies the value of the second n-bit register 11 to the first n-bit register 10, and the second copy controller 21 uses the fourth n-bit register. The value of 13 is copied to the third n-bit register 12. The first n-bit register 10 and the second n-bit register 11 are combined into a first 2n-bit register, and the third n-bit register 12 and the fourth n-bit register 13 are combined into a second 2n. As a bit register, the 2n-bit adder 35 is used to add the first 2n-bit register and the second 2n-bit register, and the result is stored in the third 2n-bit register. The third 2n-bit register can also be handled as a fifth n-bit register 14 and a sixth n-bit register 15. Further, the state of operation is stored in the state register 16. The inspection device 40 includes a subtracter 45 having the fifth n-bit register 14 and the status register 16 as inputs, and a comparator 46 for comparing the output of the subtractor with the value of the sixth n-bit register 15. The comparison result is transmitted through the output signal line 400.

  Here, the values used in the adder are the lower value of the 2n-bit value on the second, fourth, and sixth n-bit register sides, and the 2n-bit value on the first, third, and fifth n-bit register sides. The embodiment is shown as an upper value of. For example, considering the case of n = 16, if an overflow occurs in the addition result, 0xF000 F000 + 0x1000 1000 = c 0x0001 0000 (0x is a hexadecimal number, and c is a carry), so the result value is retained. An error cannot be detected by simply comparing the registers. When an overflow occurs, it is necessary to perform a comparison process after subtracting 1 from the top. When an overflow occurs during the operation, a carry flag indicating that an overflow has occurred is generally set in the status register. Therefore, if the value of the carry flag is read from the status register and the result of subtraction from the value of the upper n bits of the 2n bits as the addition result is checked with the value of the lower n bits, has an error occurred? A determination of whether or not can be made.

  The specific example shown in FIG. 9 shows addition when the value of the first 2n-bit register is 0xc362 c362 and the value of the second 2n-bit register is 0xa18c a18c. The result of addition is 0xc362 c362 + 0xa18c a18c = c 0x64ed 64ec, and a carry occurs. Therefore, it is only necessary to subtract 1 from the value of the upper bits and verify whether or not they are equal to each other. If they are not equal, an error has occurred somewhere.

[Embodiment 3]
A third embodiment according to the present invention will be described below with reference to FIGS.

In the second embodiment, the arithmetic unit is specifically described as an adder, and a specific example of addition is shown. However, in this embodiment, the arithmetic unit is a multiplier and a specific example of multiplication is shown. is there.
10 and 11 are configuration diagrams of an information processing apparatus according to the third embodiment of the present invention.
FIG. 12 is a diagram showing a specific example of numerical values when detecting an erroneous operation in multiplication.

  The information processing apparatus shown in FIG. 10 includes a mechanism that detects an erroneous operation of the multiplier. The information processing apparatus according to the present embodiment includes a first sign inversion device 22 in the first copy controller 20, and a value obtained by sign inverting the value of the second n-bit register 11 is stored in the first n-bit register 10. Store. The second copy controller 21 copies the value of the fourth n-bit register 13 to the third n-bit register 12. The first n-bit register and the second n-bit register can be regarded as a first 2n-bit register, and the third n-bit register and the fourth n-bit register are collectively a second 2n-bit register. Can be considered.

  The multiplier 36 multiplies the two 2n-bit inputs by giving a 4n-bit output, and stores the result in the third 2n-bit register 17 and the fourth 2n-bit register 18. In the inspection device 40, the value of the third 2n-bit register 17 and the fourth 2n-bit register 18 are added by the adder 47, and the value of the second 2n-bit register is inspected, and the result is output to the output signal line 400. Communicate through.

A general 32-bit CPU has a multiply instruction that takes two 16-bit values as input values and outputs a 32-bit result. Therefore, if the processing is performed as described above, it is possible to perform an 8-bit × 8-bit operation including an erroneous operation inspection mechanism. The correctness of this calculation is confirmed as follows. Assume that k × m is calculated with k and m as 8-bit values. At this time, a, b, c, and d are each 8 bits, and a multiplier capable of calculating a | b × c | d is used. Here, a | b means a 16-bit value in which the upper 8 bits are a and the lower 8 bits are b. When a = b, k = c, d = m and multiplication a | b × c | d is performed, the upper 16 bits of the 32-bit result are −a × c and the lower 16 bits are a × c. Enters. However, it should be noted that a general-purpose computer does not necessarily have a dedicated register for codes. In this case, in order to express -k, 2 ^ 8-k is used (so-called two's complement expression), which is a value that causes the lower 8 bits to become zero by adding k and causes a carry. Here, ^ is a sign that decrements the power, and 2 ^ 8 represents 2 to the 8th power. As a result, a carry occurs when calculating -k + k. The effect of carry is
((2 ^ 8-k) × 2 ^ 8 + k) × (m × 2 ^ 8 + m)
= m (2 ^ 24 + 2 ^ 16)-mk (2 ^ 16-1>
= (m × 2 ^ 8 + m-mk) × 2 ^ 16 + mk
As a result, m | m is added to the upper 16 bits. Therefore, in the information processing apparatus of the present embodiment, an erroneous operation is detected by performing multiplication of the upper 16 bits and the lower 16 bits and confirming that it matches the 16-bit value c | d corresponding to m | m. .
Note that the above equation includes a subtractor in the inspection device, and subtracts the value of the second 2n-bit register from the upper 2n bits of the multiplication result, and the sum of the result and the lower 2n-bit value of the multiplication result is zero. This means that it is possible to check an erroneous operation even by a method for confirming that the information processing apparatus is configured as shown in FIG.

  The specific example shown in FIG. 12 is a case where the value of the second 8-bit register is 0x7f and the value of the fourth register is 0x56. The value of the second 8-bit register is inverted in sign and stored in the first 8-bit register, resulting in 0x81. The value of the fourth 8-bit register is copied to the third 8-bit register, resulting in 0x56. When these values are applied, 0x2bac is entered as the value of 0x81 × 0x56 + 0x56 (2 ^ 8 + 1) in the upper 16 bits, and 0x2aaa is entered as the value of 0x7f × 0x56 in the lower 16 bits. Therefore, if 0x56 (2 ^ 8 + 1) is left after these, it means that there is no error calculation and that it is operating normally.

[Embodiment 4]
Hereinafter, a fourth embodiment according to the present invention will be described with reference to FIGS. 13 and 14.
FIG. 13 is a diagram illustrating a physical structure of a flip-flop.
FIG. 14 shows a mounting arrangement example of the flip-flop integrated circuit.

  For example, it is assumed that a flip-flop having a physical structure as shown in FIG. 13 is used to store bit information of a register of the information processing apparatus of the present invention. Here, 2n flip-flops are used to hold the value of the 2n-bit register, and the n-bits of 2n are arranged so as to be covered by the remaining n bits. By arranging the two n-bit registers constituting the 2n-bit register so as to physically overlap in the vertical direction as shown in FIG. 14, the value of the register is affected by the incidence of light or the like from one direction. Even in such a case, since one of them protects the other and the incident component changes, an operation that changes to the same value can be prevented, and higher malfunction tolerance can be provided. .

1 is a general configuration diagram of an information processing apparatus according to a first embodiment of the present invention. It is a block diagram which shows the structure of the arithmetic processing apparatus which concerns on patent document 1. FIG. It is a figure which shows the register structure of a general 32-bit CPU. It is a figure which shows the register use restriction | limiting of CPU in the error calculation detection mode of the information processing apparatus of this invention. It is the figure shown about the connection relation of a copy controller, a register | resistor, a computing unit, and an inspection apparatus (the 1). It is the figure shown about the connection relation of a copy controller, a register | resistor, a computing unit, and an inspection apparatus (the 2). 2 is a block diagram of an information processing apparatus including a controller 60 for controlling operations of the copy controllers 20 and 21 and the inspection apparatus 40. FIG. It is a block diagram of the information processing apparatus which concerns on 2nd embodiment of this invention. It is the figure which showed the specific example of the numerical value in the case of detecting the erroneous calculation in addition. It is a block diagram of the information processing apparatus which concerns on 3rd embodiment of this invention (the 1). It is a block diagram of the information processing apparatus which concerns on 3rd embodiment of this invention (the 2). It is the figure which showed the specific example of the numerical value in the case of detecting the erroneous calculation in multiplication. It is a figure showing the physical structure of a flip-flop. The example of mounting arrangement in the integrated circuit of the flip-flop is shown.

Explanation of symbols

10, 11, 12, 13, 14, 15 ... n-bit register 16 ... status register 17, 18 ... 2n-bit register 20, 21 ... copy controller 22, 47 ... sign inversion device 30 ... 2n-bit calculator 31, 32 ... n Bit calculator 40 ... inspection device 41, 46 ... comparator 60 ... error calculation inspection mechanism control device

Claims (13)

In an information processing apparatus that performs an m-bit operation with a first m (m is a positive integer) bit register and a second m-bit register,
A copy controller,
An arithmetic unit;
An inspection device,
The copy controller uses the value of n (n is a positive integer, m> n) bits of the first n-bit register and the second n-bit register to determine the remaining mn bits of each register. To the area of
The computing unit computes and outputs the value of the first m-bit register and the value of the second m-bit register,
The information processing apparatus according to claim 1, wherein the inspection apparatus determines whether an erroneous operation has occurred based on an output of the arithmetic unit.   The information processing apparatus according to claim 1, wherein m is an even number and n = m / 2. The computing unit is an adder,
The inspection device comprises a subtractor and a comparator,
The copy controller copies the n-bit value of the first m-bit register and the second m-bit register to the remaining n-bit area of each register, respectively, and the same n-bit value;
The adder adds the values of the first m-bit register and the second m-bit register, and outputs the result.
When an overflow occurs in the addition result of the adder, 1 is subtracted from the value of the upper n bits of the m-bit value of the output of the adder and output,
3. The information processing apparatus according to claim 2, wherein the comparator detects an erroneous operation by comparing a lower n-bit value of the output of the subtracter and the output of the adder. The computing unit is a multiplier,
The inspection device comprises an adder and a comparator,
Furthermore, a sign inverting device is provided,
The sign inversion device copies the n-bit value of the value of the first m-bit register by inverting the sign to the remaining n-bit area,
The copy controller copies an n-bit value among the values of the second m-bit register to the remaining n-bit area,
Multiplying the first m-bit register and the second m-bit register by the multiplier and outputting a 2 m-bit value;
The adder adds the upper m-bit value and the lower m-bit value of the 2m-bit value of the multiplier output, and outputs the result.
3. The information processing apparatus according to claim 2, wherein the comparator detects an erroneous operation by comparing an output of the adder with a value of the second m-bit register. The computing unit is a multiplier,
The inspection device comprises an adder and a comparator,
Furthermore, a sign inverting device is provided,
The sign inversion device copies the n-bit value of the value of the first m-bit register by inverting the sign to the remaining n-bit area,
The copy controller copies an n-bit value among the values of the second m-bit register to the remaining n-bit area,
Multiplying the first m-bit register and the second m-bit register by the multiplier and outputting a 2 m-bit value;
The adder adds the upper m-bit value and the lower m-bit value of the 2m-bit value of the multiplier output, and outputs the result.
3. The information processing apparatus according to claim 2, wherein the comparator detects an erroneous operation by comparing an upper m-bit value and a lower m-bit value of the output of the adder. It has a register access controller,
The register access controller switches between a first mode and a second mode for calculating an m-bit register,
In the first mode, a predetermined n bits out of m bits are set as a calculation target of a user instruction,
2. The information processing apparatus according to claim 1, wherein in the second mode, predetermined n bits out of m bits are not set as a calculation target of a user instruction.   The information processing apparatus according to claim 1, wherein when it is determined that the erroneous operation has occurred, a reset operation is performed.   The information processing apparatus according to claim 1, wherein power consumption of the copy controller is constant.   2. The information processing apparatus according to claim 1, wherein a storage element that holds a bit of a copy source register is arranged so as to overlap a storage element that holds a bit of a copy destination register in a vertical direction. In an error detection method for an information processing apparatus that can use a 2n-bit register as two n-bit registers,
The lower part of the first 2n-bit register is the first n-bit register, the upper part is the second n-bit register,
The lower part of the second 2n-bit register is the third n-bit register and the upper part is the fourth n-bit register.
(1) copying the value of the first n-bit register to the second n-bit register;
(2) copying the value of the third n-bit register to the fourth n-bit register;
(3) performing an operation with the first 2n-bit register and the second 2n-bit register as inputs, and storing the result in a third 2n-bit register and a status register;
(4) An error of the information processing apparatus comprising the step of checking the validity of the operation by using the value of the upper n bits and the value of the lower n bits of the third 2n-bit register and the status register. Calculation detection method. The lower part of the third 2n-bit register is a fifth n-bit register, and the upper part is a sixth n-bit register,
The step (3) is a step of adding the first 2n-bit register and the second 2n-bit register and storing the result in a third 2n-bit register and a status register,
11. The information according to claim 10, wherein the step (4) is a step of subtracting a value of the status register from the sixth n-bit register and comparing it with a value of a fifth n-bit register. A method for detecting an erroneous operation of a processing apparatus. In an error detection method for an information processing apparatus, a 2n-bit register can be used as two n-bit registers, and a 4n-bit register can be used as two 2n-bit registers.
The lower part of the first 2n-bit register is the first n-bit register, the upper part is the second n-bit register,
The lower part of the second 2n-bit register is the third n-bit register, the upper part is the fourth n-bit register,
The lower part of the first 4n-bit register is the third 2n-bit register and the upper part is the fourth 2n-bit register.
(1) The value of the first n-bit register is inverted and copied to the second n-bit register;
(2) copying the value of the third n-bit register to the fourth n-bit register;
(3) multiplying the value of the first 2n-bit register by the value of the second 2n-bit register and storing the result in the first 4n-bit register;
(4) a step of adding and outputting the value of the third 2n-bit register and the value of the fourth 2n-bit register, and (5) the addition result of the step of (4) and the second 2n-bit register. A method of detecting an erroneous operation of an information processing apparatus, comprising the step of comparing the values of the information processing apparatuses. In an error detection method for an information processing apparatus, a 2n-bit register can be used as two n-bit registers, and a 4n-bit register can be used as two 2n-bit registers.
The lower part of the first 2n-bit register is the first n-bit register, the upper part is the second n-bit register,
The lower part of the second 2n-bit register is the third n-bit register, the upper part is the fourth n-bit register,
The lower part of the first 4n-bit register is the third 2n-bit register and the upper part is the fourth 2n-bit register.
(1) The value of the first n-bit register is inverted and copied to the second n-bit register;
(2) copying the value of the third n-bit register to the fourth n-bit register;
(3) multiplying the value of the first 2n-bit register by the value of the second 2n-bit register and storing the result in the first 4n-bit register;
(4) A step of adding and outputting the value of the third 2n-bit register and the value of the fourth 2n-bit register, and (5) an upper 2n-bit value of the addition result of the step (4) and a lower-order A method of detecting an erroneous operation of an information processing apparatus, comprising a step of comparing 2n-bit values.

Images