JPWO2006035500A1 - Data storage system and memory card - Google Patents

Abstract

  For example, in the case where the memory content on the target side is 5A′h and the memory content is updated to 5B′h by data transfer from the initiator to the target, for example, the initiator is updated toward the target. The data 01'h indicating the presence / absence of update for each bit is transmitted with the bit set to '1' and the bit without update to '0', and the target receives the data of 01'h and receives the data of its own memory The data of the bit corresponding to the updated bit (in this case, the last bit) is inverted and stored again.

Description

  The present invention relates to a data storage system and a memory card, and more particularly to a technique effective when applied to a data storage system including a storage device represented by a memory card and an initiator for reading and writing data to and from the storage device. .

  According to a study by the present inventor, the following technologies can be considered for the data storage system.

  For example, various memory card standards such as SD (Secure Digital) memory card and Memory Stick (registered trademark), USB (Universal Serial Bus) and IEEE (the Institute of Electrical and Electronics Engineers) 1394 network communication type communication type such as 1394. In the bus standard and storage-related standards such as ATA (AT Attachment) and SCSI (Small Computer System Interface), data transfer on the bus is performed using raw data that is not particularly optimized.

  That is, for example, data transfer as shown in FIG. 6A and 6B are diagrams for explaining an example of the data transfer method in the conventional data storage system examined as a premise of the present invention. FIG. 6A is a simplified diagram of the system configuration, and FIG. 6B is an operation flow diagram. is there. In FIG. 6, the data transmission side is an initiator 60, the reception side is a target 61, and the initiator 60 is a memory space having a value of 5A'h (hexadecimal "5A", the same notation is used hereinafter) of the target 61. In this example, 1-byte data A (= 5B′h) is written at address N (N is an integer of 0 or more). In this case, the following processes (1) to (6) are performed.

  (1) The initiator 60 sets a write head address (= N) and a write size (= 1 byte) in the target 61, and transmits a write command.

  (2) Upon receiving a write command from the initiator 60, the target 61 analyzes the content and extracts the write address and size.

  (3) After extraction, the target 61 prepares for data reception from the initiator 60.

  (4) The initiator 60 transmits raw data A (= 5 B′h) to the target 61.

  (5) The target 61 receives data A from the initiator 60.

  (6) The target 61 updates its corresponding memory space (here, one byte from address N) to data A.

  By the way, as a result of examination by the present inventor on the technology of the data storage system as described above, the following has been clarified.

  For example, in the data transfer method as described in FIG. 6, since raw data is transferred between the initiator and the target, the change in the data content of the corresponding address is particularly small before and after the transfer. For example, the following problems occur.

  (1) On the target side, when the received data is written and updated in its own memory or register, if all are overwritten, power and time are wasted. Further, in the data bus, the logic signals of “H” and “L” change with high frequency, so that noise and useless power are generated.

  (2) Therefore, on the target side, a method of updating data by focusing only on the bit to be updated can be considered, but it takes time to detect the bit to be updated. That is, the efficiency of data update is improved by using a method of inverting only the bits that need to be updated. However, when this method is applied, when detecting the bit to be inverted based on the raw data, it is necessary to compare the contents of the memory before update with the contents of the raw data, resulting in a reduction in efficiency.

  (3) In general, access to the memory is often performed by system software such as a device driver. Since system software is created in a language suitable for bit operations such as assembler language and C language, it is not efficient to handle raw data.

  Accordingly, an object of the present invention is to provide a data storage system and a memory card capable of improving the time efficiency when storing data.

  Another object of the present invention is to provide a data storage system and a memory card that can save power when data is stored.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  In the data storage system according to the present invention, an initiator that transmits first data having different signal levels when data inversion is required and data holding is required, and second data is stored in advance. And a target for updating the second data by inverting or holding the second data based on the signal level of the first data.

  In other words, when updating the target memory, etc., whether to update the data already stored in the target memory, etc., instead of updating by sending raw data to the target as in the prior art Update is done by sending information on whether or not. As a result, in the target memory or the like, for example, the process of overwriting and updating 'H' data to 'H' data or 'L' data to 'L' data can be reduced. It becomes possible to improve the efficiency of electric power.

  Here, examples of the target include a storage device.

  A data storage system according to the present invention includes an initiator that transmits data and a target that receives the transmitted data. Then, the initiator corresponds to the first signal level and the second signal level for the bit that needs to be inverted and the bit that does not need to be inverted with respect to the second data of the plurality of bits stored in the target. The plurality of bits of the first data are formed, and the plurality of bits of the first data are transmitted to the target. On the other hand, the target receives first data of a plurality of bits, detects a bit corresponding to the first signal level from the received first data of the plurality of bits, and for the second data of the plurality of bits, The storage of the second data is updated by inverting the bit data corresponding to the detected bit.

  That is, for example, when writing 1-byte data from the initiator to the target memory or the like, when there is a bit having the first signal level among the 8 bits in the 1-byte, The bit data in the memory or the like corresponding to the bit is inverted, and the data in the memory or the like is updated.

  Here, in the target, for example, system software processing is performed using a computer provided in the target, and the system software processing is performed by setting the signal level of each bit with respect to the first data of a plurality of bits. Only when the signal level of the determined bit and the determined bit is the first signal level, the bit data corresponding to the determined bit is read from the second data of the plurality of bits, and the read And a step of inverting the data and writing back.

  That is, the function of determining the signal level of data received by the target by processing of system software such as a device driver and controlling writing to the memory or the like based on the determination result is realized.

  The memory card according to the present invention stores the write address when a command including the write address and data assigned with different signal levels corresponding to inversion or retention of data are input from the initiator. The data stored in the write address is updated by inverting or holding the stored data based on the signal level of the input data.

  Here, examples of the memory card include an SD memory card and an MMC card. In this case, a new write command to a block or a plurality of blocks may be provided as the command using a protocol similar to a write command to a block or a plurality of blocks generally provided in such a memory card.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  Improving the time efficiency when storing data by transferring data with different signal levels depending on whether the data in the target memory or the like is inverted and retained from the initiator to the target It becomes possible. Furthermore, it is possible to save power when storing data.

1 is a system schematic diagram showing an example of the configuration of a data storage system according to an embodiment of the present invention. FIG. 5 is a conceptual diagram for explaining a data transfer method between an initiator and a target in comparison with a conventional technique in a data storage system according to an embodiment of the present invention. In the data storage system by one embodiment of this invention, it is a figure which shows an example of the operation | movement, (a) is a simplified diagram of system configuration, (b) is an operation | movement flowchart. In the data storage system according to an embodiment of the present invention, it is a diagram comparing the system software processing of the target in the case of using the conventional data transfer method and the case of using the data transfer method of the present invention, (A) is an example of a processing flow when the conventional technique is used, and (b) is an example of a processing flow when the present invention is used. In the data storage system of one embodiment of this invention, it is explanatory drawing which shows an example of the command specification of the memory card defined when using a memory card as a target, (a) is a specification example of CMD60, (b ) Shows a specification example of CMD61. In the data storage system of the prior art examined as a premise of the present invention, it is a figure explaining an example of the data transfer system, (a) is a simplified diagram of the system configuration, (b) is an operation flow diagram.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is a system schematic diagram showing an example of the configuration of a data storage system according to an embodiment of the present invention. The data storage system shown in FIG. 1 includes an initiator 10 that transmits data and a target 11 that receives data, and the initiator 10 and the target 11 are connected by a communication network 12. Examples of the initiator 10 and the target 11 include a memory card host device, a USB device, and an IEEE 1394 device.

  The initiator 10 and the target 11 have the same configuration, for example, an application 13a, a file system 13b, a device driver 13c, an interface controller 13d, and a storage unit 13e including a memory and / or a register. Is included.

  The application 13a is software such as an explorer having a function of operating folders and files, an audio player having a music data reproduction function, and the like. The file system 13b is system software that converts data input / output via the device driver 13c into a file so that processing can be performed by the application 13a, for example. Specific examples include those conforming to FAT (File Allocation Table) such as FAT16 and FAT32. The device driver 13c is software that performs control of the interface controller 13d, management of transactions and command sequences, and the like.

  Although not shown in FIG. 1, the initiator 10 and the target 11 include, for example, a computer such as a microprocessor, and thereby the software as described above is executed. Further, the software as described above may be configured such as an OS including a file system, an application, and a device driver when the initiator 10 and the target 11 are PCs (Personal Computers) or the like.

  The interface controller 13d is hardware that performs command transmission, response reception, data transmission / reception, and the like via the communication network 12 that connects the initiator 10 and the target 11. Examples of the communication network 12 include a wiring line to a memory card, a USB cable, an IEEE 1394 cable, and the like, and data transfer is performed by an electrical signal on the communication network 12. The memory of the storage unit 13e stores, for example, files and data necessary for the system, and the register is used for specific applications such as device operation control.

  The data transfer between the initiator 10 and the target 11 is not necessarily performed using a wired communication network. For example, the data transfer may be performed wirelessly using the interface controller 13d as a wireless controller.

  In such a system configuration, the feature of the present invention resides in that a new function is provided to the device driver 13c and the interface controller 13d to cope with a new data transfer method as shown in FIG. FIG. 2 is a conceptual diagram for explaining the data transfer method between the initiator and the target in comparison with the prior art in the data storage system according to the embodiment of the present invention.

  In FIG. 2, for example, it is assumed that the memory content on the target side is 5A'h, and the memory content is updated to 5B'h by data transfer from the initiator to the target. First, in the prior art, 5B′h (binary “01011011”), which is raw data, is transferred from the initiator to the target, and the memory content on the initiator side is overwritten and stored in 5B′h.

  On the other hand, in the present invention, data indicating whether or not each bit is updated is transferred from the initiator to the target. That is, in FIG. 2, when “1” (“H” level) is set to the bits with update and “0” (“L” level) is set to the bits without update, only the last bit is updated. Therefore, the data 01'h is transferred. Then, the target side receives the data 01'h, inverts the data of the bit corresponding to the updated bit (the last bit in this case) from the data of its own memory contents, and stores it again.

  Usually, in various memory card standards for SD memory cards, memory sticks, etc., serial bus standards such as USB and IEEE 1394, and storage standards such as ATA and SCSI, data is assigned to addresses assigned to memories and registers. One-to-one correspondence. Access to the memory and registers is processed with a bitmap image.

  Therefore, the data is considered as a bitmap image, and the bit that is updated (inverted) by data transfer is changed to ‘1’, and the bit that holds the value is changed to ‘0’. Then, data having bit information to be updated (inverted) is transferred to the target. As a result, when there is little change in the data content, it is easy to update the value of the memory or register in bit units, and it is possible to improve the efficiency of data update. Specifically, for example, the following effects can be obtained.

  (1) When the received data is written and updated in its own memory or register, it is easy and efficient to detect bits that need to be updated, and processing can be performed at high speed. Furthermore, when writing and updating, it is sufficient to write only to the bits that need to be updated. Therefore, for example, in a situation where there are few bits that need to be updated, the writing time can be shortened compared to the case where all bits are overwritten and updated, and the power associated with writing can be saved.

  (2) Since the frequency with which the logic signal changes in the data bus can be reduced, the generation of noise and wasteful power can be suppressed.

  (3) Since data suitable for bit operation is received, processing by system software can be performed efficiently.

  (4) The time for writing and updating received data is shortened, and this time can be allocated to other functions of the product (decoding multimedia data, etc.).

  (5) The entire system including the initiator and the target can save power. In addition, the system development period (especially software) can be shortened.

  Such an effect becomes more significant as the number of locations to be updated in the transferred data is smaller. In general, when updating and saving sentences, there are few parts to be updated. Therefore, the present invention is particularly useful when applied to a storage device for storing data such as a USB flash memory or a hard disk such as an ATA connection.

  Further, the present invention is not limited to this, and the present invention can be applied to all products in which data to be transferred and corresponding addresses of the memory / register are associated one-to-one. Particularly, the update of the system area of the file system is performed in units of sectors (512 bytes or the like), and the portion to be updated is as small as about 2 to 3 bytes, and has the one-to-one correspondence described above. . Therefore, the effect becomes large when applied to a product having such a file system.

  Next, an example of the operation of the entire data storage system using the data transfer method as described above will be described with reference to FIG. FIG. 3 is a diagram showing an example of the operation of the data storage system according to the embodiment of the present invention, where (a) is a simplified diagram of the system configuration and (b) is an operation flow diagram.

  3A and 3B, the initiator 30 has 1-byte data A (= 5B′h) at the N address (N is an integer of 0 or more) of the memory space having the value of 5A′h in the target 31. ) Is assumed. The operation will be described below in correspondence with the numbers in FIG.

  (1) The initiator 30 sets a write head address (= N) and a write size (= 1) to the target 31 and transmits a write command.

  (2) Upon receiving a write command from the initiator 30, the target 31 analyzes the content and extracts the write address and size.

  (3) After extraction, the target 31 prepares to receive data from the initiator 30.

  (4) The initiator 30 transmits data A ′ (= 01′h (“00000001” in binary number)) having information on bits that need to be updated to the target 31. In this case, since the data change ('0' → '1' or '1' → '0') is smaller than when the raw data A (= 5B'h (binary number "01011011")) is transferred. Data bus noise can be suppressed.

  (5) The target 31 receives data A ′ from the initiator 30.

  (6) The target 31 updates its corresponding memory to data A. When updating the data, a method of inverting only the bits that need to be updated is used. However, since the data A ′ itself has information on the bits that need to be updated, the updating method can be easily used. Become.

  That is, by using the data transfer method of the present invention, the system software processing on the target side associated with such an updating method becomes easy and efficient as shown in FIG. FIG. 4 compares the target system software processing in the data storage system according to the embodiment of the present invention when the conventional data transfer method is used and when the data transfer method of the present invention is used. FIG. 4A is an example of a processing flow when the conventional technique is used, and FIG. 4B is an example of a processing flow when the present invention is used.

  Here, a case where the contents (= data N) of the N address of the target 31 are updated will be described as an example. First, in the prior art, for example, a processing flow as shown in FIG. 4A is performed, and the following processing is performed.

  In S401a, the target 31 receives the data A. Then, the process proceeds to S402a.

  In S402a, data N is extracted from the memory of the target 31 for updating the data at address N. Then, the process proceeds to S403a.

  In S403a, a bit extraction counter is initialized. Then, the process proceeds to S404a.

  In S404a, the I-th bit of data A is extracted and is designated as A [I]. Then, the process proceeds to S405a.

  In S405a, the I-th bit of data N is taken out and is designated as N [I]. Then, the process proceeds to S406a.

  In S406a, it is compared whether N [I] and A [I] are different from each other. If they are different, the process proceeds to S407a. Otherwise, the process proceeds to S408a.

  In S407a, if they are different from each other as a result of comparison, the data corresponding to the I-th bit of the N address in the target memory is inverted. Then, the process proceeds to S408a.

  In step S408a, it is determined whether the bit extraction counter is valid. If it is valid, the process proceeds to S409a, and if not, the process ends.

  In S409a, if the bit extraction counter is valid, it is incremented by one. And it transfers to S404a and repeats a process.

  On the other hand, in the present invention, for example, the processing flow shown in FIG. 4B is performed, and the following processing is performed.

  In S401b, the target 31 receives the data A '. Then, the process proceeds to S403b.

  In S403b, a bit extraction counter is initialized. Then, the process proceeds to S404b.

  In S404b, the I-th bit of the data A 'is taken out and set as A' [I]. Then, the process proceeds to S406b.

  In S406b, it is determined whether A ′ [I] is “1”. If so, the process proceeds to S407b, and otherwise, the process proceeds to S408b.

  In S407b, if the result of determination is “1”, the data corresponding to the I-th bit of address N in the memory of the target 31 is inverted. Then, the process proceeds to S408b.

  In S408b, it is determined whether the bit extraction counter is valid. If it is valid, the process proceeds to S409b, and if not, the process ends.

  In S409b, if the bit extraction counter is valid, it is incremented by one. And it transfers to S404b and repeats a process.

  As described above, by using the data transfer method of the present invention, the process of extracting the data N in S402a and the process of extracting the I-th bit of the data N in S405a can be omitted as compared with the prior art. As a result, the processing of the system software and the hardware processing accompanying this software processing become easy and efficient.

  Next, an example will be described in which the data transfer method as described above is applied to a card system that targets a memory card such as an SD memory card or an MMC (MultiMediaCard (registered trademark)) card.

  In the SD memory card standard or the MMC card standard, CMD24 (= WRITE_BLOCK) is defined as a write command to a block, and CMD25 (= WRITE_MULTIPLE_BLOCK) is defined as a write command to a plurality of blocks. Therefore, a command reserved in the SD memory card standard or the MMC card standard is used as a write command to which the data transfer method of the present invention is applied.

  That is, for example, CMD60 (= DIFFERENTIAL_WRITE_BLOCK) is defined as a write command to the block, and CMD61 (DIFFERENTIAL_WRITE_MULTIPLE_BLOCK) is defined as the write command to a plurality of blocks. The write command protocol between the initiator and target using CMD60 and CMD61 is exactly the same as that of CMD24 and CMD25, respectively, and only the data content is changed to one having bit inversion information. That is, the command formats of CMD60 and CMD61 are as shown in FIGS. 5 (a) and 5 (b), respectively.

  5A and 5B are explanatory diagrams showing an example of command specifications of a memory card defined when a memory card is used as a target in the data storage system according to the embodiment of the present invention. a) shows a specification example of CMD60, and (b) shows a specification example of CMD61.

  As shown in FIG. 5A, the CMD 60 is an addressc (addressed (point-to-point) data transfer commands) type command. In this type, a command is issued to a specific memory card designated from the CMD line, and after the specific memory card returns a response, data transfer to the memory card is performed through the DAT line. By this data transfer, in the memory card, data writing for the block size specified by the SET_BLOCKLEN command is performed from the address specified by the argument when the CMD60 is issued. The data transferred to the memory card is data having bit inversion information as described above.

  On the other hand, as shown in FIG. 5B, the CMD 61 is an adtc type command as with the CMD 60. Then, by data transfer from the host to the memory card, the memory card continuously writes data from the address specified by the argument when issuing the CMD61, and writes to a plurality of blocks until it is stopped by the STOP_TRANSMISION command. Is called. The data transferred to the memory card is data having bit inversion information as described above.

  In this manner, a new command is defined in a memory card such as an SD memory card or an MMC card, and a command determination function or a function for processing the bit inversion information as described above is a function for responding to the command in the memory card. Etc., the data transfer efficiency of the memory card can be improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The data storage system and memory card of the present invention are particularly useful when applied to a data storage system including various memory cards such as an SD memory card and a memory stick, and a serial transfer storage device such as a USB flash memory. Further, the present invention is not limited to these, and various storage devices such as a hard disk such as an ATA connection, a memory card host device such as SD audio, a DVD drive connected by IEEE 1394, and a storage medium, not limited to a storage device. Is widely applicable to data storage systems including various devices assigned one-to-one.

Claims (9)

An initiator that transmits first data having different signal levels when data inversion is required and data holding is required;
Second data is stored in advance, the first data is received, and the stored second data is inverted or held based on the signal level of the first data, thereby storing the stored second data A data storage system having a target to be updated. The data storage system of claim 1, wherein
The data storage system, wherein the target is a storage device. A data storage system having an initiator for transmitting data and a target for receiving the transmitted data,
The initiator corresponds to the first signal level and the second signal level, respectively, for a bit that needs to be inverted and a bit that does not need to be inverted with respect to second data of a plurality of bits stored in the target. Forming a plurality of bits of first data, transmitting the plurality of bits of first data to the initiator,
The target receives the first data of the plurality of bits, detects a bit corresponding to the first signal level from the received first data of the plurality of bits, and outputs the second data of the plurality of bits. Then, the data storage system updates the storage of the second data of the plurality of bits by inverting the data of the bit corresponding to the detected bit. The data storage system of claim 3, wherein
In the target, software processing is performed using a computer provided in the target,
The processing of the software is as follows:
Determining a signal level of each bit for the plurality of first bits of data;
Only when the signal level of the determined bit is the first signal level, the bit data corresponding to the determined bit is read from the second data of the plurality of bits, and the read data is inverted. And a step of writing back the data storage system. The data storage system according to claim 3 or 4,
The data storage system, wherein the target is a storage device including a file system.   When an initiator receives a command including a write address and data assigned with different signal levels corresponding to data inversion or retention, the data stored in the write address is input. A memory card, wherein the data stored in the write address is updated by inversion or holding based on the signal level of the data. The memory card according to claim 6, wherein
The memory card is an SD memory card or an MMC card. The memory card according to claim 7,
The memory card according to claim 1, wherein the command is a write command to a block. The memory card according to claim 7,
The memory card, wherein the command is a write command to a plurality of blocks.

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